Abstract: A dynamic random-access memory array includes a plurality of memory cells and sensor cells physical arranged in a row. The sensor cells include a transistor and a capacitor having an input terminal connected to a first non-gate terminal of the transistor. A wordline is connected to transistor gates of both the memory cells and sensor cells in the row. A sensor amplifier has inputs connected to the sensor cell, a high voltage reference line, and a low voltage reference line, and an output in communication with a row refresh circuit. If the sensor amplifier detects that the sensor cell voltage falls outside of the range of the high and low voltage reference lines, then a trigger signal is output to request that the row refresh circuit perform a priority row refresh of the memory cells and the sensor cell in the row.

Abstract: Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes performing a read operation on a non-volatile memory to obtain a first value. The method further includes comparing the value to a predetermined value to obtain a comparison result. The method further includes determining whether a boot image stored on the non-volatile memory is to be read based at least on the first comparison result. The method further includes performing, based on the determining, a read operation on the boot image to obtain data associated with booting of a device. The method further includes booting the device based at least on the data. Related systems and devices are provided.

Abstract: Disclosed are devices and methods for periodically powering up a storage device(s) (SSDs) associated with a vehicle to avoid and prevent data loss. The disclosed embodiments provide mechanisms for preserving stored data collected during the running of a vehicle without requiring the main power supply to be routed through the CPU. Through the improved configuration and application of the disclosed power management integrated circuitry (PMIC), storage devices of a vehicle are enabled to be provided direct power and refreshed without powering on the vehicle (e.g., starting the car). The PMIC also ensures that the necessary power can be provided to and maintained to the storage device(s) in the event of an unexpected power loss.

Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

Abstract: Aggressor rows may be detected by comparing access count values of word lines to a threshold value. Based on the comparison, a word line may be determined to be an aggressor row. The threshold value may be dynamically generated, such as a random number generated by a random number generator. In some examples, a random number may be generated each time an activation command is received. Responsive to detecting an aggressor row, a targeted refresh operation may be performed.

Abstract: A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data may be retrieved from a memory array for the pattern matching operation by a read operation, a refresh operation, an error correction operation, and/or a pattern matching operation. The data may be retrieved from incoming data input lines instead of or in addition to the memory array. How the data is stored or retrieved for pattern matching operations may be controlled by a memory controller.

Abstract: A dynamic memory system having multiple memory regions respectively storing multiple types of data. A controller coupled to the dynamic memory system via a communication channel and operatively to: monitor usage of a communication bandwidth of the communication channel; determine to reduce memory bandwidth penalty caused by refreshing the dynamic memory system; and in response, reduce a refresh rate of at least one of the memory regions based on a type of data stored in the respective memory region.

Abstract: A memory apparatus comprises: a sampling circuit for sampling an input address through a sampling method corresponding to a first selection signal among at least two sampling methods, a storage circuit for storing up to N number of addresses having different values among sampled addresses received from the sampling circuit, an arranging circuit for determining an output sequence of addresses stored in the storage circuit through an arranging method corresponding to a second selection signal among the two arranging methods, and setting, as a target address, an address outputted according to the output sequence, a selection control circuit for setting each of the first selection signal and the second selection signal based on a state of the storage circuit, and a refresh operation circuit for controlling a target refresh operation on a row of memory cells corresponding to the target address.

Abstract: A memory system includes: a memory controller suitable for: generating a normal refresh command and a target refresh command when a number of inputs of an active command reaches a certain number, and providing the active command, the normal refresh command, the target refresh command, and an address; and a memory device including a plurality of banks and suitable for: performing a target refresh operation on one or more word lines of at least one bank in response to the target refresh command, determining a row hammer risk level per bank by counting, within a periodic interval, a number of inputs of the target refresh command per bank based on the address, and performing a hidden refresh operation corresponding to the row hammer risk level per bank in response to the normal refresh command.

Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.

Abstract: According to one embodiment, a memory device includes: a variable resistance memory region; a semiconductor layer; an insulating layer; first and second word lines; and a first select gate line. When information stored in the first memory cell is read, or when information is written into the first memory cell, after a voltage of the first select gate line is set to a first voltage and voltages of the first and second word lines are set to a second voltage, the voltage of the first select gate line is increased from the first voltage to a third voltage. After the voltage of the first select gate line is increased to at least the second voltage, the voltage of the first word line is decreased from the second voltage to the first voltage, and the voltage of the second word line is increased from the second voltage to a fourth voltage.

Abstract: A memory system includes: a plurality of memory chips each including a plurality of banks and each suitable for generating a tracking address by tracking a row-hammer risk of selected banks among the banks, encrypting the tracking address using an encryption key to output tracking information to a corresponding data bus of a plurality of data buses and performing a target refresh operation according to a row-hammer address transferred through a command/address bus; and a memory controller suitable for collecting the tracking information for the banks transferred through the plurality of data buses to generate and output the row-hammer address to the command/address bus.

Abstract: A clock correction circuit in which a correction accuracy of a duty cycle is increased is provided.

Abstract: An electronic device includes an intelligent refresh control circuit generating an intelligent refresh pulse with a pulse that has a generation period that is adjusted based on the number of generations of an auto refresh signal during an intelligent refresh operation, and an internal refresh signal generation circuit outputting one of a self-refresh pulse including a pulse that is periodically generated by an enable signal during a self-refresh operation and the intelligent refresh pulse as an internal refresh signal.

Abstract: A method and memory device of controlling a plurality of low power states are provided. The method includes: entering a low power mode state, in which memory cell rows of the memory device are refreshed and power consumption is lower than in a self-refresh mode state, in response to a low power state entry command; and exiting the low power mode state based on a low power mode exit latency time that is set in a mode register of the memory device or at least one of an alarm signal and a low power mode exit command.

Abstract: A processing device in a memory system assigns a memory page to a sensitivity tier of a plurality of sensitivity tiers. The processing device determines respective scan intervals for the plurality of sensitivity tiers, wherein the respective scan intervals are based on at least one characteristic of a memory device, the at least one characteristic comprising memory cell margins of the memory device. The processing device scans a subset of a plurality of memory pages, wherein the subset comprises a number of memory pages from each sensitivity tier identified according to the respective scan intervals.

Abstract: An electronic device includes a memory having a plurality of memory rows and a memory refresh functional block that performs a victim row refresh operation. For the victim row refresh operation, the memory refresh functional block selects one or more victim memory rows that may be victims of data corruption caused by repeated memory accesses in a specified group of memory rows near each of the one or more victim memory rows. The memory refresh functional block then individually refreshes each of the one or more victim memory rows.

Abstract: A method includes monitoring a temperature of a memory component of a memory sub-system to determine that the temperature of the memory component corresponds to a first monitored temperature value; writing data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the first monitored temperature value; determining that the first monitored temperature value exceeds a threshold temperature range; monitoring the temperature of the memory component of the memory sub-system to determine that the temperature of the memory component corresponds to a second monitored temperature value that is within the threshold temperature range; and rewriting the data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the second monitored temperature value.

Abstract: A power management integrated circuit (PMIC) includes a voltage regulator, a monitoring circuit, and a count register. The voltage regulator is configured to generate an output voltage. The monitoring circuit is configured to receive a feedback voltage of the output voltage, and to determine at each of periodic intervals whether the feedback voltage is outside a threshold voltage range. The count register is configured to store a count value indicative of a number of times the feedback voltage is determined by the monitoring circuit to be outside the threshold voltage range.

Abstract: A memory controller includes a command queue and an arbiter operating in a first voltage domain, and a physical layer interface (PHY) operating in a second voltage domain. The memory controller includes isolation cells operable to isolate the PHY from the first voltage domain. A local power state controller, in response to a first power state command, provides configuration and state data for storage in an on-chip RAM memory, causes the memory controller to enter a powered-down state, and maintains the PHY in a low-power state in which the second voltage domain is powered while the memory controller is in the powered-down state.

Abstract: A memory device includes a memory cell array, an address manager and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The address manager samples access addresses provided from a memory controller to generate sampling addresses and determines a capture address from among the access addresses, based on a time interval between refresh commands from the memory controller. The refresh controller refreshes target memory cells from among the plurality of memory cells based on one of a maximum access address from among the sampling address and the captured address.

Abstract: A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

Abstract: A semiconductor apparatus includes a memory controller and data storage configured to input and output data in synchronization with a clock signal provided from the memory controller. The data storage includes a memory cell array and a data output apparatus configure to output read data from the memory cell array by sensing a logic level of the read data during a low-level period of a first clock, which is an inverted signal of a divided clock of the clock signal, and a low-level period of a second clock, the second clock having a set to phase delay amount from the divided clock.

Abstract: A memory may include multiple rows each coupled to multiple memory cells; a target row classification circuit suitable for classifying, as a target row, a row, among the multiple rows, that is susceptible to data loss as a result of activity of an adjacent row; and a target row signal generation circuit suitable for sequentially activating a target row active signal for activating the target row and a target row precharge signal for precharging the target row in response to a precharge command.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for a sequence of refreshing memory mats. During a refresh operation, wordlines of the memory may be refreshed in a sequence. Groups of wordlines may be organized into memory mats. In order to prevent noise, each time a wordline in a memory mat is refreshed, the next wordline to be refreshed may be in a mat which is not physically adjacent to the mat containing the previously refreshed wordline.

Abstract: A memory device includes a memory cell array, a random bit generator, a comparator and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The random bit generator generates a random binary code having a predetermined number of bits. The comparator compares the random binary code and a reference binary code to output a matching signal based on a result of the comparison. The refresh controller refreshes target memory cells from among the plurality of memory cells based on addresses accessed by a memory controller during a sampling period randomly determined based on the matching signal and a refresh command from the memory controller.

Abstract: Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of skipped refresh operations on a memory. Memory cells of memories may need to periodically perform refresh operations. In some instances, auto-refresh operations may be periodically skipped when charge retention characteristics of the memory cells of the memory exceed the auto-refresh frequency. To reduce peak current draw during refresh operations, the skipped refresh operations may be staggered across different portions of the memory. In one example, the skipped refresh operation may be staggered in time among memory dies of the memory to limit a number of memory dies that are performing an auto-refresh operation to a maximum number. In another example, the skipped refresh operation may be staggered in time among memory banks of a single memory array to limit a number of memory banks that are performing an auto-refresh operation to a maximum number.

Abstract: A write masked latch bit cell of an SRAM includes a write mask circuit that is responsive to assertion of a first write mask signal to cause a value of a write data node to be a first value and is responsive to assertion of a second write mask signal to cause the value of the write data node to have a second value. A pass gate supplies the data on the write data node to an internal node of the bit cell responsive to write word line signals being asserted. A keeper circuit maintains the value of the first node independently of values of the write word line signals while the first write mask signal and the second write mask signal are deasserted.

Abstract: Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.

Abstract: The present description relates to a method and a circuit for powering a volatile memory in which power pulses are sent to the memory, the duration between two pulses being shorter than a remanence time of said volatile memory.

Abstract: A method to perform an on demand refresh operation of a memory sub-system is disclosed. The method includes identifying a temporal attribute of user data stored in the memory component, upon determining that the identified temporal attribute satisfies a time condition, providing an indication whether a refresh operation of the user data improves performance of the memory component, receiving an indication to perform the refresh operation of the memory component, and responsive to a time between the refresh operation and a previously performed refresh operation not satisfying a threshold criterion, refraining from performing the refresh operation of the memory component.

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.

Abstract: A method for performing a refresh operation based on system characteristics is provided. A The method includes determining that a current operation condition of a memory component is in a first state and detecting a change in the operation condition from the first state to a second state. The method further includes determining a range of the operation condition to which the second state belongs. The method further includes determining a refresh period associated with the range of the operation condition, the refresh period corresponding to a period of time between a first time when a write operation is performed on a segment of the memory component and a second time when a refresh operation is to be performed on the segment. The method further includes performing the refresh operation on the memory component according to the refresh period.

Abstract: A non-volatile storage system includes: a host and a storage device. The host includes a submission queue memory, a completion queue memory, and a read/write data memory, and the storage device includes: a controller configured to concurrently communicate with the read/write data memory and with at least one of the submission queue memory and the completion queue memory; and a memory device configured to communicate with the controller.

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

Abstract: An apparatus and method are provided for controlling memory accesses. The apparatus has memory access circuitry for performing a tag-guarded memory access operation in response to a target address, the tag-guarded memory access operation by default comprising: comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and generating an indication of whether a match is detected between the guard tag and the address tag. Further, the apparatus has control tag storage for storing, for each of a plurality of memory regions, configuration control information used to control how the tag-guarded memory access operation is performed by the memory access circuitry when the target address is within that memory region. Each memory region corresponds to multiple of the blocks.

Abstract: A resistive element array circuit includes word lines, bit lines, resistive elements, a selector, a differential amplifier, and a ground terminal. The word lines are coupled to a power supply. The resistive elements are each disposed at an intersection of corresponding one of the word lines and corresponding one of the bit lines. The selector is configured to select one word line and one bit line. The differential amplifier includes a positive input terminal configured to be coupled to the selected one of the bit lines which is selected by the selector, a negative input terminal configured to be coupled to non-selected one of the bit lines which is not selected by the selector and to non-selected one of the word lines which is not selected by the selector, an output terminal being coupled to the negative input terminal. The ground terminal is coupled to the positive input terminal.

Abstract: A semiconductor memory device and a memory system are provided. The semiconductor memory device includes a memory cell array, a normal refresh row address generator, a hammer refresh row address generator, a refresh selection signal generator, and a selector. The normal and hammer refresh row address generators generates a normal refresh row address and a hammer refresh row address, respectively, in response to a refresh counting control signal. The refresh selection signal generator sequentially generates normal and hammer refresh selection signals in response to the refresh counting control signal. The selector selects the normal refresh row address or the hammer refresh row address in response to the normal and hammer refresh selection signals. A normal refresh operation and a hammer refresh operation are sequentially performed on a memory cell array block among plural memory cell array blocks in response to the refresh row address.

Abstract: An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

Abstract: Methods, systems, and devices for memory device operation are described. A memory device may operate in different modes in response to various conditions and user constraints. Such modes may include a power-saving or low power mode. While in the low power mode, the memory device may refrain from operations, such as self-refresh operations, on one or more of the memory array(s) included in the memory device. The memory device may deactivate external interface components and components that may generate operating voltages for the memory array(s), while the memory device may continue to power circuits that store operating information for the memory device. The memory device may employ similar techniques in other operating modes to accommodate or react to different conditions or user constraints.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for controlling refresh operations. Responsive to a refresh command, or one or more pumps generated responsive to the refresh command, different banks of a memory array may perform different types of refresh operations for a pump. In some examples, the type of refresh operation performed by a bank may vary from pump to pump of a refresh operation.

Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

Abstract: A semiconductor memory device is provided. The semiconductor memory device can suppress increases in power consumption. As a result, damage to the data normally caused by row hammer problem can be prevented. The semiconductor memory device includes a control unit. The control unit controls a refresh operation for a memory to be performed at any interval, wherein there are a plurality of possible intervals. When read/write access to the memory is required, the control unit controls the refresh operation for the memory to be performed with a shortest interval among the intervals, until a predetermined condition is met.

Abstract: Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.

Abstract: Systems, apparatuses, and methods related to host-based error correction are described. Error correction operations can be performed on a host computing system as opposed to on a memory system. For instance, data containing erroneous bits can be transferred from a memory system to a host computing system and error correction operations can be performed using circuitry resident on the host computing system. In an example, a method can include receiving, by a host computing system, data that comprises a plurality of uncorrected bits from a memory system coupleable to the host computing system, determining an acceptable error range for the data based at least in part on an application associated with the data, and performing, using error correction logic resident on the host computing system, an initial error correction operation on the data based at least in part on the acceptable error range.

Abstract: Information associated with a user and a presentation made by the user is received. A presentation readiness of the user is dynamically detected. One or more of a presentation mode of a presentation software and a recording mode of the presentation software is initiated based on the received information and the dynamically detected presentation readiness.

Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage to the memory array based on the read request. The control circuit is additionally configured to count a total number of the plurality of memory cells that have switched to an active read state based on the first voltage and to apply a second voltage to the memory array based on the total number. The control circuit is further configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.