Abstract: A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for scheduling targeted refreshes in a memory device. Memory cells in a memory device may be volatile and may need to be periodically refreshed as part of an auto-refresh operation. In addition, certain rows may experience faster degradation, and may need to undergo targeted refresh operations, where a specific targeted refresh address is provided and refreshed. The rate at which targeted refresh operations need to occur may be based on the rate at which memory cells are accessed. The memory device may monitor accesses to a bank of the memory, and may use a count of the accesses to determine if an auto-refresh address or a targeted refresh address will be refreshed.

Abstract: A memory device includes a latch circuit suitable for storing an input address as a first latch address in response to a first latch signal, and storing an address, selected between the input address and the first latch address, as a second latch address in response to a second latch signal, a test determining circuit suitable for determining whether a memory cell fail occurs, based on test data, and generating a detection signal corresponding to the determination result, in response to a test mode signal, and a control signal generation circuit suitable for comparing the input address to the first and second latch addresses in response to the detection signal, and selectively enabling the first and second latch signals according to the comparison result.

Abstract: A memory for an artificial neural network (ANN) accelerator is provided. The memory includes a first bank, a second bank and a bank selector. Each bank includes at least two word lines and a plurality of read word selectors. Each word line stores a plurality of words, and each word has a plurality of bytes. Each read word selector has a plurality of input ports and an output port, is coupled to a corresponding word in each word line, and is configured to select a byte of the corresponding word of a selected word line based on a byte select signal. The bank selector is coupled to the read word selectors of the first bank and the second bank, and configured to select a combination of read word selectors from at least one of the first bank and the second bank based on a bank select signal.

Abstract: A sense amplifier is biased to reduce leakage current equalize matched transistor bias during an idle state. A first read select transistor couples a true bit line and a sense amplifier true (SAT) signal line and a second read select transistor couples a complement bit line and a sense amplifier complement (SAC) signal line. The SAT and SAC signal lines are precharged during a precharge state. An equalization circuit shorts the SAT and SAC signal lines during the precharge state. A differential sense amplifier circuit for latching the memory cell value is coupled to the SAT signal line and the SAC signal line. The precharge circuit and the differential sense amplifier circuit are turned off during a sleep state to cause the SAT and SAC signal lines to float. A sleep circuit shorts the SAT and SAC signal lines during the sleep state.

Abstract: Methods, systems, and devices for restoring memory cell threshold voltages are described. A memory device may perform a write operation on a memory cell during which a logic state is stored at the memory cell. Upon detecting satisfaction of a condition, the memory device may perform a read refresh operation on the memory cell during which the threshold voltage of the memory cell may be modified. In some cases, the duration of the read refresh operation may be longer than the duration of a read operation performed by the memory device on the memory cell or on a different memory cell.

Abstract: A memory system includes a memory controller and a memory device. The memory controller generates refresh commands periodically by an average refresh interval. The memory device performs a normal refresh operation and a hammer refresh operation during a refresh cycle time. The memory device includes a memory cell array including memory cells connected to a plurality of wordlines, a temperature sensor configured to provide temperature information by measuring an operation temperature of the memory cell array and a refresh controller configured to control the normal refresh operation and the hammer refresh operation. The refresh controller varies a hammer ratio of a unit hammer execution number of the hammer refresh operation executed during the refresh cycle time with respect to a unit normal execution number of the normal refresh operation executed during the refresh cycle time.

Abstract: A reducing peak current consumption in a memory device when performing a word line voltage refresh operation or a read operation. When a word line voltage refresh operation or read operation is performed for the first time after a memory device powers up, the operation is performed with a power-saving technique such as reducing a ramp up rate of a voltage pulse, ramping up the voltage pulse in multiple steps, initiating the ramp up for different groups of word lines in a block at different times, initiating the ramp up for different blocks of word lines at different times, and reducing the number of blocks which are refreshed concurrently. When an additional word line voltage refresh operation or read operation is subsequently performed, the power-saving technique can be omitted.

Abstract: Methods, systems, and devices for self-refresh of memory cells are described. A controller coupled with a memory cell may be configured to apply a first voltage to a control gate of a first transistor, where the first voltage activates the first transistor to selectively couple terminals of the first transistor with each other based on a charge stored on the interstitial gate. The controller may be configured to apply a current to a bit line, where a second voltage of the bit line is based on the current and the charge stored on the interstitial gate. The controller may be configured to apply, based on applying the first voltage to the control gate of the first transistor and applying the current to the bit line, a third voltage to a gate of a second transistor to couple the bit line with the interstitial gate of the first transistor.

Abstract: A memory core including a memory core including memory cells that are arranged in a plurality of rows and a plurality of columns; and a refresh target selection circuit suitable for storing an address and a risk score of each of activated rows among the rows, wherein the refresh target selection circuit is further suitable for increasing the risk score of a corresponding row whenever the corresponding row is activated, whenever a row at a ‘+2’ position of the corresponding row is activated, and whenever a row at a ‘?2’ position of the corresponding row is activated.

Abstract: A storage device comprising: a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device to determine a memory block to perform a refresh operation and to control the memory block to perform the refresh operation to recover data of the memory block.

Abstract: A memory apparatus may include a row hammer control circuit. The row hammer control circuit may generate a plurality of selection control signals by monitoring an interval at which a memory bank of a memory cell array is accessed. The row hammer apparatus may set a threshold value for performing a refresh operation, as one of a plurality of values, based on the plurality of selection control signals.

Abstract: A device includes a plurality of memory cells, an error detection circuit configured to detect at least one memory cell storing error data and a refresh control circuit including a register configured to store an error address corresponding to the at least one memory cell storing error data. The refresh control circuit is configured to control a refresh cycle of the error address.

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

Abstract: Memory devices and systems with programmable refresh order and stagger times are disclosed herein. In one embodiment, a memory device includes a first memory bank group and a second memory bank group. The memory device is configured, in response to a refresh command, to perform a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time after the first time. The memory device is further configured to perform, in response to a read or write command, a read or write operation on the first memory bank group, the second memory bank group, or both the first and second memory bank groups after beginning the first refresh operation and before completing the second refresh operation.

Abstract: Apparatuses and methods for calculating targeted refresh addresses may include circuitry that may be used to calculate victim row addresses having a variety of spatial relationships to an aggressor row. The spatial relationship of the victim row addresses calculated by the circuitry may be based, at least in part, on states of control signals provided to the circuitry. That is, the circuitry may be used to calculate the different victim row addresses by changing the states of the control signals.

Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.

Abstract: A memory device including: a plurality of pins for receiving control signals from an external device; a first bank having first memory cells, wherein the first bank is activated in a first operation mode and a second operation mode; a second bank having second memory cells, wherein the second bank is deactivated in the first operation mode and activated in the second operation mode; a processing unit configured to perform an operation on first data, output from the first memory cells, and second data, output from the second memory cells, in the second operation mode; and a processing-in-memory (PIM) mode controller configured to select mode information, indicating one of the first operation mode and the second operation mode, in response to the control signals and to control at least one memory parameter, at least one mode register set (MRS) value, or a refresh mode according to the mode information.

Abstract: Methods, systems, and apparatuses related to determination of durations of memory device temperatures are described. For example, a controller can be coupled to a memory device to monitor an operating temperature of the memory device. The controller can determine the operating temperature exceeds a threshold temperature. The controller can determine a duration that the temperature exceeds the threshold temperature. The controller can provide data corresponding to the operating temperature and the duration to a requesting device.

Abstract: Various implementations described herein are related to a device having a sense amplifier that provides output data based on sensing a difference between input signals. The device may have a tracking circuit that tracks a resistive state of a bitcell and provides an input signal to the sense amplifier based on the tracked resistive state of the bitcell. The device may have a bitcell circuit that senses a data value associated with the resistive state of the bitcell and provides another input signal to the sense amplifier based on the sensed data value of the bitcell.

Abstract: Disclosed herein are mechanisms and methods for reducing power consumed by various DRAM technologies (e.g., high-capacity DRAM and/or 3D DRAM) which may impact battery life of the platform. These mechanisms and methods may opportunistically reduce the power consumed by DRAM by inhibiting periodic refresh commands to memory ranks that are not in-use. Since these mechanisms and methods may be based on enhancements to memory controllers, they may accordingly be operating system (OS) agnostic.

Abstract: Techniques described herein are related to protecting at least a portion of data stored in a memory array. A method may include detecting an invalid memory access request based at least in part on the secret key and the identifier and preventing unauthorized access of a memory array by halting an internal refresh of one or more memory cells associated with the memory array in response to detecting the invalid memory access request.

Abstract: A method includes monitoring a temperature of a memory component of a memory sub-system to determine that the temperature of the memory component corresponds to a first monitored temperature value; writing data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the first monitored temperature value; determining that the first monitored temperature value exceeds a threshold temperature range; monitoring the temperature of the memory component of the memory sub-system to determine that the temperature of the memory component corresponds to a second monitored temperature value that is within the threshold temperature range; and rewriting the data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the second monitored temperature value.

Abstract: Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, a device can be coupled to a memory device with an embedded sensor. The memory device can transmit the data generated by the embedded sensor using a sensor output coupled to the device. The memory device may generate, based at least in part on a characteristic of a memory device, a signal from a sensor embedded in the memory device and transmit the signal generated by the sensor from the memory device to another device coupled to the memory device.

Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device is comprised of a controller, a random access memory (RAM) unit, and a NVM unit, wherein the NVM unit is comprised of a plurality of zones. The RAM unit comprises a first logical to physical address table and the NVM unit comprises a second logical to physical address table. The zones are partitioned into sections, and each partitioned section aligns with a change log table. Data is written to each zone sequentially, and only one partitioned section is updated at a time for each zone. Each time a zone is erased or written to in the NVM unit, the first logical to physical address table is updated and the second logical to physical address table is periodically updated to match the first logical to physical address table.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes a computing resource and a memory controller coupled to a memory device. The computing resource selectively generates a hint that includes a target address of a memory request generated by the processor. The hint is sent outside the primary communication fabric to the memory controller. The hint conditionally triggers a data access in the memory device. When no page in a bank targeted by the hint is open, the memory controller processes the hint by opening a target page of the hint without retrieving data. The memory controller drops the hint if there are other pending requests that target the same page or the target page is already open.

Abstract: Addresses of accessed word lines are stored. Data related to victim word lines associated with the accessed word line are also stored. The victim word lines may have data stored in relation to multiple accessed word lines. The data related to the victim word lines is adjusted when the victim word line is refreshed during a targeted refresh operation or an auto-refresh operation. The data related to the victim word lines is adjusted when the victim word line is accessed during a memory access operation.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for dynamic refresh allocation. Memories may be subject to row hammer attacks, where one or more wordlines are repeatedly accessed to cause data degradation in victim rows nearby to the hammered wordlines. A memory may perform background auto-refresh operations, and targeted refresh operations where victim wordlines are refreshed. The memory may monitor access patterns to the memory in order to dynamically allocate the number of targeted refresh operations and auto-refresh operations in a set of refresh operations based on if a hammer attack is occurring and the type of hammer attack which is occurring.

Abstract: In some examples, a memory device may perform refresh operations responsive to internal and/or external commands. internal refresh commands may include auto-refresh commands and row hammer (e.g., targeted) refresh commands. External commands may include refresh management commands. In some examples, the external command may cause a refresh operation to occur after a number of activation commands. The memory device may monitor row addresses associated with the activation commands. In some examples, the memory device may skip a refresh operation indicated by a refresh management command if none of the row addresses associated with the activation commands occurs at a high frequency. In some examples, row addresses may be determined to be aggressor row addresses if a received row address matches a previously received row address.

Abstract: Systems and methods are described to enable a memory device integrated in a memory module or system to disable one or more data bits, nibbles or bytes of the memory device. The memory device can be further configured to disable error or redundancy checking associated with the disabled data bits, nibbles or bytes, to mask errors associated with the disabled data bits, nibbles or bytes, and/or to suppress the refresh of portions of a memory array associated with the disabled data bits, nibbles or bytes.

Abstract: A boot image is modified to require authentication based on stable system values that are uniquely associated with a storage array. The stable system values may be used as a key to decrypt a password. The modified boot image will not allow booting to proceed without the decrypted password. The password cannot be decrypted based on different stable system values such as the stable system values of other storage arrays.

Abstract: A module for multiple dies is disclosed. The module can include a group of dies that include a first die having a first voltage block and a second die having a second voltage block. The module can also include an interconnect that electrically connects the first and second dies. Power supply generation in the first die is enabled in non-active mode, while power supply generation in the second die is disabled. The power supply generation in the second die may be enabled when the second die is in active mode. The first die can send enabling signal to the second the die to enable the second die. The first die can provide supply to the second die in the non-active mode. The first die can send self-refresh timing command to the second die when the module is in a self-refresh mode.

Abstract: Methods, systems, and devices for decoder architecture for memory device are described. An apparatus includes a memory array having a memory cell and an access line coupled with the cell and a decoder having a first stage and a second stage. The decoder supplying a first voltage during a first access operation and a second voltage during a second access operation to the access line. The second stage of the decoder includes a first transistor that supplies the first voltage based on a third voltage at the source of the first transistor exceeding a fourth voltage at a gate of the first transistor and a first threshold voltage. The second stage includes a second transistor that supplies the second voltage based on a fifth voltage at a gate of the second transistor exceeding a sixth voltage at the source of the second transistor and a second threshold voltage.

Abstract: Memory devices, system, and methods for operating the same are provided. The memory device can comprise a non-volatile memory array and control circuitry. The control circuitry can be configured to store a value corresponding to a number of activate commands received at the memory device, update the value in response to receiving an activate command received from a host device, and trigger, in response to the value exceeding a predetermined threshold, a remedial action performed by the memory device. The control circuitry can be further configured to store a second value corresponding to a number of refresh operations performed by the memory device, update the second value in response to performing a refresh operation, and trigger, in response to the value exceeding a second predetermined threshold, a second remedial action performed by the memory device.

Abstract: A memory system includes a plurality of memory dies respectively having at least one channel, a controller configured to control the plurality of memory dies, and a base die configured for interfacing signal and data transmissions between the plurality of memory dies and the controller. The controller is configured to remap a logical channel address of the most frequently used channel to a physical channel address of a channel having a lowest temperature value to transmit the remapped physical channel address to the base die.

Abstract: A memory device comprises a memory array that includes memory cells and a memory controller operatively coupled to the memory array. The memory controller includes an oscillator circuit, internal memory, a processor core coupled to the oscillator circuit and the internal memory, and configured to load operating firmware during a boot phase of the memory device, voltage detector circuitry configured to detect a decrease in a circuit supply voltage of the memory controller during the boot phase, and logic circuitry configured to halt operation of the oscillator circuit and power down the processor core and the internal memory during the boot phase in a low power mode in response to detecting the decrease in the circuit supply voltage.

Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for providing refresh logic, such as row hammer refresh circuitry, in a location on a memory die apart from a bank logic region of the memory die. In some examples, at least some of the components of the row hammer refresh circuitry may be shared between banks of the memory.

Abstract: An opening is formed in an accommodating case of a fuel cell stack. Flat cables are led out of the accommodating case through the opening. The flat cables pass through a grommet covering the opening. The grommet is positioned by a seal plate (positioning member) attached to the accommodating case.

Abstract: A semiconductor memory device includes a cell array including a plurality of word lines; a plurality of address storing circuits suitable for sequentially storing a sampling address as one of a plurality of latch addresses, and sequentially outputting each of the latch addresses as a target address according to a refresh command; a duplication decision circuit suitable for preventing the sampling address from being stored in the address storing circuits when the sampling address is identical to any of the latch addresses stored in the address storing circuits; and a row control circuit suitable for refreshing one or more word lines based on the target address in response to the refresh command.

Abstract: Methods, systems, and devices for memory accessing with auto-precharge are described. For example, a memory system may be configured to support an activate with auto-precharge command, which may be associated with a memory device opening a page of memory cells, latching respective logic states stored by the memory cells at a row buffer, writing logic states back to the page of memory cells, and maintaining the latched logic states at the row buffer (e.g., while maintaining power to latches of the row buffer, after closing the page of memory cells, while the page of memory cells is closed).

Abstract: A semiconductor device may include a plurality of memory banks arranged in a first direction; an address decoder arranged at one side of the memory banks; a plurality of local sense amplifier arrays arranged under each of the memory banks; a plurality of first input/output lines connected between the memory banks and the local sense amplifier arrays corresponding to each of the memory banks; and at least one second input/output line connected to the local sense amplifier arrays and extended in the first direction.

Abstract: An apparatus has an array of memory cells and a controller coupled to the array. The controller is configured to track a sub-threshold leakage current through a number of memory cells of the array and determine a threshold voltage based on the sub-threshold leakage current.

Abstract: Apparatuses, systems, and methods for refresh modes. A memory may need to perform targeted refresh operations to refresh the ‘victim’ word lines which are near to frequently accessed ‘aggressor’ word lines. To refresh the victims at a high enough rate, it may be desirable to refresh multiple victims as part of the same refresh operation. However, certain word lines (e.g., word lines in a same section or adjacent sections of the memory) cannot be refreshed together. The memory may have a section comparator, which may check stored aggressor addresses and may provide a signal if there are not two stored addresses which can be refreshed together. Based, in part, on the signal, the memory may activate one of several different refresh modes, which may control the types of refresh operation performed responsive to a refresh signal.

Abstract: A memory system includes a plurality of memory dies respectively having at least one channel, a controller configured to control the plurality of memory dies, and a base die configured for interfacing signal and data transmissions between the plurality of memory dies and the controller. The controller is configured to remap a logical channel address of the most frequently used channel to a physical channel address of a channel having a lowest temperature value to transmit the remapped physical channel address to the base die.

Abstract: An opening is formed in an accommodating case of a fuel cell stack. Flat cables are led out of the accommodating case through the opening. The flat cables pass through a grommet covering the opening. The grommet is positioned by a seal plate (positioning member) attached to the accommodating case.

Abstract: Methods, systems, and devices for performing safety event detection for a memory device are described. For example, a memory array of a memory device may operate in a first mode of operation (e.g., a normal mode of operation). An event associated with a reduction of data integrity for the memory array may be detected. In some cases, the event may be associated with a temperature of the memory device, a voltage level detected at the memory device, an error event at the memory device, or the like. Based on the detected event, it may be determined whether to adjust the operation of the memory device to a second mode of operation (e.g., a safe mode of operation). The second mode of operation may correspond to a mode of operation that increases data retention characteristics.

Abstract: A device includes a power gating signal generation circuit, a clock interrupt signal generation circuit, and a shift clock generation circuit. The power gating signal generation circuit configured to generate a power gating signal based on a mode entry signal and a mode exit signal to perform a power gating operation. The clock interrupt signal generation circuit configured to generate a clock interrupt signal based on the mode entry signal and the power gating signal to perform a clock interrupt operation. The shift clock generation circuit configured to generate a shift clock signal supplied to an internal circuit based on the power gating signal and the clock interrupt signal.

Abstract: A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of word lines each coupled to a plurality of memory cells, and a control circuit configured to activate first and second internal signals in a time-division manner in response to a first external command. A first number of the word lines are selected in response to the first internal signal, and a second number of the word line is selected in response to the second internal signal, the second number is smaller than the first number.

Abstract: Apparatuses and methods for distributing row hammer refresh events across a memory device is disclosed. In one embodiment, the present disclosure is directed to an apparatus that includes a first memory configured to receive a sequential series of refresh commands and to replace a first of the sequential refresh commands with a row hammer refresh operation once during a refresh steal cycle, a second memory configured to receive the sequential series of refresh commands at to replace a second of the sequential refresh command with a row hammer refresh operation once during a refresh steal cycle, wherein the first of the sequential refresh commands and the second of the sequential refresh commands are different commands.