Having Fuse Element Patents (Class 365/225.7)
  • Patent number: 11152052
    Abstract: Apparatuses, systems, and methods for fuse based device identification. A device may include a number of fuses which are used to encode permanent information on the device. The device may receive an identification request, and may generate an identification number based on the states of at least a portion of the fuses. For example, the device may include a hash generator, which may generate the identification number by using the fuse information as a seed for a hash algorithm.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yoshihito Morishita, Chikara Kondo
  • Patent number: 11152300
    Abstract: An electrical fuse device is disclosed. A circuit apparatus can include the fuse device, a first circuit element and a second circuit element. The fuse includes a first contact that has a first electromigration resistance, a second contact that has a second electromigration resistance and a metal line, which is coupled to the first contact and to the second contact, that has a third electromigration resistance that is lower than the second electromigration resistance. The first circuit element is coupled to the first contact and the second circuit element coupled to the second contact. The fuse is configured to conduct a programming current from the first contact to the second contact through the metal line. Further, the programming current causes the metal line to electromigrate away from the second contact to electrically isolate the second circuit element from the first circuit element.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Yan Zun Li, Keith Kwong Hon Wong, Chih-Chao Yang
  • Patent number: 11094388
    Abstract: An anti-fuse device includes an anti-fuse array and a biasing circuit. The anti-fuse array includes an anti-fuse cell that has a gate node, a gate oxide layer and a source-drain node. The biasing circuit is coupled to the anti-fuse array and is configured to bias the gate node of the anti-fuse cell with a first bias voltage during a program operation, and bias the source-drain node of the anti-fuse with a second bias voltage during the program operation. A voltage level of the first bias voltage is lower than a voltage level of the second bias voltage, and a voltage difference between the first bias voltage and the second bias voltage is higher than a gate oxide breakdown voltage of the gate oxide layer.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: August 17, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Chan Jong Park
  • Patent number: 11029886
    Abstract: The present technology relates to a memory system and a method of operating the memory system. The memory system includes a memory device including a plurality of memory blocks, the memory device configure to perform on each of the plurality of memory blocks at least one of a program operation, a read operation, or an erase operation in response to an internal command; and a controller in communication with a host and the memory device and configured to receive a request from the host and generate the internal command in response to the request from the host, the controller further configured to control the memory device to perform a stress check operation on a first memory block of the plurality of memory blocks in which the program operation has been completed.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: June 8, 2021
    Assignee: SK hynix Inc.
    Inventors: Min Ho Her, Sung Ho Kim, Seung Il Kim, Jae Min Lee
  • Patent number: 10971247
    Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Ryun Kim, Yoon-Na Oh, Hyung-Jin Kim, Hui-Kap Yang, Jang-Woo Ryu
  • Patent number: 10923483
    Abstract: A metal fuse structure may be provided. The metal fuse structure may comprise a first fuse element and a second fuse element. The second fuse element may be adjacent to the first fuse element for a length L. The second fuse element may be spaced apart from first fuse element by a width W.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: February 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Sheng Chang, Yao-Jen Yang
  • Patent number: 10885997
    Abstract: A one-time programmable (OTP) memory cell, and an OTP memory and a memory system including the same may be provided. The OTP memory cell includes a main OTP cell transistor, a redundant OTP cell transistor, and an access transistor that are connected in series between a first node in a floating state and a second node. The OTP memory cell is configured to apply a program voltage to gates of the main OTP cell transistor and the redundant OTP cell transistor, and a program access voltage lower than the program voltage to a gate of the access transistor, during a program operation.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: January 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Min Yeol Ha
  • Patent number: 10878929
    Abstract: A circuit includes an eFuse and a first program device coupled in series between a bit line and a program node, and a second program device configured in parallel with the first program device. The first program device and the second program device are separately controllable.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Meng-Sheng Chang, Yao-Jen Yang
  • Patent number: 10868021
    Abstract: A semiconductor memory device includes a semiconductor substrate having an active region of a first conductivity type defined by a device isolation layer, a first impurity region in the active region, an anti-fuse gate electrode on the semiconductor substrate and extending across the first impurity region, an anti-fuse gate dielectric layer between the anti-fuse gate electrode and the first impurity region, a selection gate electrode on the semiconductor substrate and extending across the active region, a selection gate dielectric layer between the selection gate electrode and the active region, and a second impurity region in the active region between the selection gate electrode and the anti-fuse gate electrode. The first and second impurity regions have impurities of a second conductivity type. The first impurity region has an impurity concentration less than the impurity concentration of the second impurity region.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jongpil Son
  • Patent number: 10755777
    Abstract: The ROM device has a memory array including memory cells formed by an access element and a data storage element; a high voltage column decoder stage; a high voltage row decoder stage; an analog stage; and a writing stage, wherein the data storage elements are electrically non-programmable and non-modifiable. The memory array is formed by memory cells having a first logic state and by memory cells having a second logic state. The data storage element of the memory cells having the first logic state is formed by a continuous conductive path uninterruptedly connecting the access transistor to the respective bit line, the data storage element of the memory cells having the second logic state is formed by a region of dielectric material insulating the access transistor from the respective bit line.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: August 25, 2020
    Assignee: STMicroelectronics S.R.L.
    Inventors: Marcella Carissimi, Marco Pasotti, Chantal Auricchio
  • Patent number: 10741267
    Abstract: A memory cell includes a first anti-fuse element, a second anti-fuse element, and a selection circuit. The first anti-fuse element has a first terminal, a second terminal being floating, and a control terminal coupled to a first anti-fuse control line. The second anti-fuse element has a first terminal coupled to the first terminal of the first anti-fuse element, a second terminal being floating, and a control terminal coupled to a second anti-fuse control line. The selection circuit is coupled to the first terminal of the first anti-fuse element, the first terminal of the second anti-fuse element, and a source line. The selection circuit controls an electrical connection from the source line to the first terminal of the first anti-fuse element and the first terminal of the second anti-fuse element.
    Type: Grant
    Filed: June 9, 2019
    Date of Patent: August 11, 2020
    Assignee: eMemory Technology Inc.
    Inventor: Dung Le Tan Hoang
  • Patent number: 10693363
    Abstract: Aspects of the present disclosure involve a power module, which may include an inverter circuit employing semiconductor switch dies. In the presence of a failure of a die, which may include an arc from a short, a sensor produces a signal responsive to the failure. The signal initiates an indirect fuse, such as a pyrotechnic element, that opens conductors associated with the die. For example, the die or a related die may be wire bonded to terminals of the module. The indirect element may therefore open the bonds to the terminals to isolate the failed die and/or related dies.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: June 23, 2020
    Inventors: Paul M. White, Mark H. Sherwood, Stephen M. Spiteri, Zachary M. Rubin
  • Patent number: 10672489
    Abstract: An electronic device including: a fuse array including: fuse elements organized along a first direction and a second direction, wherein each fuse element is configured to store information, and a selection circuit configured to provide access to the fuse elements according to positions of the fuse elements along the first direction and the second direction; and a fuse read circuit connected to the fuse array, the fuse read circuit configured to generate a fuse-read output based on reading from one or more of the fuse elements.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John E. Riley, Girish N. Cherussery, Scott E. Smith, Yu-Feng Chen
  • Patent number: 10665311
    Abstract: Apparatuses and methods including anti-fuses and for reading and programming same are disclosed herein. An example apparatus may include an anti-fuse element comprising first, second, and third transistors coupled in series between first and second nodes such that the second transistor is between the first and third transistors. The second transistor is configured to be operated such that a punch-through current flows through the second transistor to indicate that the anti-fuse element has been programmed.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Shinichi Miyatake
  • Patent number: 10629282
    Abstract: An E-fuse circuit comprising: a ring address latch, configured to receive a first input address arranged in serial i bits responding to a first clock signal, and to output a second input address arranged in serial j bits responding to a second clock signal; a control signal generating circuit, configured to receive the second input address, and to decode the second input address to generate first control signals with m bits and second control signals with n bits, wherein the first control signals and the second control signals are transmitted in parallel, and m, n are factors of j; and an E-fuse group, comprising j fuses. If any one of the first control signals has a first logic value and any one of the second control signals has the logic value, a corresponding fuse the E-fuse group is burned.
    Type: Grant
    Filed: June 16, 2019
    Date of Patent: April 21, 2020
    Assignee: Elite Semiconductor Memory Technology Inc.
    Inventors: Tse-Hua Yao, Yi-Fan Chen
  • Patent number: 10600496
    Abstract: Methods, systems, and devices for modifying memory bank operating parameters are described. Operating parameter(s) may be individually adjusted for memory banks or memory bank groups within a memory system based on trimming information. The local trimming information for a memory bank or memory bank group may be stored in a fuse set that also stores repair information for the particular memory bank or in a fuse set that also stores repair information for a memory bank in the particular memory bank group. The local trimming information may be applied to operating parameters for particular memory banks or memory bank groups relative to or instead of global adjustments applied to operating parameters of multiple or all of the memory banks in the memory system.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, Alan J. Wilson
  • Patent number: 10417455
    Abstract: Described are various embodiments of a hardware security module. For example, in one embodiment, a hardware security module is described to comprise: two or more hardware ports, each one of which operable to electronically receive given input hardware port-specific cryptographic data thereon to initiate execution of an internal cryptographic process as a function thereof; two or more segregated hardware port-specific storage spaces each operatively linked to a corresponding one of said hardware ports via a corresponding hardware link, and storing respective secured hardware port-specific cryptographic data thereon exclusively retrievable as a function of said given input hardware port-specific cryptographic data corresponding thereto; and a cryptographic engine operable to execute said cryptographic process based on said secured port-specific cryptographic data retrieved from said segregated hardware port-specific storage spaces as a function of said given input port-specific cryptographic data.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 17, 2019
    Assignee: CRYPTO4A TECHNOLOGIES INC.
    Inventors: Bruno Couillard, Bradley Clare Ritchie, James Ross Goodman, Jean-Pierre Fiset
  • Patent number: 10403380
    Abstract: A semiconductor device with an anti-fuse element includes a semiconductor substrate, a well region of a first conductivity type formed in the semiconductor substrate, and a gate electrode formed over the semiconductor substrate through a gate insulating film, and source regions of a second conductivity type opposite to the first conductivity type formed within the well region at the both ends of the gate electrode. When writing in the fuse element, a first writing potential is applied to the gate electrode, a first reference potential is applied to the well region, an intermediate potential is supplied to the source regions, and the intermediate potential is lower than the first writing potential and higher than the first reference potential.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: September 3, 2019
    Assignee: RENESAS ELECTRONCIS CORPORATION
    Inventor: Hiromichi Takaoka
  • Patent number: 10395731
    Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
  • Patent number: 10374152
    Abstract: Magnetic tunnel junction antifuse devices are protected from degradation caused by programming voltage drop across the gates of unselected magnetic tunnel junction antifuses by connecting said magnetic tunnel junctions serially with a first field effect transistor and a second field effect transistor, the first field effect transistor having its gate connected to a positive supply voltage while the gate of the second field effect transistor is switchably connected to a programming voltage, such that when the second field effect transistor of a selected magnetic tunnel junction is switched to direct the programming voltage to program the selected magnetic tunnel junction an unswitched magnetic tunnel junction and the second field effect transistor do not experience a voltage drop across the gates thereof sufficient to degrade.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, John K. DeBrosse, Chandrasekharan Kothandaraman
  • Patent number: 10373698
    Abstract: An electronic device including: a fuse array including fuse cells organized along a first direction and a second direction, wherein each fuse cell includes: a fuse element configured to store information, and a selection circuit configured to provide access to the fuse element according to a position of the fuse cell element along the first direction and the second direction; and a fuse read circuit connected to the fuse array, the fuse read circuit configured to generate a fuse read output based on reading from one or more of the fuse cells simultaneously and in parallel.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: John E. Riley, Girish N. Cherussery, Scott E. Smith, Yu-Feng Chen
  • Patent number: 10333321
    Abstract: The present disclosure provides an overvoltage and overcurrent protection circuit and a mobile terminal. The overvoltage and overcurrent protection circuit comprises a primary protection circuit and a secondary protection circuit. The primary protection circuit comprises a power end coupled to an anode of a cell, a detection end coupled to a cathode of the cell, and a low potential interface end coupled to a ground end of a charging and discharging interface. The secondary protection circuit comprises a high potential cell end, a low potential cell end, and a high potential interface end, in which the high potential cell end is externally coupled to the anode of the cell, the low potential cell end is externally coupled to the cathode of the cell, and the high potential interface end is externally coupled to a power end of the charging and discharging interface.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: June 25, 2019
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Jialiang Zhang, Wenqiang Cheng, Dashuai Huang, Yuanxiang Hu, Kewei Wu
  • Patent number: 10332609
    Abstract: A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array comprising a plurality of fuses. The memory device additionally includes a first plurality of local fuse latches disposed outside of the fuse array and configured to provide redundancy for the plurality of memory addresses. The memory device also includes a fuse array broadcasting system comprising an N-bit bus system, wherein the N-bit bus system is communicatively coupled to the fuse array and to the first plurality of local fuse latches, and wherein the fuse array broadcasting system is configured to communicate fuse data from the fuse array to the first plurality of local fuse latches via the N-bit bus system.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: John E. Riley, Yu-Feng Chen, Scott E. Smith
  • Patent number: 10304554
    Abstract: A circuit may include a first switch to pre-charge a first voltage line to a first voltage for a first amount of time, such that the first voltage is an opposite polarity as compared to a second voltage coupled to the first voltage line when a first fuse is blown. The circuit may also include a second switch to pre-charge a second voltage line to a third voltage for the first amount of time, such that the third voltage is an opposite polarity as compared to a fourth voltage coupled to the second voltage line when a second fuse is blown. The circuit also includes a latch circuit to amplify a first voltage signal present on the first voltage line and amplify a second voltage signal present on the second voltage line after the first amount of time expires.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Raghukiran Sreeramaneni, Ramachandra R. Jogu, William J. Wilcox, Girish N. Cherussery
  • Patent number: 10274534
    Abstract: A reading circuit for a die ID in a chip is provided. The reading circuit includes a chip damage detection circuit, a switch selector, a fuse controller, and a fuse device, where the fuse device stores the die ID; the fuse controller reads the die ID from the fuse device; the chip damage detection circuit detects whether a processor in the chip is capable of operating properly, so as to obtain a detection result, and notify the switch selector of the detection result; and when the detection result is that the processor is capable of operating properly, the switch selector connects the processor and the fuse controller; and when the detection result is that the processor is not capable of operating properly, the switch selector connects the fuse controller and a maintenance device that is located outside the chip.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 30, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Bo Liang, Qi Wang, Yuan Liu
  • Patent number: 10217521
    Abstract: A non-volatile programmable bitcell has a read enable device with a source coupled with a bitline, an anti-fuse device with a gate coupled with a first write line, a drain coupled with a supply voltage and a source coupled with a drain of the read enable device. The bitcell has a fuse device coupled between a second write line and the drain of the read enable device. A magnitude of current flowing in the bitline, when the read enable device is enabled for reading, is dependent both on (1) a voltage level applied to the first write line and anti-fuse device state and on (2) a voltage level applied to the second write line and fuse device state. Usages include in a memory array, such as for FPGA configuration memory. The bitcell can be used as a multi-time programmable element, or to store multiple bit values.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: February 26, 2019
    Assignee: Lattice Semiconductor Corporation
    Inventors: Farrokh Kia Omid-Zohoor, Nguyen Duc Bui, Binh Ly
  • Patent number: 10199117
    Abstract: Disclosed are a unit cell capable of improving a reliability by enhancing a data sensing margin in a read operation, and a nonvolatile memory device with the same. The unit cell of a nonvolatile memory device includes: an antifuse having a first terminal between an input terminal and an output terminal; and a first switching unit coupled between a second terminal of the antifuse and a ground voltage terminal.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: February 5, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Chang-Hee Shin, Ki-Seok Cho, Seong-Do Jeon, Youn-Jang Kim
  • Patent number: 10109363
    Abstract: A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N? well and an anti-fuse cell formed on the N? well. The anti-fuse cell includes a drain P+ diffusion deposited in the N? well, a source P+ diffusion deposited in the N? well, and an oxide layer deposited on the N? well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: October 23, 2018
    Assignee: NEO Semiconductor, Inc.
    Inventor: Fu-Chang Hsu
  • Patent number: 10062448
    Abstract: A circuit includes a fuse cell with a current mirror. The first leg of the current minor includes first and second N-type transistors coupled in series between the upper and lower rails and the second leg includes third and fourth N-type transistors coupled in series between the upper and lower rails. The size of the first N-type transistor is (Y·A1), the second N-type transistor is (X·A2), the third N-type transistor is (X·A1) and the fourth N-type transistor is (Y·A2) where X and Y are integers and A1 and A2 are the sizes of respective reference transistors. A fuse has a first terminal coupled between the first and second N-type transistors and a second terminal coupled between the third and fourth N-type transistors; a first control node on the second leg of the current minor is coupled to control the voltage at an output node of the fuse cell.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: August 28, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Hector Torres, Mark Bryan Hamlyn
  • Patent number: 10026690
    Abstract: A fuse blowing method is disclosed. The fuse blowing method includes the following operations: receiving a number signal, in which the number signal includes a number; triggering the number of several fuse pumps according to the number signal; and generating a current to blow a fuse.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 17, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Ting-Shuo Hsu
  • Patent number: 10020030
    Abstract: A semiconductor apparatus may be provided. The semiconductor apparatus may include a plurality of memory blocks. The semiconductor apparatus may include a peripheral circuit region arranged between the plurality of memory blocks. A plurality of signal input/output (I/O) pads may be arranged in the plurality of memory blocks.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: July 10, 2018
    Assignee: SK hynix Inc.
    Inventors: Seung Bong Kim, Geun Il Lee
  • Patent number: 9991003
    Abstract: The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory cell; and a column of memory cells correspond to at least one redundant column of redundant memory cells wherein each redundant memory cell in the at least one redundant column stores same data as the memory cell in a same row.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: June 5, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Chen-Yi Huang, Jiaqi Yang, Cheng-Tai Huang
  • Patent number: 9991002
    Abstract: The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory cell; and a column of memory cells correspond to at least one redundant column of redundant memory cells wherein each redundant memory cell in the at least one redundant column stores same data as the memory cell in a same row.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: June 5, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Chen-Yi Huang, Jiaqi Yang, Cheng-Tai Huang
  • Patent number: 9928921
    Abstract: There is provided a non-volatile memory circuit including: plural storage element sections each including a zener zap device and a switch section that connects an anode of the zener zap device to an output terminal during data reading; and wherein cathodes of respective zener zap devices of the plural storage element sections are commonly connected so as to be connected to a power supply employed in the writing or to a power supply employed in the reading, wherein the output terminals of the plural storage element sections are commonly connected to an input terminal of a detector, an anode of each of the storage element sections being connected to a ground voltage during data writing, and wherein the switch section is switched ON during data reading so as to connect the anode of the storage element section through the output terminal to the input terminal of the detector.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: March 27, 2018
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Masayuki Otsuka
  • Patent number: 9800414
    Abstract: Embodiments relate to the authentication of a semiconductor. An identification circuit disposed within a package of an integrated circuit, and the identification circuit includes carbon-nanotube transistors configured to generate an encryption key.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: October 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Shu-Jen Han
  • Patent number: 9791482
    Abstract: A power loss protection integrated circuit includes a current switch circuit portion (eFuse) and an autonomous limit checking circuit. The limit checking circuit includes an input analog multiplexer, an ADC, a plurality of capture registers, a state machine, and a flag output terminal. For each capture register, the limit checking circuit further includes an associated lower limit register and an associated upper limit register. The state machine controls the multiplexer and the capture registers so the ADC digitizes voltages on various nodes to the monitored, and stores the results into corresponding capture registers. In integrated circuit has circuitry that allows both a high voltage as well as a high current to be monitored. The value in a capture register is compared to upper and lower limit values. If any capture value is determined to be outside the limits, then a digital flag signal is asserted onto the flag output terminal.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: October 17, 2017
    Assignee: Active-Semi, Inc.
    Inventors: John H. Carpenter, Jr., Brett E. Smith, Hiroshi Watanabe
  • Patent number: 9780030
    Abstract: An integrated circuit according to an embodiment includes: an anti-fuse element including a first terminal and a second terminal; a fuse element including a third terminal connected to the second terminal, and a fourth terminal; a first wiring line connected to the first terminal of the anti-fuse element; and a drive circuit configured to supply a plurality of potentials to the first terminal of the anti-fuse element, the drive circuit being connected to the first wiring line, the potentials being different from each other.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: October 3, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masato Oda, Mari Matsumoto, Kosuke Tatsumura, Shinichi Yasuda
  • Patent number: 9762391
    Abstract: Embodiments relate to the authentication of a semiconductor. An identification circuit disposed within a package of an integrated circuit, and the identification circuit includes carbon-nanotube transistors configured to generate an encryption key.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: September 12, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Shu-Jen Han
  • Patent number: 9741403
    Abstract: Memory die can be stacked to form a three-dimensional integrated circuit. For example, through-silicon vias (TSVs) can permit signals to pass vertically through the three-dimensional integrated circuit. Disclosed herein are apparatuses and methods to perform post package trimming of memory die, which advantageously permits the memory die to be trimmed after the memory die is stacked, such that test and trimming characteristics are relatively close to that which will be actually be encountered.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: August 22, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Alan J. Wilson, Jeffrey P. Wright
  • Patent number: 9685958
    Abstract: A locking system for an integrated circuit (IC) chip can include an arrangement of one or more antifuse devices in a signal path of the IC chip. The antifuse devices can be configured to operate in a first state, corresponding to a normally open switch, to inhibit normal operation of the IC chip, and to transition from the first state to a permanent second state, corresponding to a closed switch, in response to a program signal applied to at least one terminal of the IC chip to enable the normal operation of the IC chip.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: June 20, 2017
    Assignee: Case Western Reserve University
    Inventors: Swarup Bhunia, Abhishek Basak, Yu Zheng
  • Patent number: 9640275
    Abstract: A one-time memory control apparatus is obtained that prevents erroneous opening of a fuse from causing logic conversion and enhances the reliability. The one-time memory control apparatus includes an opening current creation fuse C opening switch and an opening current creation fuse D opening switch that each allow a fuse opening current from a fuse opening current creation circuit to flow in response to an opening enable signal, and a fuse opening permission signal creation circuit that receives respective logic signals corresponding to the states of fuse opening currents that flow through an opening current creation fuse C and an opening current creation fuse D, and that creates a fuse opening permission signal.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: May 2, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masahiro Nakajima, Katsuyuki Sumimoto, Junya Sasaki, Akio Kamimurai, Keisuke Katsurada
  • Patent number: 9594998
    Abstract: In embodiments of the present invention improved capabilities are described for RFID tags with hardened memory, where the memory comprises a plurality of one time programmable (OTP) non-volatile memory locations for storing data, wherein the plurality of OTP non-volatile memory locations are configured to emulate a hardened memory system that retains data stored in the OTP non-volatile memory locations, wherein the data stored is retained after exposure of the RFID tag to an ionizing radiation exposure with an exposure level greater than 25 kGy.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: March 14, 2017
    Assignee: TEGO, INC.
    Inventors: Timothy P. Butler, David Puleston, Javier Berrios, Steve Beckhardt, Robert W. Hamlin, Larry Moore, Leonid Mats
  • Patent number: 9583210
    Abstract: Various systems and methods for implementing fuse-based integrity protection are described herein. A system for validating a read-only memory (ROM), the system comprising a ROM reader logic, implemented at least partly in hardware, to: access a read-only memory (ROM) having a plurality of permanently programmable electric couplings (PPECs), the PPECs having been programmed; survey a number of permanently altered PPECs in the set of PPECs to produce a counter value; read a binary representation of the counter value from PPEC values stored as a PPEC signature; and read a binary representation of the binary complement of the counter value from PPEC values in the PPEC signature; and a ROM validation logic, implemented at least partly in hardware, to verify the integrity of the ROM using a combination of at least two of: the counter value, the binary representation of the counter value, and the binary representation of the binary complement of the counter value.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 28, 2017
    Assignee: Intel Corporation
    Inventor: Michael Berger
  • Patent number: 9557364
    Abstract: System and method for testing the reliability of a fuse blow condition. The fuse blow detection circuit includes a fuse circuit comprising a fuse having a first end coupled to ground. A common node is coupled to the second end of the fuse. A pre-charge circuit is coupled to the common node for pre-charging the common node to a pre-charged HIGH level. An inverter includes an inverter output and an inverter input, wherein the inverter input is coupled to the common node. A feedback latch is coupled between a voltage source and ground, and includes a latch input that is coupled to the inverter output and a latch output coupled to the common node. A test circuit is included that is coupled to the common node, wherein in a normal mode the test circuit adds strength to the feedback latch for purposes of maintaining the common node at the pre-charged HIGH level, such that in a test mode the feedback latch is weaker than in the normal mode for purposes of maintaining the common node at the pre-charged HIGH level.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: January 31, 2017
    Assignee: TESSERA, INC.
    Inventor: Michael Curtis Parris
  • Patent number: 9543037
    Abstract: To provide an electrical fuse that is connected to a detection node via a selective transistor, a precharge transistor that precharges the detection node in a state where the selective transistor is off; a bias transistor that passes a bias current to the detection node in a state where the selective transistor is on and the precharge transistor is off, and a detection circuit that detects a potential of the detection node in a state where the bias current is flowing into the detection node, wherein the bias transistor reduces an amount of the bias current in a stepwise manner or a continuous manner.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: January 10, 2017
    Assignee: Longitude Semiconductor S.A.R.L.
    Inventors: Shuichi Kubouchi, Daiki Nakashima
  • Patent number: 9514840
    Abstract: A semiconductor memory device includes a fuse portion including a first fuse set having a plurality of first fuses assigned for a first mode and a second fuse set having a plurality of second fuses assigned for a second mode, and a program portion suitable for programming an available fuse among the first fuses included in the first fuse set or programming the second fuses included in the second fuse set in response to a repair control signal in the second mode.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: December 6, 2016
    Assignee: SK Hynix Inc.
    Inventor: Ga-Ram Park
  • Patent number: 9508641
    Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: November 29, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Iwamoto, Kazushi Kono, Masashi Arakawa, Toshiaki Yonezu, Shigeki Obayashi
  • Patent number: 9478493
    Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: October 25, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Iwamoto, Kazushi Kono, Masashi Arakawa, Toshiaki Yonezu, Shigeki Obayashi
  • Patent number: 9466391
    Abstract: A semiconductor device that includes a fuse array including a plurality of fuses, and suitable for operating using a fuse operation voltage in a fuse operation period, a first voltage generation block suitable for generating an internal voltage based on a first target level, a second voltage generation block suitable for generating the fuse operation voltage based on a second target level in the fuse operation period, and generating the fuse operation voltage based on the first target level outside the fuse operation period, and a connection control block suitable for disconnecting a line of the internal voltage and a line of the fuse operation voltage in the fuse operation period, and connecting the line of the internal voltage and the line of the fuse operation voltage outside the fuse operation period.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: October 11, 2016
    Assignee: SK Hynix Inc.
    Inventor: Yun-Seok Hong
  • Patent number: RE46970
    Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: July 24, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuan-Fu Chen, Yin-Jen Chen, Tzung-Ting Han, Ming-Shang Chen