Abstract: A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.

Abstract: A redundancy circuit includes a plurality of block address lines, a first fuse array storing a first data, a plurality of first local lines configured to supply a verification voltage to the first fuse array in response to a signal of a corresponding line among the plurality of block address lines, a second fuse array storing a second data, a plurality of second local lines configured to supply the verification voltage to the second fuse array in response to a signal of a corresponding line among the plurality of block address lines, and a plurality of verification lines configured to check the first data of the first fuse array and the second data of the second fuse array, wherein the plurality of verification lines are shared by the first fuse array and the second fuse array and are disposed between the first fuse array and the second fuse array.

Abstract: An anti-fuse circuit in which anti-fuse program data may be monitored outside of the anti-fuse circuit and a semiconductor device including the anti-fuse circuit are disclosed. The anti-fuse circuit includes an anti-fuse array, a data storage circuit, and a first selecting circuit. The anti-fuse array includes one or more anti-fuse blocks including a first anti-fuse block having a plurality of anti-fuse cells and the anti-fuse array is configured to store anti-fuse program data. The data storage circuit is configured to receive and store the anti-fuse program data from the anti-fuse array through one or more data buses. The first selecting circuit is configured to output anti-fuse program data of a selected anti-fuse block of the one or more anti-fuse blocks in response to a first selection signal.

Abstract: A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.

Abstract: A data write circuit of a semiconductor apparatus includes a data path configured to receive a pattern signal and generate a first delayed pattern signal; a data strobe signal path configured to receive the pattern signal and generate a second delayed pattern signal; a data latch block configured to latch the first delayed pattern signal in response to the second delayed pattern signal, and output a resultant signal; and a control block configured to generate the pattern signal, and vary a delay time of the data path according to a result of comparing phases of a latched signal of the data latch block and the pattern signal.

Abstract: A semiconductor integrated circuit includes a fuse circuit comprising a fuse configured to generate a fuse state signal corresponding to a rupture state of the fuse in response to an enable signal, a fuse state decision unit configured to determine whether or not the fuse state signal is normal based on a test signal, and generate an output enable signal according to a determination result, and a driving unit configured to output the fuse state signal in response to the output enable signal.

Abstract: Methods and systems to stress-program a first integrated circuit (IC) block to output a pre-determined value upon activation/reset, such as to support time-zero compensation/trimming. To program, the first block is configured with first-block program parameters to cause the first block to output a pre-determined value. The first block is stressed while configured with the first-block program parameters, to cause the first block to output the pre-determined value without the first-block program parameters. The first block may include a latch designed as a fully balance circuit and may be asymmetrically stressed to alter a characteristic of one path relative to another. The pre-determined value may be selected to compensate for process corner variations and/or other random variations.

Abstract: A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit for a 3D IC to repair defects, trim devices, or adjust parameters is presented here. At least one die in a 3D IC can be built with at least one low-pin-count OTP memory. The low-pin-count OTP memory can be built with a serial interface such as I2C-like or SPI-like of interface. The pins of the low-pin-count OTP in at least one dies can be coupled together to have only one set of low-pin-count bus for external access. With proper device ID, each dies in a 3D IC can be accessed individually for soft programming, programming, erasing, or reading. This technique can improve the manufacture yield, device, circuit, or logic performance or to store configuration parameters for customization after 3D IC are built.

Abstract: Provided is an OTP memory cell including a first antifuse unit, a second antifuse unit, a select transistor, and a well region. The first and the second antifuse unit respectively include an antifuse layer and an antifuse gate disposed on a substrate in sequence. The select transistor includes a select gate, a gate dielectric layer, a first doped region, and a second doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The first and the second doped region are respectively disposed in the substrate at two sides of the select gate, wherein the second doped region is disposed in the substrate at the periphery of the first and the second antifuse unit. The well region is disposed in the substrate below the first and the second antifuse unit and is connected to the second doped region.

Abstract: A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also include that upon an event, using a value in the latch in an eFuse which subsequently selects the redundant element.

Abstract: The present invention discloses a small-grain three-dimensional memory (3D-MSG). Each of its memory cells comprises a thin-film diode with critical dimension no larger than 40 nm. The thin-film diode comprises at least a small-grain material, whose grain size G is substantially smaller than the diode size D. The small-grain material is preferably a nano-crystalline material or an amorphous material. The critical dimension f of the small-grain diode is smaller than the critical dimension F of the single-crystalline transistor.

Abstract: A method and apparatus for managing memory in an electronic system is described. The method includes determining a failure in an element of the memory array that is repairable by a redundant element. The method may further include using a latch to identify the redundant element. The method may also include that upon an event, using a value in the latch in an eFuse which subsequently selects the redundant element.

Abstract: A column repair circuit of a semiconductor memory apparatus includes a plurality of mats and performs a column repair operation to replace failed cells among a plurality of memory cells provided in the mats. The column repair circuit includes two or more fuse units configured to perform the column repair operation. Each of the fuse units includes a plurality of fuses, and is configured in such a manner that m mats correspond to one fuse or n mats correspond to one fuse, where m and n are natural numbers equal to or more than 1 and different from each other.

Abstract: A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit. In one embodiment, the low-pin-count non-volatile (NVM) memory can use only one external control signal and one internal clock signal to generate start, stop, device ID, read/program/erase pattern, starting address, and actual read/program/erase cycles. When programming or erasing begins, toggling of the control signal increments/decrements a program or erase address and a pulse width of the control signal determines the actual program or erase time. A data out of the low-pin-count non-volatile (NVM) memory can be multiplexed with the control signal. Since the clock signal can be derived and shared from the system clock of the integrated circuit, the NVM memory need only have one external control pin for I/O transactions to realize a low-pin-count interface.

Abstract: An apparatus is contemplated for storing and providing configuration data to a microprocessor. The apparatus has a core, disposed on a die, and a fuse array, disposed on the die and coupled to the core, where the fuse array comprises a plurality of semiconductor fuses programmed with compressed configuration data for the core, where the compressed configuration data is generated by compression of data within a virtual fuse array that corresponds to the core, and where the core accesses and decompresses the compressed configuration data upon power-up/reset, for initialization of elements within the core.

Abstract: Provided is a semiconductor non-volatile memory device capable of improving the accuracy of trimming by creating a written state before data is written into a non-volatile memory element. The semiconductor non-volatile memory device includes: a written data transmission circuit for transmitting written data to a non-volatile memory element; a first switch connected between the non-volatile memory element and a data output terminal; a third switch connected to an output terminal of the written data transmission circuit; and a control circuit for controlling the respective switches. When a test mode signal is input, the control circuit turns on only the first switch and the third switch so as to control the written data to be output to the data output terminal before data is written into the non-volatile memory element.

Abstract: Methods and systems that extend the capability of fuse elements, anti-fuse elements, and combinations thereof to enable multi-time programmable memory elements are provided. Accordingly, significantly reduced area requirements and control circuitry complexity of memory elements is enabled. The provided methods and systems can be used in non-volatile memory storage, and are suitable for use in system on chip (SoC) products.

Abstract: A memory device includes an anti-fuse cell array including a plurality of anti-fuse cells. Each anti-fuse cell includes a first cell transistor connected to a common node, a second cell transistor connected to the common node, and an access transistor connected to the common node. The first cell transistor is configured to store data and the second cell transistor is configured to store data when the first cell transistor has defect data.

Abstract: In accordance with some embodiments, instead of providing replacement rows, an area within a fuse array may be reserved for storing addresses of bits that are defective. Then these bits can be readily repaired by simply reading the stored state of identified defective bit, and inverting the stored state of the identified defective bit to get the correct output.

Abstract: An apparatus has a fuse array, a device programmer, and a plurality of cores. The fuse array is disposed on a die, where the fuse array comprises a plurality of semiconductor fuses. The device programmer is coupled to the fuse array and is configured to access the configuration data, to compress the configuration data to yield compressed configuration data, and to program the fuse array with the compressed configuration data. The plurality of cores is disposed separately on the die and is coupled to the fuse array, where each of the plurality of cores accesses and decompresses all of the compressed configuration data upon power-up/reset, for initialization of elements within the each of the plurality of cores.

Abstract: An apparatus has a fuse array, a cache memory, and cores. The fuse array is disposed on a die, into which is programmed the configuration data. The fuse array includes a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores compressed cache correction data. The second plurality of fuses stores compressed fuse correction data that indicates locations and values corresponding to one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The cores are disposed on the die, where each of the cores accesses the fuse array upon power-up/reset. The each of the cores includes a cache fuses decompressor that changes the states according to the locations and the values, decompresses the compressed cache correction data, and distributes decompressed cached correction data to initialize the cache memory.

Abstract: An apparatus is contemplated for storing and providing configuration data to a microprocessor. The apparatus has a core, disposed on a die, and a fuse array, disposed on the die and coupled to the core, where the fuse array comprises a plurality of semiconductor fuses programmed with compressed configuration data for the core, where the compressed configuration data is generated by compression of data within a virtual fuse array that corresponds to the core, and where the core accesses and decompresses the compressed configuration data upon power-up/reset, for initialization of elements within the core.

Abstract: Exemplary embodiments of the present invention disclose a method and system for substituting a group of memory cells for a defective group of memory cells in a memory. In a step, an exemplary embodiment replaces a signal path to a group of defective memory cells with a signal path to a redundant group of memory cells. In another step, an exemplary embodiment isolates the signal path to the redundant group of memory cells from a load imposed by the signal path to the replaced group of defective memory cells.

Abstract: When writing into an antifuse memory element finishes, a value of resistance of the memory element rapidly decreases; accordingly, an output voltage of a boosting circuit which produces a writing voltage rapidly decreases. By detecting a change in the output voltage of the boosting circuit to control a writing command, the writing operation can be stopped immediately after the memory element is shorted. Thus, unnecessary current consumption caused by continuing a writing operation on the shorted memory element can be suppressed.

Abstract: A one-time programmable memory includes a first one-time programmable memory cell including a fuse core having an input terminal for receiving a trim signal, an output terminal for providing a sense signal, and a fuse. The fuse core conducts current through the fuse in response to the trim signal. The one-time programmable memory cell also includes a sense circuit having an input terminal coupled to the output terminal of the fuse core, and an output terminal for providing a termination signal, and a logic circuit having a first input terminal for receiving a program enable signal, a second input terminal for receiving a data signal, a third input terminal coupled to the output terminal of the sense circuit for receiving the termination signal, and an output terminal coupled to the input terminal of the fuse core for providing the trim signal.

Abstract: A semiconductor device has an electrical fuse element including: a first filament; a second filament connected to the first filament; and a series readout section connected to an end of the first filament opposite to another end of the first filament connected to the second filament, the series readout section reading series resistance of the first filament and the second filament.

Abstract: A logic chip and memory chip stacked over the logic chip, the logic chip having a first surface facing the memory chip and a second surface opposite to the first surface and including: first and second internal input/output circuit units for exchanging signals; first external input/output circuit unit for exchanging signals through first external input/output pads formed according to an external interface standard of a first memory over the second surface; and second external input/output circuit unit for exchanging signals through second external input/output pads formed according to an external interface standard of a second memory over the second surface, wherein semiconductor device operates in one of a first mode in which the first internal input/output circuit unit and the first external input/output circuit unit are enabled and a second mode in which the first and second internal input/output circuit units and the second external input/output circuit unit are enabled.

Abstract: An integrated circuit includes a plurality of internal circuits, an e-fuse array circuit configured to store a data used by the internal circuits, and a fuse circuit configured to store a trimming data to set the e-fuse array circuit.

Abstract: In embodiments of the present invention improved capabilities are described for a Radio Frequency ID (RFID) tag that contains multiple Radio Frequency (RF) network nodes that may include memory storage for the RFID tag, the memory storage may include one time programmable (OTP) memory and many time programmable (MTP) memory and the storage of the information may be within the OTP and MTP memory.

Abstract: A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.

Abstract: The present disclosure provides a reference one time programmable (OTP) cell, wherein the reference OTP cell can generate a reference bias current in at least a programmed-on configuration; a current mirror coupled to an output of the OTP cell, wherein the current mirror includes at least two gate-coupled field effect transistors (FETs); wherein a current gain of a second of the two FETS is a fraction less than one of a first of the at least two gate-coupled FETs; a programmable OTP memory bit element (OTPMBE) coupled to an input of the current mirror; and a comparator having an input coupled to a node between the OTPMBE and the current mirror.

Abstract: A low-pin-count non-volatile memory (NVM) embedded an integrated circuit can be accessed without any additional pins. The NVM has one or more memory cells and at least one of the NVM cells can have at least one NVM element coupled to at least one selector and to a first supply voltage line. The selector can be coupled to a second supply voltage line and has a selecting signal. The integrated circuit can include at least one test mode detection circuit to activate a test mode upon detecting an abnormal (or out of normal) operation condition(s). Once a test mode is activated, at least one I/O or supply voltage of the integrated circuit can be used as the I/O or supply voltage of the NVM to select at least one NVM cell for read, program into nonvolatile, or volatile state. At least one NVM cell can be read during ramping of at least one supply voltage line.

Abstract: One or more techniques or systems for controlling a voltage divider are provided herein. In some embodiments, a control circuit is configured to bias a pull up unit of a voltage divider using an analog signal, thus enabling the voltage divider to be level tunable. In other words, the control circuit enables the voltage divider to output multiple voltage levels. Additionally, the control circuit is configured to bias the pull up unit based on a bias timing associated with a pull down unit of the voltage divider. For example, the pull up unit is activated after the pull down unit is activated. In this manner, the control circuit provides a timing boost, thus enabling the voltage divider to stabilize more quickly.

Abstract: A semiconductor apparatus includes a signal transmission block and signal reception blocks. The signal transmission block is disposed in a first chip and configured to transmit fuse information in synchronization with transmission control signals. The signal reception blocks are respectively disposed in the first chip and a second chip and configured to receive the fuse information in synchronization with reception control signals.

Abstract: A programmable crossbar array with inline fuses includes a layer of row lines and a layer of column lines with the row lines crossing over the column lines to form junctions and resistive memory elements sandwiched between row lines and a column lines at the junctions. Inline fuses are located in either the row lines, column lines or both. The inline fuses are interposed between the support circuitry and the resistive memory elements. A method for mitigating shorts in a crossbar array is also provided.

Abstract: Circuits, systems and techniques for testing a One-Time Programmable (OTP) memory are disclosed. An extra OTP bit can be provided as a test sample to be programmed. The programmed extra OTP bit can be read with any virgin cells in the OTP memory alternatively to generate a stream of logic 0 and logic 1 data so that every row or column path can be tested and the outcome can be observed in a pseudo-checkerboard pattern or other predetermined pattern. By carefully setting control signals, checkerboard-like pattern can be generated without actual programming any OTP cells in the memory array.

Abstract: A reprogrammable memory, which can be, programmed a limited number of times. A plurality of one-time programmable elements are combined by a logic arrangement such that the output of that logic arrangement may be reprogrammed a limited number of times.

Abstract: There is described a passive heater-and-diode multiplexing network for selective addressing of thermally-coupled and electrically-disconnected fuses within a passive device network (resistor/capacitor/inductor) or within an application circuit.

Abstract: A resistive memory device and a sensing margin trimming method are provided. The resistive memory device includes a memory cell array and a trimming circuit. The memory cell array has a plurality of resistive memory cells. The trimming circuit generates a trimming signal according to a characteristic distribution shift value of the resistive memory cells. With the inventive concept, although a characteristic distribution of memory cells is varied, an erroneous read operation is minimized or reduced by securing a sensing margin stably. Accordingly, a fabrication yield of the resistive memory device is bettered.

Abstract: A semiconductor device includes memory blocks MB1 and MB2 and redundancy determination circuit 25 that can enter a normal operation mode that accesses either memory block MB1 or memory block MB2 and a refresh mode that simultaneously accesses both memory block MB1 and memory block MB2. In response to normal memory cell NMC that belongs to at least one of memory blocks MB1 and MB2 being replaced by redundant memory cell RMC in the refresh mode, redundancy determination circuit 25 deactivates normal cell area NCA to which normal memory cell NMC that is a source of replacement belongs, and activates redundant cell area RCA to which redundant memory cell RMC that is to be replaced belongs and normal cell area NCA to which normal memory cell NMC that is not being replaced belongs.

Abstract: A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.

Abstract: Systems and methods are disclosed that may include a first layer comprising a first redundant memory element, an input/output interface, a first layer fuse box, and a fuse blowing control. These systems and methods also may include a second layer coupled to the first layer through a first connection comprising a second layer memory element and a second layer fuse box coupled to the first redundant memory element. In addition, these systems and methods may further include a redundancy register coupled to the first layer, wherein upon the failure of part of the second layer memory element, the redundancy register provides information to the fuse blowing control that allocates part of the first redundant memory element to provide redundancy for the failed part of the second layer memory element by blowing elements in the first layer fuse box and the second layer fuse box.

Abstract: An antifuse according to an embodiment of the invention herein can include a depletion mode metal oxide semiconductor field effect transistor (“MOSFET”) having a conduction channel and a metal gate overlying the conduction channel. A cathode and an anode of the antifuse can be electrically coupled to the gate and spaced apart from one another in a direction the gate extends, such that the antifuse is programmable by driving a programming current between the cathode and the anode to cause material of the metal gate to migrate away. The gate may be configured such that, under appropriate biasing conditions, when the antifuse is unprogrammed, the conduction channel is turned on unless a voltage above a first threshold voltage is applied to the gate to turn off the conduction channel. The gate can be configured such that when the antifuse has been programmed, the conduction channel remains turned on even if a voltage above the first threshold voltage is applied between the gate and a source region of the MOSFET.

Abstract: A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse element has been blown, the control circuit inhibits at least one of writing and erasing from being done on the second storage area.

Abstract: A semiconductor device includes a pulse generation circuit configured to generate an enable pulse signal, which is activated in response to an active command signal and deactivated in response to a column command signal, and a plurality of fuse circuits configured to store repair addresses for a column repair and to output stored repair addresses in response to the enable pulse signal.

Abstract: A configurable memory circuit is provided. The memory circuit includes an inverter coupled to another inverter as back-to-back inverters. A programmable switch is placed on each side of the memory circuit. The programmable switches are used to configure the memory circuit. The memory circuit, depending on the configuration of the programmable switches and the back-to-back inverters, may operate as a ROM that stores a logic high value, a ROM that stores a logic low value, or a RAM.

Abstract: An apparatus includes a semiconductor fuse array and a plurality of cores. The semiconductor fuse array is disposed on a die, into which is programmed configuration data. The array has a first plurality of fuses and a second plurality of fuses. The first plurality of fuses stores the configuration data in an encoded and compressed format. The second plurality of fuses stores first compressed fuse correction data that indicates locations and values corresponding to a first one or more fuses within the first plurality of fuses whose states are to be changed from that which was previously stored. The plurality of cores is disposed on the die, where each of the plurality of cores is coupled to the array and accesses all of the compressed configuration data during power-up/reset, for initialization of elements within the each of the plurality of cores.

Abstract: An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line.

Abstract: A semiconductor device includes a memory cell array having short and long sides, a row decoder, a row fuse circuit, a column decoder and a column fuse circuit. The row decoder, the row fuse circuit and the column fuse circuit are arranged along the long side of the memory cell array. The column decoder is arranged along the short side of the memory cell array.

Abstract: Apparatuses and methods for sensing fuse states are disclosed herein. An apparatus may include an array having a plurality of sense lines. A plurality of cells may be coupled to a sense line of the plurality of sense lines. A fuse sense circuit may coupled to the sense line of the plurality of sense lines and configured to receive a sense voltage from a cell of the plurality of cells. The sense voltage may be based, at least in part, on a state of a fuse corresponding to the cell of the plurality of cells. The fuse sense circuit may further be configured to compare the sense voltage to a reference voltage to provide a fuse state control signal indicative of the state of the fuse.