Abstract: Technology is disclosed herein for preventing erase disturb in NAND. Erase voltages are applied to a source line and bit lines associated with selected memory cells, while applying an erase enable voltage to word lines connected to the selected cells. Preventing erase disturb may include raising the channel potential of unselected memory cells to a source line voltage that has a sufficiently low magnitude to not erase the unselected cells given a voltage on word lines connected to the unselected cells. The unselected cells share bit lines with the selected cells and may also share word lines. Preventing erase disturb may also include applying voltages to the select transistors that prevent the erase voltage from passing from the shared bit lines to the channels of the unselected cells. The voltages decrease from the bit lines to the unselected memory cells and may prevent GIDL generation. Current consumption is kept low.

Abstract: A power management system includes a capacitor, control logic configured to determine a wait time in response to a comparison of a voltage of the capacitor to a threshold voltage and to initiate a startup upon expiration of the wait time, and a control circuit configured to charge the capacitor, discharge the capacitor, and provide the voltage of the capacitor to the control logic.

Abstract: A communication line is connected to first and second chips, and held at a first signal level. A monitor circuit changes a signal level of the communication line from the first signal to a second signal level while one of the first and second chips uses a current larger than a reference current. When the signal level of the communication line is the second signal level, the other of the first and second chips is controlled to a wait state that does not transfer to an operating state of using a current larger than the reference current.

Abstract: A device includes a first power rail for a first power domain and a second power rail for a second power domain. A first circuit block is connected to the first power rail and a second circuit block is connected to the second power rail. The first and second circuit blocks are both connected to a virtual VSS terminal. A footer circuit is connected between the virtual VSS terminal and a ground terminal, and the footer circuit is configured to selectively control a connection between the virtual VSS terminal and the ground terminal.

Abstract: Provided are a memory detection method, a computer device and a storage medium. The method includes: initializing all storage units in a storage unit array; determining a plurality of target wordlines, two adjacent target wordlines being provided with a plurality of interfering wordlines therebetween; turning on the target wordlines, and performing a write operation on storage units connected to the target wordlines; performing repeatedly turn-on and turn-off of the interfering wordlines for a plurality of times; and performing a read operation on the storage units connected to the target wordlines. A write operation is performed on the storage units connected to the interfering wordlines by means of forced current sinking.

Abstract: A power control circuit includes a power control signal generation circuit configured to generate a voltage control signal according to a deep sleep command for operating a semiconductor apparatus in a deep sleep mode; a voltage divider circuit having a division ratio that is changed according to the voltage control signal, and configured to generate a divided voltage by dividing an internal voltage at the changed division ratio; a comparator configured to generate a detection signal by comparing a reference voltage to the divided voltage; an oscillator configured to generate an oscillation signal according to the detection signal; and a pump configured to generate the internal voltage according to the oscillation signal.

Abstract: A memory, a method controlling method and a system are disclosed. The memory includes: an array of memory cells; a power manager; an instruction decoder; a controller; and an I/O interface, including a chip select pin. In the standby state, the instruction decoder and controller are enabled; in the power-down state, the instruction decoder is enabled; and in the deep power-down state, they are all disabled. In response to receiving a chip select signal, the memory enters the power-down state from the deep power-down state. The memory of the present disclosure provides the deep power-down state that disables the decoder, and the memory in the deep power-down state exits directly to the power-down state to achieve some functions without enabling all components, thereby reducing power consumption.

Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

Abstract: There is provided a method for accessing a memory cell of a plurality of memory cells that are part of a memory unit, the memory cells being grouped into a plurality of memory cell groups, wherein each memory cell group is associated with one or more local bit lines with each of the one or more local bit lines being operatively connected to a corresponding global bit line via a passgate comprising a PMOS transistor. The method comprises connecting each of the one or more local bit lines to the corresponding global bit line by decreasing a gate voltage that is applied to a gate of the corresponding PMOS transistor to a value that is sufficient to allow the PMOS transistor to conduct, wherein the value of the gate voltage that is sufficient to allow the PMOS transistor to conduct is either a positive or negative voltage.

Abstract: A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.

Abstract: A device includes a first virtual power line, a second virtual power line, a first delay circuit, and a first wakeup detector. The first virtual power line and the second virtual power line are coupled to a power supply correspondingly through a first group of transistor switches and a second group of transistor switches. The first delay circuit is coupled between gate terminals of the first group of transistor switches and gate terminals in the second group of transistor switches. The first wakeup detector is configured to generate a first trigger signal after receiving a signal from the first delay circuit.

Abstract: An operating method of a memory system including a memory device including a plurality of memory chips is provided. The operating method includes setting a parameter indicating a number of the memory chips allowed to operate in parallel for each of a plurality of operation statuses, based on information about power consumption of each of the plurality of operation statuses of a memory chip among the memory chips; obtaining information about an operation status of each of the plurality of memory chips; and scheduling data access across a plurality of channels respectively corresponding to the plurality of memory chips, based on the parameter and the information about the operation status of each of the plurality of memory chips.

Abstract: Aspects of a storage device including a memory and a controller are provided. The memory can include memory dies that draw a current from a current source during a program operation. The controller may monitor for an alarm signal from the memory dies on a first common channel between the controller and the memory dies. The alarm signal indicates that a corresponding memory die is entering an operational state that draws a peak current from the current source for the program operation. The controller can receive, from the memory dies, one or more alarm signals on the first common channel within a predetermined threshold time. The controller can transmit a postpone signal on a second common channel to the memory dies based on the one or more alarm signals received within the predetermined threshold time.

Abstract: A memory module may include a power source, a memory device, and a power controller. The power source provides at least one power supply voltage. The memory device operates by being supplied with at least one memory power supply voltage. The power controller supplies the at least one memory power supply voltage by changing a voltage level of the at least one power supply voltage based on operation modes of the memory device.

Abstract: In each of two or more pipelined subsystems, the relative amount of time that the processing cores are idle may be determined. If the idle ratio is below a threshold, the clock frequency and voltage may be adjusted using dynamic clock and voltage scaling (DCVS) based on a power limit. However, if the idle ratio exceeds the threshold, the clock frequency and voltage may be decreased without regard to the power limit.

Abstract: Disclosed herein is an apparatus that includes a first address generator generating a first address in response to a clock signal; a second address generator generating a second address corresponding to the first address; a first detection circuit activating a first signal when the second address matches with a third address; a second detection circuit activating a second signal when the second address indicates a predetermined state; a first latch circuit latching the first address in response to the first signal; a second latch circuit latching the first address in response to the second signal; a third detection circuit activating a third signal when the first address matches with an address stored in the first latch circuit; a fourth detection circuit activating a fourth signal when the first address matches with an address stored in the second latch circuit; and a first selector selecting the third or fourth signal.

Abstract: Implementations described herein provide a component system that reconfigures interchangeable computing device components based on a current state of the computing device. The current state of the computing device is determined based on a hardware configuration of the device, a shell configuration describing software and firmware of the device, and/or context information describing a relationship between the device and its surrounding environment. Based on the current state of the computing device, an output is determined that specifies interchangeable components are to be activated and deactivated. The output is useable to reconfigure individual computing device functionalities, control a manner in which applications execute on the computing device, and adapt the computing device to its current state.

Abstract: A power consumption/power backup-based ride-through system includes a power supply system that is configured to supply power to the one or more components. A power backup device is coupled to the one or more components and the power supply system, and operates to monitor an amount of power provided by the power supply system to the one or more components. Based on the amount of power provided by the power supply system to the one or more components, as well as characteristics of the power backup device in some embodiments, the power backup device determines a ride-through time period for which the power backup device is capable of powering the one or more components. When the power backup device detects a loss of power to the one or more components, it powers the one or more components for the ride-through time period.

Abstract: An electronic device, and more particularly, a storage device for mitigating periods where a peak current occurs from currents overlapping is provided. The storage device includes a memory device including a plurality of dies and a memory controller controlling the memory device. The memory device generates status information about an amount of current consumed by each of the plurality of dies during a busy period when all of the plurality of dies are in a busy state, and wherein the memory controller determines, based on the status information, whether peak currents for multiple dies of the plurality of dies are consumed in a common sub-period of a plurality of sub-periods which span the busy period, and when it is determined that peak currents for multiple dies are consumed in the common sub-period, the memory controller controls the memory device to suspend an operation on a die among the plurality of dies.

Abstract: A semiconductor device includes: a first buffer circuit configured to receive a chip select signal in a power-down mode in response to a first select signal, a second buffer circuit configured to receive the chip select signal in an active mode in response to the first select signal, a power supply circuit configured to supply external power to a plurality of logic elements in the active mode in response to a second select signal, and not supply the external power to the plurality of logic elements in the power-down mode, and a select control circuit configured to transition a logic level of the second select signal at a first edge of a first chip select signal in the power-down mode, and then transition a logic level of the first select signal at a following second edge of the first chip select signal to exit from the power-down mode and enter the active mode.

Abstract: Methods, systems, and devices for power domain switches for switching power reduction are described. A device, such as a memory device, may receive an indication (e.g., a command) for a power domain component of the device to transition between states. The device may float first and second gate drivers. A pass gate may be used to connect (e.g., short) the first switch to the second switch. The pass gate may be deactivated to isolate the gates. The first and second gate drivers may be enabled, and the first and second gate drivers drive the first and second switches to disconnect the power domain component from a power source to deactivate the power domain component, or connect to the power source to activate the power domain component. The energy to switch between active and inactive states may thereby be reduced.

Abstract: The machine implemented method for operating at least one electronic system comprises detecting a pattern of use of plural control parameters in a path through a graph of operational context switches to reach a target operational context; storing a representation of the pattern in association with an indicator identifying the target operational context; responsive to detecting at least one of a request for a switch of operation from a source operational context to the target operational context, a trapping on a resource access, and a detection of a breakpoint, retrieving the representation in accordance with the indicator identifying the target operational context; and responsive to the retrieving, applying at least one control parameter to said at least one electronic system to match the pattern.

Abstract: A data storage system can connect a cache memory to a caching module, a host, and a data storage device. The caching module can employ one or more local controllers to generate a caching strategy in response to detected data storage operations and execute the caching strategy to divide the cache memory into a first pool having a first size and a second pool having a second size.

Abstract: A power management circuit suitable for a memory device and a memory device is provided. The power management circuit includes a first logic circuit, a second logic circuit, and a transmission gate. The first logic circuit is configured to receive an inverted first input signal and a second input signal and generates a first output signal. The second logic circuit is configured to receive a first input signal and the second input signal and generates a second output signal. The transmission gate is configured to receive the first output signal and generates a control signal to at least one power transistor coupled between the power management circuit and the memory device. During a standby mode, the power transistor is turned on to make a first voltage equal to a predetermined voltage and during a sleep mode, the control signal is coupled to a first voltage. The predetermined voltage is greater than the first voltage.

Abstract: The power consumption of a circuit block outside a microcomputer and inside the same system is reduced. An electric power control system includes a first power supply circuit, a semiconductor device having a first circuit block operated by electric power supplied from the first power supply circuit, a state holding circuit that holds an operation state in the first circuit block according to the electric power, an electric power control circuit that controls the electric power supplied to the first circuit block according to the operation state, and a first terminal that outputs a first state signal corresponding to the operation state, a second power supply circuit that controls the supply of electric power according to the first state signal, and a second circuit block operated by the electric power supplied from the second power supply circuit.

Abstract: A memory module may include a memory device and a power controller. The memory device may operate by being supplied with a first memory power supply voltage and a second memory power supply voltage. The power controller may receive a first power supply voltage and a second power supply voltage from a power source, and supply the first memory power supply voltage and the second memory power supply voltage by changing levels of the first power supply voltage and the second power supply voltage based on operation state information.

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

Abstract: Discussed herein are systems and methods for charging an access line to a nonvolatile memory cell during a standby state, such as to prevent or mitigate standby-state charge loss. An embodiment of a memory device comprises a memory cell, a string driver circuit, and a charging circuit. The string driver circuit is coupled to the memory cell via a local word line, and has a common p-well. The charging circuit, in response to a voltage of a global word line of the memory device falling below a reference voltage during a standby state, couple a supply voltage to the common p-well of the string driver circuit to charge the global word line to a positive bias potential. The memory device includes a leakage compensation circuit to compensate for the junction leakage.

Abstract: A sub-word line circuit having a phase driver circuit to provide a first phase signal and a second phase signal. The sub-word line circuit includes a sub-word line driver circuit having a pull-up circuit configured to receive the first phase signal and a global word line signal. The pull-up circuit is further configured to drive a local word line to follow the global word line signal when the first phase signal is at a first value and isolate the local word line from the global word line signal when the first phase signal is at a second value. The sub-word line circuit also includes a processing device that sets the first phase signal to the first value prior to the global word line signal entering an active state and sets the first phase signal to the second value only after the global word line signal has entered a pre-charge state.

Abstract: Methods, systems, and devices for variable filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two voltage sources to increase the capacitance provided by the access lines between the two voltage sources. In some cases, the access lines may be in electronic communication with capacitive cells that include a capacitive element and a selection component, and the voltage sources and access lines may be configured to utilize the capacitive elements and the capacitance between the access lines to generate an increase capacitance between the voltage sources. In some cases, decoders may be used to implement certain configurations that generate different capacitance levels. Similarly, sub-decoders may generate different capacitance levels by selecting portions of a capacitive array.

Abstract: A memory quality engine can improve the operation of a memory system by setting more effective operating parameters, disabling or removing memory devices unable to meet performance requirements, and providing evaluations between memory populations. These improvements can be accomplished by converting quality measurements of a memory population into CDF-based data, formulating comparisons of the CDF-based data to metrics for quality analysis, and applying the quality analysis. In some implementations, the metrics for quality analysis can use one or more thresholds, such as a system health threshold. Formulating the comparison to these metrics can include determining an area between a baseline frequency and a curve specified by the CDF-based data. In some implementations, this area can further be defined by a lowest frequency bound and/or can be compared as a ratio to an area of a rectangle that contains the CDF curve.

Abstract: An apparatus including a host interface and a registered clock driver interface. The host interface may be configured to receive an enable command from a host. The registered clock driver interface may be configured to perform power management for a dual in-line memory module, generate data for the dual in-line memory module, communicate the data, receive a clock signal and communicate an interrupt signal. The registered clock driver interface may be disabled at power on. The registered clock driver interface may be enabled by in response to the enable command. The apparatus may be implemented as a component on the dual in-line memory module.

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

Abstract: A wireless communication device (UE) may include a paging subsystem that performs paging-monitoring as part of wireless communications of the wireless communication device. The UE may place wireless communication system resources not required during paging-monitoring into either a low-power state or a power-down state, and those system resources may remain in one of those respective states during paging-monitoring. The wireless communication system resources not required during the paging-monitoring may include at least a wireless communications protocol stack used during the wireless communications of the UE, and at least system resources used for performing uplink related tasks independently of wireless communication system resources used for performing downlink related tasks.

Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.

Abstract: Provided is a memory device including: a memory array, including a flag memory array having a plurality of flag memory cells and a data memory array having a plurality of data memory cells, the corresponding flag memory cells being used to record whether the corresponding data memory cells have been written or not. In initialization, the flag memory array is initialized by the control circuit but the data memory array is not initialized.

Abstract: A semiconductor apparatus includes a state storage circuit configured to store information depending on a plurality of signals, and output the stored information as a power gating signal. The semiconductor apparatus may include a power gating circuit configured to provide or block a power supply voltage to an internal operation circuit as a driving voltage in response to the power gating signal.

Abstract: A memory system includes: a memory device; a cache memory suitable for caching a portion of a data stored in the memory device; and a read voltage controller suitable for controlling a level of a read voltage of the memory device by comparing a cache data in the cache memory with a data from the memory device corresponding to the cache data.

Abstract: An option code providing circuit includes a plurality of resistive random access memory cells and a controller. The controller determines whether to provide a control signal to operate a heavy forming operation on the resistive random access memory cells or not. Wherein, the controller performs a read operation on the resistive random access memory cells to determine a bit number of the resistive random memory cell which is heavy formed, and the option code is determined by the bit number of resistive random access memory cell which is heavy formed or a bit number of the resistive random access memory cell which is not heavy formed.

Abstract: The machine implemented method for operating at least one electronic system comprises detecting a pattern of use of plural control parameters in a path through a graph of operational context switches to reach a target operational context; storing a representation of the pattern in association with an indicator identifying the target operational context; responsive to detecting at least one of a request for a switch of operation from a source operational context to the target operational context, a trapping on a resource access, and a detection of a breakpoint, retrieving the representation in accordance with the indicator identifying the target operational context; and responsive to the retrieving, applying at least one control parameter to said at least one electronic system to match the pattern.

Abstract: A hardware coding mechanism is described. The coding mechanism may include a first encoder to produce a first code using a base number of bits and a second encoder to produce a second code using a supplementary number of bits. The second code and the first code together may be stronger than the first code alone. A mode register stored in a storage may specify whether a switch to the second encoder is open or closed: the first coder is always used.

Abstract: A word line decoder circuit located in a memory storage apparatus is provided. The memory storage apparatus includes a memory cell array. The word line decoder circuit includes a word line decoder and a power supply circuit. The word line decoder is coupled to a plurality of word lines of the memory storage apparatus. The power supply circuit is coupled to the word line decoder. The power supply circuit is configured to provide a first power to the word line decoder in a read mode, and provide a second power to the word line decoder in a standby mode. A voltage value of the first power is greater than or less than that of the second power.

Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a soft decision decoding on a codeword, generating a hard decision for each bit of the codeword at an end of the soft decision decoding, generating a hard decision for each bit of the codeword at an end of the soft decision decoding, generating a reliability determination for each hard decision and performing a hard decision decoding using the hard decision for each bit and reliability determination for each hard decision.

Abstract: An error checking and correcting (ECC) decoding method and apparatus are provided. A decoding circuit decodes a codeword using (or without using) reference information, wherein when the decoding circuit fails to decode a first codeword, the decoding circuit decodes a second codeword to produce decoded data. The decoding circuit checks whether a change has occurred from each codeword bit of the second codeword to a corresponding bit of the decoded data. In accordance with a bit position of the changed corresponding bit, the decoding circuit correspondingly changes the first codeword to a modified codeword, and/or correspondingly changes the reference information to modified information. The decoding circuit performs the ECC decoding again on the modified codeword (or the first codeword) using (or without using) the modified information.

Abstract: According to one embodiment, a memory controller includes: a memory I/F that reads a codeword written in a NAND memory as any one of hard-bit information, first soft-bit information, and second soft-bit information; a codeword processor that generates a codeword of an first soft-decision value from the first soft-bit information, and generates a codeword of a second soft-decision value from the second soft-bit information; a first decoder that executes hard-decision decoding on a codeword of a hard-decision value configured from the hard-bit information; a second decoder that executes first soft-decision decoding on the codeword of the first soft-decision value; and a third decoder that executes second soft-decision decoding on the codeword of the second soft-decision value, wherein the first soft-bit information includes information having a first number of bits greater than the number of bits of the hard-bit information, and the second soft-bit information includes information having a second number of bits

Abstract: A transmission control apparatus includes a first control board including a first control unit with an input/output port and a first board connector; and a second control board including a second control unit with an input/output port and a second board connector. The first control board is connected to the second control board via a general purpose cable, the general purpose cable is used for transmission of an indication signal as a digital signal controlling a power-supply mode transition and is used for serial communications. Lengths of change periods, during which a logical value of the indication signal is changed and with which transitions among three or more power-supply modes are associated, are preset and stored in the first control unit and the second control unit, respectively. The power-supply mode is transitioned to a specific mode according to the lengths of the change periods of the indication signal.

Abstract: An IC includes a first IC portion and a second IC portion. The IC includes a first set of standard cells in the first IC portion. The IC includes a plurality of memory cells and a second set of standard cells in the second IC portion. The second set of standard cells is located in channels between the memory cells. The IC further includes a plurality of GDHS cells in the first IC portion. The GDHS cells are configured to switch power on and to switch power off to the first set of standard cells. The IC further includes a plurality of CHS cells in the first IC portion. The CHS cells are configured to switch power on and to switch power off to the second set of standard cells in the second IC portion.

Abstract: A wireless communication device (UE) may include a paging subsystem that performs paging-monitoring as part of wireless communications of the wireless communication device. The UE may place wireless communication system resources not required during paging-monitoring into either a low-power state or a power-down state, and those system resources may remain in one of those respective states during paging-monitoring. The wireless communication system resources not required during the paging-monitoring may include at least a wireless communications protocol stack used during the wireless communications of the UE, and at least system resources used for performing uplink related tasks independently of wireless communication system resources used for performing downlink related tasks.

Abstract: One example of layer-by-layer error correction can include iteratively error correcting the codeword on a layer-by-layer basis with the first error correction circuit in a first mode and determining on the layer-by-layer basis whether a number of parity errors in a particular layer is less than a threshold number of parity errors. The codeword can be transferred to a second error correction circuit when the number of parity errors is less than the threshold number of parity errors. The codeword can be iteratively error corrected with the first error correction circuit in a second mode when the number of parity errors is at least the threshold number of parity errors. The threshold number of parity errors can be at least partially based on an adjustable code rate of the first error correction circuit or the second error correction circuit.

Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.