Conservation Of Power Patents (Class 365/227)
  • Patent number: 10776293
    Abstract: An apparatus including a host interface and a registered clock driver interface. The host interface may be configured to receive an enable command from a host. The registered clock driver interface may be configured to perform power management for a dual in-line memory module, generate data for the dual in-line memory module, communicate the data, receive a clock signal and communicate an interrupt signal. The registered clock driver interface may be disabled at power on. The registered clock driver interface may be enabled by in response to the enable command. The apparatus may be implemented as a component on the dual in-line memory module.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: September 15, 2020
    Assignee: Integrated Device Technology, Inc.
    Inventors: Shwetal Arvind Patel, Andy Zhang, Wen Jie Meng, Chenxiao Ren, Alejandro F. Gonzalez
  • Patent number: 10754801
    Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Matthew A. Prather
  • Patent number: 10701635
    Abstract: A wireless communication device (UE) may include a paging subsystem that performs paging-monitoring as part of wireless communications of the wireless communication device. The UE may place wireless communication system resources not required during paging-monitoring into either a low-power state or a power-down state, and those system resources may remain in one of those respective states during paging-monitoring. The wireless communication system resources not required during the paging-monitoring may include at least a wireless communications protocol stack used during the wireless communications of the UE, and at least system resources used for performing uplink related tasks independently of wireless communication system resources used for performing downlink related tasks.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: June 30, 2020
    Assignee: Apple Inc.
    Inventors: Moustafa M. Elsayed, Tarik Tabet
  • Patent number: 10657051
    Abstract: Provided is a memory device including: a memory array, including a flag memory array having a plurality of flag memory cells and a data memory array having a plurality of data memory cells, the corresponding flag memory cells being used to record whether the corresponding data memory cells have been written or not. In initialization, the flag memory array is initialized by the control circuit but the data memory array is not initialized.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: May 19, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Su-Chueh Lo, Chun-Yu Liao
  • Patent number: 10657081
    Abstract: Memory devices and methods for operating the same are provided. A memory device can include at least one command contact and at least one data contact. The memory device can be configured to detect a condition in which the at least one command contact is connected to a controller and the at least one data contact is disconnected from the controller, and to enter, based at least in part on detecting the condition, a first operating mode with a lower nominal power rating than a second operating mode. Memory modules including one or more such memory devices can be provided, and memory systems including controllers and such memory modules can also be provided.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 19, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Matthew A. Prather
  • Patent number: 10613617
    Abstract: A semiconductor apparatus includes a state storage circuit configured to store information depending on a plurality of signals, and output the stored information as a power gating signal. The semiconductor apparatus may include a power gating circuit configured to provide or block a power supply voltage to an internal operation circuit as a driving voltage in response to the power gating signal.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: April 7, 2020
    Assignee: SK hynix Inc.
    Inventor: Sung Soo Chi
  • Patent number: 10614880
    Abstract: A memory system includes: a memory device; a cache memory suitable for caching a portion of a data stored in the memory device; and a read voltage controller suitable for controlling a level of a read voltage of the memory device by comparing a cache data in the cache memory with a data from the memory device corresponding to the cache data.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Sang-Gu Jo, Jung-Hyun Kwon, Sung-Eun Lee, Yong-Ju Kim
  • Patent number: 10579418
    Abstract: The machine implemented method for operating at least one electronic system comprises detecting a pattern of use of plural control parameters in a path through a graph of operational context switches to reach a target operational context; storing a representation of the pattern in association with an indicator identifying the target operational context; responsive to detecting at least one of a request for a switch of operation from a source operational context to the target operational context, a trapping on a resource access, and a detection of a breakpoint, retrieving the representation in accordance with the indicator identifying the target operational context; and responsive to the retrieving, applying at least one control parameter to said at least one electronic system to match the pattern.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: March 3, 2020
    Assignee: ARM IP LIMITED
    Inventors: Milosch Meriac, Alessandro Angelino
  • Patent number: 10579290
    Abstract: An option code providing circuit includes a plurality of resistive random access memory cells and a controller. The controller determines whether to provide a control signal to operate a heavy forming operation on the resistive random access memory cells or not. Wherein, the controller performs a read operation on the resistive random access memory cells to determine a bit number of the resistive random memory cell which is heavy formed, and the option code is determined by the bit number of resistive random access memory cell which is heavy formed or a bit number of the resistive random access memory cell which is not heavy formed.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: March 3, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Johnny Chan, Chi-Shun Lin
  • Patent number: 10552256
    Abstract: A hardware coding mechanism is described. The coding mechanism may include a first encoder to produce a first code using a base number of bits and a second encoder to produce a second code using a supplementary number of bits. The second code and the first code together may be stronger than the first code alone. A mode register stored in a storage may specify whether a switch to the second encoder is open or closed: the first coder is always used.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dimin Niu, Mu-Tien Chang, Hongzhong Zheng
  • Patent number: 10511326
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a soft decision decoding on a codeword, generating a hard decision for each bit of the codeword at an end of the soft decision decoding, generating a hard decision for each bit of the codeword at an end of the soft decision decoding, generating a reliability determination for each hard decision and performing a hard decision decoding using the hard decision for each bit and reliability determination for each hard decision.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: December 17, 2019
    Assignee: Nyquist Semiconductor Limited
    Inventors: Yuan-mao Chang, Jie Chen, Chung-Li Wang
  • Patent number: 10510389
    Abstract: A word line decoder circuit located in a memory storage apparatus is provided. The memory storage apparatus includes a memory cell array. The word line decoder circuit includes a word line decoder and a power supply circuit. The word line decoder is coupled to a plurality of word lines of the memory storage apparatus. The power supply circuit is coupled to the word line decoder. The power supply circuit is configured to provide a first power to the word line decoder in a read mode, and provide a second power to the word line decoder in a standby mode. A voltage value of the first power is greater than or less than that of the second power.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: December 17, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Chung-Zen Chen
  • Patent number: 10474529
    Abstract: An error checking and correcting (ECC) decoding method and apparatus are provided. A decoding circuit decodes a codeword using (or without using) reference information, wherein when the decoding circuit fails to decode a first codeword, the decoding circuit decodes a second codeword to produce decoded data. The decoding circuit checks whether a change has occurred from each codeword bit of the second codeword to a corresponding bit of the decoded data. In accordance with a bit position of the changed corresponding bit, the decoding circuit correspondingly changes the first codeword to a modified codeword, and/or correspondingly changes the reference information to modified information. The decoding circuit performs the ECC decoding again on the modified codeword (or the first codeword) using (or without using) the modified information.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: November 12, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Ching-Yu Chen, Yi-Lin Lai, Chen-Te Chen
  • Patent number: 10437668
    Abstract: According to one embodiment, a memory controller includes: a memory I/F that reads a codeword written in a NAND memory as any one of hard-bit information, first soft-bit information, and second soft-bit information; a codeword processor that generates a codeword of an first soft-decision value from the first soft-bit information, and generates a codeword of a second soft-decision value from the second soft-bit information; a first decoder that executes hard-decision decoding on a codeword of a hard-decision value configured from the hard-bit information; a second decoder that executes first soft-decision decoding on the codeword of the first soft-decision value; and a third decoder that executes second soft-decision decoding on the codeword of the second soft-decision value, wherein the first soft-bit information includes information having a first number of bits greater than the number of bits of the hard-bit information, and the second soft-bit information includes information having a second number of bits
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: October 8, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Yasuhiro Takase
  • Patent number: 10409207
    Abstract: A transmission control apparatus includes a first control board including a first control unit with an input/output port and a first board connector; and a second control board including a second control unit with an input/output port and a second board connector. The first control board is connected to the second control board via a general purpose cable, the general purpose cable is used for transmission of an indication signal as a digital signal controlling a power-supply mode transition and is used for serial communications. Lengths of change periods, during which a logical value of the indication signal is changed and with which transitions among three or more power-supply modes are associated, are preset and stored in the first control unit and the second control unit, respectively. The power-supply mode is transitioned to a specific mode according to the lengths of the change periods of the indication signal.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: September 10, 2019
    Assignee: Ricoh Company, Ltd.
    Inventor: Naoto Ikeda
  • Patent number: 10346574
    Abstract: An IC includes a first IC portion and a second IC portion. The IC includes a first set of standard cells in the first IC portion. The IC includes a plurality of memory cells and a second set of standard cells in the second IC portion. The second set of standard cells is located in channels between the memory cells. The IC further includes a plurality of GDHS cells in the first IC portion. The GDHS cells are configured to switch power on and to switch power off to the first set of standard cells. The IC further includes a plurality of CHS cells in the first IC portion. The CHS cells are configured to switch power on and to switch power off to the second set of standard cells in the second IC portion.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: July 9, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Rajesh Arimilli, Sabyasachi Sarkar, Gaurav Arya
  • Patent number: 10341952
    Abstract: A wireless communication device (UE) may include a paging subsystem that performs paging-monitoring as part of wireless communications of the wireless communication device. The UE may place wireless communication system resources not required during paging-monitoring into either a low-power state or a power-down state, and those system resources may remain in one of those respective states during paging-monitoring. The wireless communication system resources not required during the paging-monitoring may include at least a wireless communications protocol stack used during the wireless communications of the UE, and at least system resources used for performing uplink related tasks independently of wireless communication system resources used for performing downlink related tasks.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: July 2, 2019
    Assignee: Apple Inc.
    Inventors: Moustafa M. Elsayed, Tarik Tabet
  • Patent number: 10326479
    Abstract: One example of layer-by-layer error correction can include iteratively error correcting the codeword on a layer-by-layer basis with the first error correction circuit in a first mode and determining on the layer-by-layer basis whether a number of parity errors in a particular layer is less than a threshold number of parity errors. The codeword can be transferred to a second error correction circuit when the number of parity errors is less than the threshold number of parity errors. The codeword can be iteratively error corrected with the first error correction circuit in a second mode when the number of parity errors is at least the threshold number of parity errors. The threshold number of parity errors can be at least partially based on an adjustable code rate of the first error correction circuit or the second error correction circuit.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: June 18, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mustafa N. Kaynak, Patrick R. Khayat, Sivagnanam Parthasarathy, Nicholas J. Richardson
  • Patent number: 10296065
    Abstract: A system on chip (SoC) includes a plurality of intellectual property (IP) blocks and a clock management unit (CMU) configured to perform clock gating on at least one of the IP blocks. The IP blocks and the CMU interface with one another using a full handshake method. The full handshake method may include at least one of the IP blocks sending a request signal to the CMU to begin providing a clock signal or to stop providing the clock signal, and the CMU sending an acknowledgement signal to the corresponding IP block in response to receipt of the request signal.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: May 21, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Gon Lee, Ah Chan Kim, Jin Ook Song, Jae Young Lee, Youn Sik Choi
  • Patent number: 10272251
    Abstract: A filtering algorithm implemented by a filtering module in an implantable medical device (IMD), or in an external device for communicating with an IMD, is disclosed which reviews blocks based on a number of rules. The filtering module preferably comprises both firewall and instruction analysis modules. The instruction analysis module analyzes the instructions and associated data (if present) in each block to determine whether such blocks would compromise operation of the IPG or injure a patient if executed. Instruction rules corresponding to an instruction identified in the block are retrieved by the instruction analysis module. The instruction analysis module reviews the block per the retrieved rules, and possibly also in light of current and historical IPG therapy setting or mode data, or other received but un-executed blocks. If a block is compliant, it is executed by the IMD or transmitted to the IMD.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: April 30, 2019
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: Sridhar Kothandaraman, Dennis Zottola
  • Patent number: 10225425
    Abstract: The present information processing apparatus includes a plurality of memory modules that can be controlled in a first mode in which power is supplied, and in a second mode in which power consumption is smaller than in the first mode, specifies a memory module to be accessed based on input address information, shifts the specified memory module from the second mode to the first mode, and, upon access to the specified memory module being terminated, shifts the specified memory module from the first mode to the second mode.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: March 5, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shuichi Nakamura
  • Patent number: 10186313
    Abstract: A memory macro includes a first input terminal, a first memory cell array, a second memory cell array, a first input output (IO) circuit, a second IO circuit, a first set of driver circuits, a second set of driver circuits and a logic circuit. The first set of driver circuits are coupled to the first memory cell array and the first IO circuit. The second set of driver circuits are coupled to the second memory cell array and the second IO circuit. The logic circuit has a first terminal coupled to the first input terminal and configured to receive a first signal. The logic circuit is coupled to the first set of driver circuits and the second set of driver circuits. The logic circuit is configured to generate at least a second signal responsive to the first signal causing a change in the operational mode of the memory macro.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: January 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pankaj Aggarwal, Jui-Che Tsai, Ching-Wei Wu
  • Patent number: 10142442
    Abstract: Methods, systems, and computer readable media for enabling a downloadable service to access components in a mobile device are disclosed. According to one aspect, a system comprises a mobile device that includes a mobile wallet application configured to determine at least one hardware component or software component provisioned on the mobile device and to generate a capabilities object containing information identifying the at least one hardware or software component. The system further includes a network server supporting a downloadable service configured to receive the capabilities object from the mobile device, to generate personalized downloadable service content based on the information in the received capabilities object, to provide the personalized web page content to the mobile device, wherein the personalized downloadable service content is configured to access the at least one hardware component or software component on the mobile device.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: November 27, 2018
    Assignee: MASTERCARD INTERNATIONAL INCORPORATED
    Inventors: Dickey B. Singh, Mohammad Khan, Venkata Sastry Akella, Alan Marshall, Sanjay Dalal, Pradeep Kumar
  • Patent number: 10089150
    Abstract: A method of central processor unit (CPU) resource allocation for a multi-processor device includes the step of obtaining the amounts of demanded CPU resources for the process groups executing on the multi-processor device during a pre-configured time period. The method also includes the step of obtaining the amounts of idle CPU resources for the CPUs of the multi-processor device during the pre-configured time period. The method further includes the step of allocating the CPUs to the process groups based upon the obtained amounts of demanded CPU resources for the process groups and the obtained amounts of idle CPU resources for the CPUs.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: October 2, 2018
    Assignee: Alibaba Group Holding Limited
    Inventor: Zhiyuan Zhou
  • Patent number: 9991877
    Abstract: A current break circuit includes a current break control circuit suitable for sequentially outputting a first enable signal and a second enable signal with a time difference in response to at least one control signal, and a current break switch circuit suitable for outputting or blocking a second voltage in response to a first voltage, wherein the current break switch circuit forms a first current path in response to the first enable signal and a second current path in response to the second enable signal when blocking the second voltage.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: June 5, 2018
    Assignee: SK Hynix Inc.
    Inventors: Min Su Kim, Kang Youl Lee
  • Patent number: 9954558
    Abstract: A method for fast decoding, the method may include (a) performing a hard read of a group of flash memory cells to provide hard read data; wherein the group of flash memory cells store a codeword that comprises component codes of multiple dimensions; (b) hard decoding the hard read data to provide a hard decoding result; wherein the hard decoding result comprises first suggested values of component codes of at least one dimension of the multiple dimensions; (c) performing at least one additional read attempt of the group of flash memory cells to provide additional data; (d) performing a partial extensiveness soft decoding the additional data, in response to the first suggested values, to provide a soft decoding result; and (e) wherein the soft decoding result comprises second suggested values of component codes of one or more dimensions of the multiple dimensions.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: April 24, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Avi Steiner, Avigdor Segal, Hanan Weingarten
  • Patent number: 9948179
    Abstract: Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: April 17, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jaydeep P. Kulkarni, Pascal A. Meinerzhagen, Dinesh Somasekhar, James W. Tschanz, Vivek K. De
  • Patent number: 9939863
    Abstract: According to one embodiment, a power control system includes a power controlled unit, a first power controller configured to generate a first control signal that controls the power of the power controlled unit, and a second power controller including a signal holding unit configured to hold the first control signal and to transmit a second control signal including information identical to the information of the first control signal to the power controlled unit, the second power controller being different from the first power controller as hardware.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: April 10, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Sasagawa
  • Patent number: 9881653
    Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 30, 2018
    Assignee: Maxlinear, Inc.
    Inventors: Curtis Ling, Vadim Smolyakov, Timothy Gallagher, Glenn Gulak
  • Patent number: 9830272
    Abstract: An apparatus is described. The apparatus includes a cache memory having two or more memory blocks and a central processing unit (CPU), coupled to the cache memory, to open a first memory block within the cache memory upon exiting from a low power state.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: November 28, 2017
    Assignee: Intel Corporation
    Inventors: Iris Sorani, Larisa Novakovsky, Joseph Nuzman
  • Patent number: 9785221
    Abstract: An image processing apparatus having a plurality of functional units that respectively execute predetermined functions, a method of controlling the apparatus, the apparatus manages a memory with a plurality of areas, and allocates the plurality of areas of the memory to the plurality of functional units respectively. Then, when, in a power saving state, at least one of the plurality of functional units is caused to transition into a power saving state, the apparatus stops a refreshing of the area of the memory allocated to the functional unit that is caused to transition into the power saving state.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: October 10, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Toshiaki Iizuka
  • Patent number: 9749279
    Abstract: The invention provides a system and method for analyzing a collection of communication messages. The communication messages may be any one of a collection of electronic mail messages, voicemail messages, instant messaging dialogs and other forms of communications. The collections of communications, such as electronic mail messages, may be selected by a user and then subsequently processed to determine the identity of any of the user's contacts within the communications. The contacts may then be arranged in a relative priority arrangement whereby contacts which have been identified as engaging in prior reciprocal communications with the user are given higher priority. Higher priority may also be given to contacts which engage in more recent communications with the user. Specific contact relationships may be inferred from the communications depending on whether specific contacts are repeatedly mentioned within the communication messages.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: August 29, 2017
    Assignee: FACEBOOK, INC.
    Inventors: Ellen Isaacs, Bonnie A. Nardi, Stephen Whittaker
  • Patent number: 9734061
    Abstract: A memory control circuit has a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an integer of 1 or more and of n or less, n being an integer of 2 or more) level cache memory among first to n-th level cache memories continues for a first period of time or longer, the i-th level cache memory comprising a first nonvolatile memory, and a power-supply controller to control a power cut-off timing to the i-th level cache memory based on a determination of the request determination circuitry.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: August 15, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kumiko Nomura, Shinobu Fujita, Keiko Abe, Kazutaka Ikegami, Hiroki Noguchi, Susumu Takeda
  • Patent number: 9728241
    Abstract: Non-volatile flip-flops (NVFFs) based circuitries and schemes that incorporate magnetic tunnel junctions (MTJs) are provided to ensure fast data storage and restoration from an intentional or unintentional power outage. The NVFFs based circuitries and schemes also include enhanced scan mode testing capability by exploiting the nonvolatile latch to function as hold latch for delay testing. The NVFFs based circuitries and schemes eliminate additional write drivers, and may operate at an operation frequency of, for example, up to 2 GHz at a supply voltage of 1.1 V and with 0.55 pJ of energy consumption. A near uniform write latency can be achieved through transistor sizing, given write asymmetry of MTJs. NVFFs based circuitries and schemes incorporating data-dependent power gating circuitries can be used to mitigate high static currents generated during retention and back-to-back writing of identical input data.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: August 8, 2017
    Assignee: UNIVERSITY OF SOUTH FLORIDA
    Inventors: Swaroop Ghosh, Anirudh Srikant Iyengar, Jae-Won Jang
  • Patent number: 9690697
    Abstract: According to one embodiment, a memory controller controlling a nonvolatile memory which stores a code word includes a read control unit which controls reading from the nonvolatile memory and a decoding unit which obtains likelihood information of each memory cells based on a reading result from the nonvolatile memory and decodes the code word by using the likelihood information, wherein the decoding unit obtains the likelihood information of a first memory cell based on the reading result of the first memory cell and the reading results of second memory cells which are one or more of the memory cells adjacent to the first memory cell.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: June 27, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenji Sakurada
  • Patent number: 9678896
    Abstract: An asset management system is provided, which includes a hardware module operating as an asset control core. The asset control core generally includes a small hardware core embedded in a target system on chip that establishes a hardware-based point of trust on the silicon die. The asset control core can be used as a root of trust on a consumer device by having features that make it difficult to tamper with. The asset control core is able to generate a unique identifier for one device and participate in the tracking and provisioning of the device through a secure communication channel with an appliance. The appliance generally includes a secure module that caches and distributes provisioning data to one of many agents that connect to the asset control core, e.g. on a manufacturing line or in an after-market programming session.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: June 13, 2017
    Assignee: Certicom Corp.
    Inventors: Daniel Francis O'Loughlin, Keelan Smith, Jay Scott Fuller, William Lundy Lattin, Marinus Struik, Yuri Poeluev, Matthew John Campagna, Thomas Rudolf Stiemerling, Wei Cheng Joseph Ku
  • Patent number: 9647697
    Abstract: Systems, methods, and/or devices are used to improve decoding of data read from a storage device with one or more memory devices. In one aspect, the method includes obtaining, in response to a read request, a codeword with two or more codeword portions from distinct memory portions of the storage device. When a decoding iteration on the codeword fails to satisfy predetermined decoding criteria, the method includes, for the two or more codeword portions of the codeword: determining a bit-flip count between raw read data for a respective codeword portion and a decoding result for the respective codeword portion after the decoding iteration; determining a soft information offset for the respective codeword portion based on the bit-flip count for the respective codeword portion relative to bit-flips counts for other codeword portions; and adjusting soft information for the respective codeword portion based on the soft information offset.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: May 9, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xiaoheng Chen, Jingyu Kang, Jiangli Zhu, Ying Yu Tai
  • Patent number: 9633716
    Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: April 25, 2017
    Assignee: Intel Corporation
    Inventors: Jaydeep P. Kulkarni, Bibiche M. Geuskens, James Tschanz, Vivek K. De, Muhammed M. Khellah
  • Patent number: 9621188
    Abstract: A decoder unit is configured to perform a decoding on encoded data. The decoder unit includes a data bus comprising a number N of data lines, a local memory configured to store messages for a message-passing decoding and communicate the messages across the data bus, a plurality of first decoder processing units, wherein each first decoder processing unit is configured to perform the message-passing decoding by communicating with the local memory using a number A of the data channels, and a plurality of second decoder processing units, where each second decoder processing unit is configured to perform the message-passing decoding by communicating with the local memory using a number B of the data lines. N is at least two, A and B are less than or equal to N, and A is different from B.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: April 11, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eran Hof, Jun Jin Kong
  • Patent number: 9612643
    Abstract: Methods and apparatus relating to controlling processor slew rates based on battery charge state/level are described. In one embodiment, logic causes modification to a slew rate of a processor based on at least a charge level of a battery pack. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 29, 2014
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Alexander B. Uan-Zo-Li, Don J. Nguyen, Gang Ji, Philip R. Lehwalder, Jorge P. Rodriguez, Vasudevan Srinivasan
  • Patent number: 9612761
    Abstract: According to one embodiment, a semiconductor device includes a nonvolatile memory, a volatile memory, and a controller. The controller is configured to transition a part of the volatile memory to a self-refresh mode when a request for stopping supplying of power to the nonvolatile memory is received.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: April 4, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Naoki Kimura
  • Patent number: 9612763
    Abstract: Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface; monitoring a state of the attached memory; determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold; and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: April 4, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: Krishanth Skandakumaran, Arun Kumar Medapati, Sri Rama Namala, Ashwin Narasimha, Ajith Kumar B
  • Patent number: 9607671
    Abstract: Integrated circuits may include partial reconfiguration (PR) circuitry for reconfiguring only a portion of a memory array. In some applications, partial reconfiguration may be performed during user mode. During partial reconfiguration, write assist techniques such as varying the power supply voltage may be applied to help increase write margin, but doing so can potentially affect the performance of in-operation pass gates that are being controlled by the memory array during user mode. In one suitable arrangement, ground power supply voltage write assist techniques may be implemented on memory cells that include p-channel access transistors and that are used to control n-channel pass transistors. In another suitable arrangement, positive power supply voltage write assist techniques may be implemented on memory cells that include n-channel access transistors and that are used to control p-channel pass transistors.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: March 28, 2017
    Assignee: Altera Corporation
    Inventors: Andy L. Lee, Shankar Sinha, Ning Cheng
  • Patent number: 9568980
    Abstract: The disclosed embodiments relate to a system that supports dynamic bursts to facilitate frequency-agile communication between a memory controller and a memory device. During operation, the system monitors a reference clock signal received at an interface between the memory device and the memory controller. Upon detecting a frequency change in the reference clock signal from a fullrate to a subrate, the interface operates in a burst mode, wherein data is communicated through bursts separated by intervening low-power intervals during which portions of the interface are powered down.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 14, 2017
    Assignee: RAMBUS INC.
    Inventors: Jared L. Zerbe, Brian Hing-Kit Tsang, Barry William Daly
  • Patent number: 9564208
    Abstract: The invention concerns a memory cell having: first and second cross-coupled gated inverters (102, 104), each including first and second inputs (IN1, IN2) and an output (OUT) and being adapted to couple its output to a first logic level only when the first and second inputs both receive the inverse of the first logic level; a first cut-off circuit (106) coupling the second input (IN2) of the first gated inverter (102) to the first input (IN1) of the first gated inverter (102); and a second cut-off circuit (108) coupling the second input (IN2) of the second gated inverter (104) to the first input (IN1) of the second gated inverter (104).
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: February 7, 2017
    Assignee: Dolphin Integration
    Inventors: Oron Chertkow, Ariel Pescovsky
  • Patent number: 9519330
    Abstract: A multicore computer architecture provides for clock dividers on each core, the clock dividers capable of providing rapid changes in the clock frequency of the core. The clock dividers are used to reduce the clock frequency of individual cores spinning while waiting for a synchronization instruction resolution such as a lock variable. Core power demands may be decreased before and after change in dock speed to reduce power bus disruption.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: December 13, 2016
    Assignee: Wisconsin Alumni Research Foundation
    Inventor: Nam-Sung Kim
  • Patent number: 9514837
    Abstract: A memory is released for use without pre-verification of its memory blocks as being defect free. Some memory blocks are subjected to a verification process when the computer memory is in use in order to verify a minimum number of memory blocks required for high performance program operation as being defect free. The verification process continues as the computer memory is in use in order to maintain the minimum number of memory blocks required for high performance operation in the verified defect free state. A verification mode of either no verification, delayed verification, or immediate verification is applied to memory blocks used for regular performance program operation. Delayed verification is maintained until an ability to recover the stored data is going to be lost. Immediate verification can be performed using bit error rate analysis. Some verification processes are performed using aggressive programming trim and/or multiple word line sensing for faster programming.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: December 6, 2016
    Assignee: SanDisk Technologies LLC
    Inventors: Ofer Shapira, Eran Sharon, Idan Alrod
  • Patent number: 9471490
    Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: October 18, 2016
    Assignee: Intel Corporation
    Inventors: Avinash N. Ananthakrishnan, Efraim Rotem, Eliezer Weissmann, Doron Rajwan, Nadav Shulman, Alon Naveh, Hisham Abu-Salah
  • Patent number: 9443600
    Abstract: A method and apparatus that controls a peak-current condition in a multi-die memory, such as a solid-state drive, by determining by at least one die of the multi-die memory whether a subsequent memory operation is a high-current memory operation, such as an operation to enable a charge pump of the die, an operation to charge a bit line of the die, or a program/erase loop operation, or a combination thereof. The die enters a suspended-operation mode if the subsequent memory operation is determined to be a high current memory operation. Operation is resumed by the die in response to a resume operation event, such as, but not limited to, a command specifically address to the die, an indication from another die that a high-current memory operation is complete. Once operation is resumed, the die performs the high-current memory operation.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: September 13, 2016
    Assignee: Intel Corporation
    Inventors: Ali Ghalam, Dean Nobunaga, Jason Guo
  • Patent number: 9400544
    Abstract: Methods and apparatuses for reducing leakage power in a system cache within a memory controller. The system cache is divided into multiple sections, and each section is supplied with power from one of two supply voltages. When a section is not being accessed, the voltage supplied to the section is reduced to a voltage sufficient for retention of data but not for access. The cache utilizes a maximum allowed active section policy to limit the number of sections that are active at any given time to reduce leakage power. Each section includes a corresponding idle timer and break-even timer. The idle timer keeps track of how long the section has been idle and the break-even timer is used to periodically wake the section up from retention mode to check if there is a pending request that targets the section.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: July 26, 2016
    Assignee: Apple Inc.
    Inventors: Wolfgang H. Klingauf, Rong Zhang Hu, Sukalpa Biswas, Shinye Shiu