Abstract: According to an embodiment, a semiconductor integrated circuit includes a regulator, a level shifter and a switch circuit. The regulator converts an input voltage that is a difference in potential between a first terminal and a third terminal into an output voltage that is a difference in potential between a second terminal and the third terminal. The level shifter adjusts a voltage level between a first terminal and a second terminal. The switch circuit includes a first switch selectively connecting the third terminal of the regulator to a first potential, a second switch selectively connecting the third terminal of the regulator to the first terminal of the level shifter, and a third switch selectively connecting the third terminal of the regulator to a second potential.

Abstract: A content search system including a CAM device having a plurality of CAM blocks and a governor logic receives a search request and compares the number of CAM blocks required to perform the requested search to a limit number, the limit number being the maximum number of CAM blocks permitted to be used in a requested search operation. If the number of CAM blocks required to perform the requested search exceeds the maximum number of CAM blocks permitted to be used in a requested search operation, then the search operation is rejected. The governing operation can be performed on each requested search, thus limiting power dissipation. The relationship between a maximum number of CAM blocks and power dissipation can be characterized, and a corresponding block limit value can be stored into a memory accessible by governor logic.

Abstract: A semiconductor memory device includes a memory cell array, a voltage generator suitable for generating voltages used for controlling the memory cell array in response to a power-saving signal, and a control logic suitable for providing a power-saving signal to the voltage generator, based on a chip select signal. The control logic includes a delay block suitable for delaying the chip select signal and generating the power-saving signal based on the delayed chip select signal.

Abstract: In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached.

Abstract: Implementations of the present disclosure involve a circuit and/or method for providing a static random access memory (SRAM) component of a very large scale integration (VLSI) design, such as a microprocessor design. In particular, the present disclosure provides for an SRAM circuit that includes a step voltage regulator coupled to the SRAM circuit and designed to maintain a fixed-value voltage drop across the regulator rather than a fixed voltage across the load of the SRAM circuit. The fixed-value drop across the regulator allows the SRAM circuit to be operated at a low retention voltage to reduce leakage of the SRAM circuit while maintaining the parasitic decoupling capacitance across the power supply from the SRAM circuit to reduce power signal fluctuations. In addition, the regulator circuit coupled to the SRAM circuit may include a switch circuit to control the various states of the SRAM circuit.

Abstract: A memory system includes first to third memory devices each having an input terminal for receiving a token signal and an output terminal for transmitting the token signal, wherein the input terminal of each of the first to third memory devices are connected to the output terminal of another memory device through a ring topology, a subset of the first to third memory devices substantially simultaneously perform an operation of consuming a peak current in response to any one of a plurality of token signals, and each of the first to third memory devices possesses only any one of the plurality of token signals and transmits the other token signals to another memory device.

Abstract: A memory module includes volatile memory and non-volatile memory. The module includes logic to check if a non-volatile memory comprises un-erased areas, and if the non-volatile memory comprises un-erased areas, to elevate a backup capacitor potential above a predetermined operating potential sufficient to power a backup of a volatile memory to the non-volatile memory. The module includes logic to ERASE the un-erased areas and to return the capacitor to the predetermined operating potential after the ERASE is complete.

Abstract: A host device includes a voltage source which is connected to a voltage line via a host voltage switch and which supplies a first voltage to the voltage line, a host regulator which is connected to the voltage line and which outputs the first voltage or a second voltage that is lower than the first voltage, a host IO driver for driving a data line with the output of the host regulator as a power source, a host voltage detection circuit for detecting whether the voltage of the data line is the second voltage or a voltage that is higher than the second voltage, and a host control unit for detecting a mismatch of interface voltages between the host device and a memory card based on the output voltage of the host regulator and the detection result of the host voltage detection circuit.

Abstract: A method for storing data. The method includes providing an addressable memory including a memory space, wherein the memory space includes a plurality of memory cells. The method includes configuring the addressable memory such that a majority of the plurality of memory cells in the memory space stores internal data values in a preferred bias condition when a first external data state of one or more external data states is written to the memory space, wherein the first external data state is opposite the preferred bias condition.

Abstract: A flash memory device. In one embodiment, the flash memory device includes a flash memory, a diode, a controller, and a capacitor. The flash memory has a voltage source pin. The diode is coupled between a voltage source and the voltage source pin of the flash memory. The controller is coupled to the flash memory via a data bus. The capacitor is coupled between the voltage source pin of the flash memory and a ground, and supplies power to the flash memory to enable the flash memory to complete writing of at least one data page when the level of the voltage source is lowered.

Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.

Abstract: To provide a semiconductor device including a plurality of circuit blocks each of which is capable of performing power gating by setting off periods appropriate to temperatures of the respective circuit blocks. Specifically, the semiconductor device includes an arithmetic circuit, a memory circuit configured to hold data obtained by the arithmetic circuit, a power supply control switch configured to control supply of the power supply voltage to the arithmetic circuit, a temperature detection circuit configured to detect the temperature of the memory circuit and to estimate overhead from the temperature, and a controller configured to set a period during which supply of the power supply voltage is stopped in the case where a power consumption of the arithmetic circuit during the period is larger than the overhead period and to control the power supply control switch.

Abstract: In a semiconductor device including a row-based control circuit applied with a current reduction circuit having a standby state and an active state, a refresh control circuit generates a refresh request signal every predetermined time interval on a self-refresh mode and time-sequentially generates an internal active signal at N times in connection with the refresh request signal once. The row-based control circuit time-sequentially refreshes information of memory cells on the based of the internal active signal at the N times. The refresh control circuit inactivates the row-based control circuit by making the current reduction circuit the standby state.

Abstract: A non-volatile semiconductor memory device that can reduce power consumption includes plural memory banks containing nonvolatile plural memory cells. A common data bus is shared by plural memory banks and transmits the data of the memory cells. The plural switches are provided respectively between the electric source and plural memory banks. A controller controls the plural switches. The controller, in the data reading-out action or the data writing-in action, makes at least one of the switches corresponding to at least one of the memory banks accessible in a conduction state, and other switches in a non-conduction state.

Abstract: A page copy operation such as copy back programming is performed between a source page of the memory array and a destination page of the memory array in different segments. The segments divide the columns of the main array and the set of redundant columns of the redundant array into, for example, sets of rows. The copy back programming transfers data from a part of the source page in the redundant array to a part of the destination page in the main array, and transfers data from a part of the source page in the main array to a part of the destination page in the redundant array.

Abstract: In accordance with an embodiment of the disclosure, systems and methods are provided for reducing an amount of peak power consumption in a device. In certain implementations, a first signal and a second signal are received, wherein the first signal and the second signal are indicative of amounts of power consumption in a device. The first signal is combined with the second signal to generate a combined signal, and at least a portion of the second signal is shifted in time to cause a combination of the first signal and the shifted portion to have a peak amplitude less than a peak amplitude of the combined signal.

Abstract: A data processing apparatus may include: a data conversion unit configured to designate one-transfer data as one transfer unit and designate a predetermined number of transfer units as one conversion unit when a plurality of input data sequentially input is converted into transfer data of which the number of bits is the same as that of a data bus having a predetermined number of bits, and the transfer data is sequentially transferred, and arrange the input data in the transfer data within the conversion unit. The data conversion unit may include: a data generation unit, a first data arrangement change unit, and a first data selection unit configured to sequentially select the changed data in which the position of the input data is changed by the first data arrangement change unit and output the selected changed data as the transfer data in the data conversion unit.

Abstract: In an embodiment of the invention, a method is provided for isolating a ferroelectric memory from a power supply during a write-back cycle or a write cycle of the ferroelectric memory. After it is determined that a write-back cycle or a write cycle will occur in the ferroelectric memory, the power supply is electrically disconnected from the ferroelectric memory before a write-back cycle or a write cycle occurs. Energy during the write-back cycle or the write cycle is provided to the ferroelectric memory by one or more capacitors in this embodiment. After the write-back cycle or the write cycle has ended, the power supply is electrically connected to the ferroelectric memory and the capacitors.

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Abstract: Semiconductor devices comprising at least one voltage sensor for sensing an operating voltage associated with an operational circuit of the semiconductor device. The at least one voltage sensor is configured to generate a signal indicative of a state of the operating voltage. Methods of monitoring a voltage in a semiconductor device include determining a magnitude of an operating voltage for an operational circuit in a semiconductor device. A signal may be generated indicating a state of the operating voltage.

Abstract: Embodiments are described for a method for regulating sleep mode of a plurality of sub-banks in an SRAM array by isolating all of the sub-banks from a regulator upon access to at least one sub-bank that causes the accessed sub-bank to go to an operating voltage, and isolating the accessed sub-bank from non accessed sub-banks, while maintaining a sleep voltage on a load memory array and each of the sub-banks through the regulator; comparing a voltage on the non accessed sub-banks to a voltage output of the regulator; and providing a sleep voltage level to all of the sub-banks through the regulator when the voltage on the non accessed sub-banks is less than the sleep voltage.

Abstract: An OOB sequence monitoring unit detects that an OOB sequence carried out between a base device as a superior device and a connection I/F which operates even if an extension device is in a standby state has proceeded to a given stage. Based on the detection by the OOB sequence monitoring unit, a power supply control unit instructs a starting power supply unit to supply power. When the extension device starts, the OOB sequence is carried out between the extension device and the connection I/F of another extension device in the same manner. As a result, extension devices are started in decreasing order from the extension device closest to the superior device.

Abstract: A memory device comprises one or more power gates and state signaling circuitry. Each of the one or more power gates is configurable such that a respective portion of the memory device is powered down. The state signaling circuitry is operative to produce a power state output signal indicative of when the one or more power gates are configured such that the memory device is fully powered up.

Abstract: A memory has a normal mode and a power saving mode. The memory has bitline precharge circuitry which during the normal mode selectively couples a pair of bitlines to a precharge node to charge the bitlines to a given voltage level. During the power saving mode the bitlines are isolated from the precharge node. Voltage control circuitry is provided to maintain the precharge node at a first voltage level during the normal mode and at a second voltage level less than the first voltage level during the power saving mode. By reducing the voltage level at the precharge node during the power saving mode, the amount of inrush current occurring when switching from power saving mode to normal mode can be reduced, and this enables the wakeup time to be reduced when returning from power saving mode to normal mode.

Abstract: Systems and methods for early warnings of power loss in solid state storage drives are disclosed. Early warnings of power loss can be used to power the drive to force the drive into a low power states before the energy in backup power sources, such as backup capacitors, is used. The low power states can allow for the reduction of power use by the drive which can provide cost savings and reduction in the risk that the drive will be rendered reconfigurable by a power failure event.

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Abstract: A system for managing redundancy in a memory device includes memory arrays and associated periphery logic circuits, and redundant memory arrays and associated redundant periphery logic circuits. The memory arrays and a first set of logic circuits associated with the periphery logic circuits corresponding to the memory arrays are connected to the power supply by way of memory I/O switches. The redundant memory arrays and associated redundant periphery logic circuits are connected to the power supply by way of redundant I/O switches. The memory and redundant I/O switches are switched on/off based on an acknowledgement signal generated during a built-in-self-test (BIST) operation of the memory device.

Abstract: Embodiments of an apparatus and method to improve power delivery including a pre-charge circuit that may include a first voltage supply rail configured to provide a first voltage amount to perform a first phase of a pre-charge of a bit line and a second voltage supply rail configured to provide a second voltage amount to perform a second phase of the pre-charge of the bit line are described herein. In embodiments, the pre-charge circuit may be a pre charge circuit for a static random-access memory (SRAM) memory cell.

Abstract: A memory has a normal mode and a power saving mode. The memory has bitline precharge circuitry which during the normal mode selectively couples a pair of bitlines to a precharge node to charge the bitlines to a given voltage level. During the power saving mode the bitlines are isolated from the precharge node. Voltage control circuitry is provided to maintain the precharge node at a first voltage level during the normal mode and at a second voltage level less than the first voltage level during the power saving mode. By reducing the voltage level at the precharge node during the power saving mode, the amount of inrush current occurring when switching from power saving mode to normal mode can be reduced, and this enables the wakeup time to be reduced when returning from power saving mode to normal mode.

Abstract: In a nonvolatile memory array, power is provided to groups of memory dies by power management circuits that have different power modes. While one power management circuit is in a high-power mode supplying power for power-hungry memory operations, another power management circuit is in a low-power mode so that overall power usage is balanced.

Abstract: To realize an optimal power-on reset in a system in which the rise of the power supply voltage is sharp. A semiconductor device according to the present invention includes two diodes connected in parallel between power supplies, and a resistor circuit and a capacitance element connected in parallel between one power supply and each of the two diodes, and outputs a comparison result between voltages outputted from the two resistor circuits as a reset signal.

Abstract: A power management method includes receiving a first command with first address indicating a first high power operation that is immediately executed in a first memory die, after receipt of the first command, receiving a second command with a second address indicating a second high power operation, such that an immediate execution of the second high power operation would overlap the first high power operation, and delaying execution of second high power operation through a first waiting period that ends upon completion of the first high power operation, while applying a reference voltage to a second word line of the second memory die indicated by the second address.

Abstract: A supply voltage distribution system for distributing a supply voltage through a semiconductor device, the supply voltage distribution system comprising: a first supply voltage distribution line arrangement and a second supply voltage distribution line arrangement, said first supply voltage distribution line arrangement and said second supply voltage distribution line arrangement being adapted to receive from outside the semiconductor device a semiconductor device supply voltage and to distribute a supply voltage to respective first and second portions of the semiconductor device; and a voltage-to-voltage conversion circuit connected to the first supply voltage distribution line arrangement, wherein the voltage-to-voltage conversion circuit is adapted to either transfer onto the first supply voltage distribution line arrangement the semiconductor device supply voltage received from outside the semiconductor device, or to put on the first supply voltage distribution line a converted supply voltage having a

Abstract: A method of controlling a power mode of a memory device is provided, which includes providing a power mode control signal responsive to a control signal and frequency information. The control signal is provided by a processing device operatively coupled to the memory device. The frequency information is associated with a clock signal used to operate the processing device, and the power mode control signal is operative to control the power mode. The control signal includes a chip select (CS) signal and/or a wait-for-interrupt (WFI) signal, and the power mode includes a light sleep (LS) mode and/or a deep sleep (DS) mode. The frequency information represents a low frequency range, medium frequency range, and/or high frequency range. A corresponding computer-readable medium, power management controller, and electronic system are also disclosed.

Abstract: A semiconductor device includes a global bit line and a local bit line, and a switch coupled therebetween. Upon performing a precharge operation, a precharge voltage is supplied to the global bit line with turning the switch ON, so that the local bit line receives the precharge voltage through the global bit line and the switch, and after a lapse of a predetermined time, a precharge voltage is further supplied to the local bit line without an intervention of the global bit line and the switch.

Abstract: A programmable crossbar array with inline fuses includes a layer of row lines and a layer of column lines with the row lines crossing over the column lines to form junctions and resistive memory elements sandwiched between row lines and a column lines at the junctions. Inline fuses are located in either the row lines, column lines or both. The inline fuses are interposed between the support circuitry and the resistive memory elements. A method for mitigating shorts in a crossbar array is also provided.

Abstract: According to an embodiment, a semiconductor integrated circuit includes a regulator, a level shifter and a switch circuit. The regulator converts an input voltage that is a difference in potential between a first terminal and a third terminal into an output voltage that is a difference in potential between a second terminal and the third terminal. The level shifter adjusts a voltage level between a first terminal and a second terminal. The switch circuit includes a first switch selectively connecting the third terminal of the regulator to a first potential, a second switch selectively connecting the third terminal of the regulator to the first terminal of the level shifter, and a third switch selectively connecting the third terminal of the regulator to a second potential.

Abstract: A semiconductor memory device of this embodiment comprises: a plurality of memory chips each including a plurality of memory cells; and a controller that controls the plurality of memory chips. The controller transmits to any of the plurality of memory chips a drive instruction command instructing an operation. The drive instruction command is transmitted sequentially to the plurality of memory chips with at least a first time interval. Each of the plurality of memory chips, when the memory chip itself is in a standby state of waiting for an instruction for one operation execution of an operation loop for a certain operation, starts the operation of the operation loop in response to the drive instruction command, while when the memory chip itself is in operation execution of the operation loop, ignores the drive instruction command.

Abstract: An image processing apparatus includes a memory provided with a first memory area and a second memory area, and a processor that stores program related data in the first memory area and image related data in the second memory area, separately. When the image processing apparatus is in an energy save mode, the processor shuts down electric power supply to the second memory area storing the image related data.

Abstract: A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

Abstract: A controlling method of a connector, the connector, and a memory storage device are provided. The controlling method includes following steps. A first clock signal generated by a first oscillator in the connector is obtained. A second clock signal generated by a second oscillator in the connector is obtained. A frequency shift of the first oscillator is smaller than a frequency shift of the second oscillator. A detection window information corresponding to the second clock signal is corrected according to the first clock signal and the second clock signal. The first oscillator is turned off. A signal stream including a first signal is received. A detection window is generated according to the corrected detection window information and the second clock signal, and whether the first signal is a burst signal is determined according to the detection window. Thereby, the power consumption of the connector is reduced.

Abstract: Semiconductor modules are provided. The semiconductor module includes semiconductor chips with one or more ranks. The semiconductor module includes a mode register configured for storing a first information signal whose logic level is set or determined according to a number of the ranks and an on-die termination (ODT) controller configured for generating an internal control signal for activating an ODT circuit in response to the first information signal. The internal control signal is enabled during a read operation or disabled during a write operation.

Abstract: A controlling method for a memory storage device is provided. The method includes: disposing a rewriteable non-volatile memory module which is operated at a first working voltage in the memory storage device; and detecting whether the first working voltage is lower than a first voltage threshold. The method also includes: detecting whether a circuit component working voltage is lower than a circuit component voltage threshold; when the first working voltage is lower than the first voltage threshold, setting the memory storage device to stop executing commands from a host system and to stop giving commands to the rewriteable non-volatile memory module; and, when the circuit component working voltage is lower than the circuit component voltage threshold, enabling a reset signal to stop receiving and executing commands from the host system. Therefore, the method can effectively improve the stability of the memory storage device.

Abstract: Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node.

Abstract: Embodiments of the invention are generally directed to interfacing between integrated circuits with asymmetric voltage swing. An embodiment of an apparatus includes a first integrated circuit including a first transmitter and a first receiver; a second integrated circuit including a second transmitter and a second receiver; and an interface including communication channel linking the first transmitter with the second receiver and the first receiver with the second transmitter, wherein the communication channel is one of a single channel or a dual channel. The first transmitter is operable to transmit a first signal and the second transmitter is operable to transmit a second signal, a first average voltage swing of the first signal being asymmetric with a second average voltage swing of the second signal.

Abstract: A method for operating a memory module device. The method can include transferring a chip select, command, and address information from a host memory controller. The host memory controller can be coupled to a memory interface device, which can be coupled to a memory module. The memory module can comprise a plurality of memory devices. The chip select, command and address information can be received at the memory interface using a command-and-address-latency (CAL) mode. Control logic can be used to initiate a power state transition from a first power state to a second power state of an input termination circuit in the memory interface device.

Abstract: A storage device according to an embodiment includes first and second non-volatile semiconductor memories. In addition, the storage device includes first controller that controls the first non-volatile memory to cause the first non-volatile memory to perform processes. In addition, the storage device includes second controller that controls the second non-volatile memory to cause the second non-volatile memory to perform processes. The storage device further includes a signal line which is connected to the first controller and the second controller and through which a token is transmitted between the first controller and the second controller. The first controller is capable of controlling the first non-volatile memory while holding the token and the second controller is capable of controlling the second non-volatile memory while holding the token.

Abstract: Power management of an embedded dynamic random access memory (eDRAM) by receiving an eDRAM power state transition event and determining both the current power state of the eDRAM and the next power state of the eDRAM from the power states of: a power-on state, a power-off state, and a self-refresh state. Using the current power state and the next power state to determine whether a power state transition is required, and, in the case that a power state transition is required, transition the eDRAM to the next power state. Power management is achieved because transitioning to a power-off state or self-refresh state reduces the amount of power consumed by the eDRAM as compared to the power-on state.

Abstract: A flash memory device. In one embodiment, the flash memory device comprises a flash memory, a diode, a controller, and a capacitor. The flash memory has a voltage source pin. The diode is coupled between a voltage source and the voltage source pin of the flash memory. The controller is coupled to the flash memory via a data bus. The capacitor is coupled between the voltage source pin of the flash memory and a ground, and supplies power to the flash memory to enable the flash memory to complete writing of at least one data page when the level of the voltage source is lowered.

Abstract: Various embodiments may generally be directed to a variable resistance data storage device and a method of managing the device. A data storage device may have at least a controller configured to re-characterize at least one variable resistance memory cell in response to an identified variance from a predetermined resistance threshold.