Abstract: A leakage current control circuit with a single low voltage power supply is provided. The circuit includes a first power supply line, a second power supply line, a ground line, a high voltage generating circuit, a power transistor and a control circuit. The high voltage generating circuit generates a voltage in response to an internal sleep signal. The gate electrode of the power transistor is connected to the output of the high-voltage generating circuit such that the power transistor is controlled by the high voltage generating circuit. When the power transistor turns on, the circuit is in operation mode; when the power transistor is off, the circuit is in sleep mode. The control circuit connects to the first power line, the second power line, and the ground line to output the internal sleep signal in response to the sleep signal.

Abstract: The present invention relates to a column decoder for low power consumption in a semiconductor memory apparatus. The semiconductor device according to the present invention includes a column select signal decoder, which has a driving voltage input node and uses a driving voltage, for producing a plurality of column select signals by decoding a column select control signal; and a driving voltage supply controller for controlling a supply of the driving voltage to the driving voltage input node.

Abstract: A memory circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Configurations of the plurality of memory cells are determined depending on the data (“high” or “low”) which is stored in the memory cells. Data array such as a program stored in the memory circuit is analyzed in advance. In the case where “high” is the majority data, memory cells storing “high” are formed with vacant cells in which a semiconductor element is not formed.

Abstract: A SRAM memory with a read assist circuit is presented. The read assist circuit uses bitline voltage level switches, which are connected to a low power supply and a high power supply. The bitline voltage level switches have a write operation state, a read operation state, and a standby operation state. The write operation state selectively provides the high power supply to bitlines in columns selected for a write operation, and provides the low power supply to bitlines in the remaining columns. The read operation state selectively provides the low power supply to bitlines in columns selected for the read operation, and provides the low power supply to bitlines in the other columns. The standby operation state selectively provides the low power supply to bitlines in all columns when not in the read operation state or the write operation state.

Abstract: The present invention provides a solution to avoid the robustness problems of sub-threshold circuits by switching small parts of circuits to nominal-voltage only when they are being used, and switching them back to sub-threshold levels when the operation finishes. Such “hybrid sub-threshold” approach is capable of supporting ultra-low power operation without the disadvantages of sub-threshold circuits.

Abstract: A semiconductor integrated circuit able to operate by different power supply voltages resulting from fluctuations in production, provided with a process monitor circuit for obtaining a grasp of a delay characteristic corresponding to the conditions of a production process, a memory circuit for storing data concerning an extent of process variation acquired by the process monitor circuit, and a power supply voltage control circuit for adaptively controlling the power supply voltage in accordance with the extent of process variation acquired by the process monitor circuit and stored in the memory circuit, and a test method for guaranteeing the operation of the semiconductor integrated circuit.

Abstract: Disclosed herein is a semiconductor memory device which prevents the voltage of a select bit line from being reduced due to the action of coupling capacitance between the select bit line and a non-select bit line, reduces current consumption, and enables high speed reading of bit lines. The semiconductor memory device includes a plurality of memory banks, a plurality of second bit lines, a plurality of selector circuits, a voltage supply circuit. Each of the memory banks includes a plurality of first bit lines, a plurality of word lines, and a plurality of memory banks which are installed between the first bit lines and the word lines. The voltage supply circuit holds non-select bit lines of the first bit lines at the GND level at all times.

Abstract: According to one embodiment of the invention, an activity detector comprises a resource partitioned into a plurality of chunks, a power controller and an activity detection unit. In communication with the activity detector and the resource, the power controller, based on measured activity by the activity detector, activates an additional chunk of the plurality of chunks and assigned the additional chunk to a specified agent or deactivates at least one chunk of the plurality of chunks.

Abstract: A plurality of memory macros, to which first power is supplied, and a logic circuit block, to which second power is supplied, are provided. The memory macros are collectively disposed as a memory block on a semiconductor chip, and memory power wires for supplying the first power to the memory macros that form the memory block are provided over the memory block.

Abstract: A power control circuit and related method providing power to an output terminal supplying a logic block within a semiconductor integrated circuit are disclosed. The power control circuit includes a power gating circuit providing a main power voltage to the output terminal during a normal operating mode and providing a retention voltage to the output terminal during a data retention mode characterized by the absence of the main power voltage from the logic block, wherein the retention voltage is minimally sufficient to retain data stored in the logic block during the data retention mode.

Abstract: A memory includes multiple interface ports. The memory also includes at least two sub-arrays each having an instance of all of the bit lines of the memory and a portion of the word lines of the memory. The memory has a common decoder coupled to the sub-arrays and configured to control each of the word lines. The memory also includes multiplexers coupled to each of the interface ports. The multiplexers are configured to cause the selection of one of the sub-arrays based upon an address of a memory cell received at one or more of the interface ports.

Abstract: A controller of a memory system is configured to reduce power requirements during memory backup transition. When transitioning to backup mode, the memory system controller performs a number of power saving techniques. The controller may change a number of configuration settings in the volatile memory system, such as reducing output driver strength, increasing differential impedance, increasing on-die termination, disabling receiver input circuitry, and disconnecting the termination voltage network. The controller may also assert a hard reset to the storage controller system to significantly reduce the load and allow the voltage regulator to continue to provide power to the memory system for a longer period of time.

Abstract: A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Abstract: A semiconductor integrated circuit device comprises: a circuit block, a first MOS transistor, a first power line, a second power line, a third power line, and a drive circuit. The first MOS transistor is connected between the first and second power lines. The circuit block is connected between the second and third power lines. The drive circuit controls a voltage supplied to a gate of the first MOS transistor. The first MOS transistor is off in a standby state and on in an operation state. During a shift from the standby state to the operation state and a shift from the operation state to the standby state, the drive circuit changes the voltage supplied to the gate of the first MOS transistor at a first rate, and then, changes the voltage supplied to the gate of the first MOS transistor at a second rate faster than the first rate.

Abstract: In one embodiment, an electronic device comprises control circuitry. The control circuitry disables termination circuitry coupled to one or more input/output (I/O) signals of the electronic device during at least a portion of a relatively low frequency operation which causes insubstantial signal reflections at the I/O signals. The control circuitry re-enables the termination circuitry prior to the electronic device performing a relatively high frequency operation after completion of the low frequency operation, the high frequency operation causing substantial signal reflections at the I/O signals. The electronic device is a memory device in one embodiment. This way, the termination circuitry may be disabled during at least a portion of a refresh operation performed by the memory device and re-enabled prior to the memory device resuming normal operation (i.e., reads and writes) after completion of the refresh operation.

Abstract: A semiconductor memory device includes a DRAM memory core circuit including a word line, a power supply circuit configured to operate in a selected one of a first state and a second state to generate a predetermined power supply voltage for provision to the DRAM memory core circuit, the power supply circuit consuming a larger electric current in the first state than in the second state, and a control circuit configured to control the power supply circuit such that the power supply circuit is shifted from the first state to the second state, and is then brought back to the first state during a period from activation of the word line to deactivation of the word line.

Abstract: A semiconductor device of this invention includes a first circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, a second circuit for controlling the output from the first circuit by activation or deactivation, and an activation control circuit for activating or deactivating the second circuit in accordance with external input.

Abstract: The present disclosure provides a dual-mode voltage controller, a method of supplying voltage to SRAM periphery circuits and an integrated circuit. In one embodiment, the dual-mode voltage controller is for use with an SRAM array and includes a voltage switching unit connected to a digital core voltage and an SRAM array voltage to form a structure capable of switching at least one SRAM periphery circuit between the digital core voltage and the SRAM array voltage.

Abstract: A semiconductor memory device that enables the reduction of the circuit scale of the antifuse write voltage generation circuit. The semiconductor memory device has a first internal power supply generation circuit that boosts an external power supply voltage to generate a first internal power supply, a memory core to which the first internal power supply is supplied, an antifuse memory for writing predetermined information, and also a write voltage generation circuit that boosts the first internal power supply to generate an antifuse write voltage.

Abstract: A semiconductor memory device (104) selectably connectable to an external high voltage power supply (122) is provided. The semiconductor memory device (104) includes a switch (314), a detector (316) and a timing device (318). The switch (314) is connected to external voltage supply signals and selectably couples the external voltage supply signals to memory cells (305) of the semiconductor memory device (104) for memory operations thereof. The external voltage supply signals including a high voltage signal (412) provided from the external high voltage power supply (122) and an operational voltage signal Vcc (402). The detector (316) is connected to the external voltage supply signals for generating a timer activation signal (404) in response to detecting an operational voltage power-on period.

Abstract: A power state management method of north bridge. The north bridge monitors power transition state of processor; then adjusting operating clocks and operating voltage of the processor and the main memory according to the determined power state to saving power consumption.

Abstract: A structure and method to reduce leakage of a Static Random Access Memory (SRAM) array, wherein the array is subdivided into a set of sub-arrays, whose supply voltages can be controlled independently using a single voltage regulation circuit dedicated to the entire SRAM array. A switch fabric enables independent switching of individual sub-arrays between a virtual ground level and a system ground level based on whether the sub-array is operating in power saving mode or a high performance mode to reduce leakage current when a sub-array is configured in a power saving mode.

Abstract: An integrated circuit includes a supply voltage controller operable to receive a plurality of control signals and at least one circuit supply voltage and to output at least one variable supply voltage to at least one supply terminal of the integrated circuit The controller is operable to switch the variable supply voltage to a first voltage level when the control signals define a first operation and to a second voltage level different from the first voltage level when the control signals define a second operation. The controller is also operable to float the variable supply voltage to a third voltage level different from the first voltage level when the control signals define a third operation.

Abstract: A circuit which includes an IP cell having a function select input signal line, combinatorial logic having an output connected to the function select input signal line of the IP cell, a configuration register having an output connected to an input of the combinatorial logic, wherein a high/low input signal line is also connected to the combinatorial logic, wherein the circuit provided that the configuration register receives configuration data during a start-up sequence, and configuration data is held by the combinatorial logic as the configuration register powers down during a functional mode.

Abstract: Embodiments for selecting regions of memory are described. For example, in one embodiment a memory device having an array of memory cells includes an array selection block. The array selection block receives an input signal indicative of a region in the array of memory cells. The array selection block generates a selection signal to map the region to at least one physical location in the array of memory cells, based on the detection of the number of defects in that location.

Abstract: An improved output buffer having single ended as well as differential signaling capabilities, providing symmetrical outputs for differential output configurations for both synchronous and asynchronous applications, comprising: a pair of flip-flops receiving complementary input signals, a pair of transmitters each having its input connected to the output of one of the flip-flops and providing its output to an output pin, a sense block that senses the transition on complementary input signals and generates a pulse at each transition, and a multiplexer having its output connected to the clock input of said pair of flip flop and one input connected to the output of the sense block for asynchronous mode operation, the second input connected to a clock signal for synchronous mode operation and a select input that enables either asynchronous mode or synchronous mode operation.

Abstract: Embodiments of power management modes for memory devices are disclosed.

Abstract: A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.

Abstract: A voltage regulator phase shedding system includes one or more subsystems to inventory memory power requirements of an IHS component, calculate a calculated memory power consumption, compare the calculated memory power consumption to a predetermined table of values to determine which phases of the voltage regulator to turn on, apply system power, assert desired phases of the voltage regulator after power is applied to the voltage regulator, and enable the voltage regulator to operate the desired phases of the voltage regulator.

Abstract: A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the memory cells, a switching element group provided in the cell array area adjacent to the memory cell array, the switching element group electrically connecting the source potential line to a ground potential line, when the memory cells are in an operation mode, a first P-type MIS transistor connected between the source potential line and the ground potential line, and fixing the source potential when the memory cells are in the sleep mode, and a bias generation circuit provided in a peripheral circuit area, and supplying a first bias potential to the first MIS transistor, the first MIS transistor being provided in the peripheral circuit area.

Abstract: A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a refresh operation is provided that includes initiating at least one refresh operation in the memory device, and ceasing generation of an internal clock signal timed with respect to the external clock signal for at least a portion of the time in which at least one refresh operation takes to complete.

Abstract: An SRAM device include: a latch unit for retaining data; one or more pass gate transistors controlled by a word line for coupling the latch unit to a bit line and a complementary bit line; and a power saving module coupled to the latch unit for raising a source voltage of the latch unit in response to a control signal on the word line, thereby reducing a leakage current for the latch unit.

Abstract: A deep power down mode control circuit is provided. The deep power down mode control circuit includes a deep power down signal generator for outputting a deep power down signal in response to a burst command signal and a clock enable signal, and a deep power down delay controller for delaying the deep power down signal for a predetermined delay time, and outputting the delayed signal.

Abstract: A semiconductor memory device may include a power line, an over driver, and/or an internal voltage driver. The power line may be connected to at least one sense amplifier. The at least one sense amplifier may be connected to a memory cell included in a memory block. The memory block may be included in one of a plurality of memory block units including one or more memory blocks. The over driver may be configured to apply an external voltage to the power line in a sensing period of the sense amplifier. The internal voltage driver may be configured to apply an internal voltage to the power line in an amplification period of the sense amplifier. The over driver may be configured to perform an over driving operation by each memory block unit.

Abstract: A semiconductor memory device operates by using a fixed power and a variable power. The device includes a plurality of word lines which select rows of a memory cell array, a plurality of word line drivers each of which is connected to a corresponding one of the word lines and includes a first CMOS gate, a first cutoff switch which is connected between a fixed power terminal and a power terminal of the first CMOS gate and cuts off the fixed power in a sleep mode, a switching circuit which is connected to the plurality of word lines and connects the plurality of word lines to a ground terminal in the sleep mode, and a power control circuit which generates the variable power by using the fixed power and sets the variable power to 0 V in the sleep mode.

Abstract: A semiconductor device includes a first and a second memory cell array each including a plurality of electrically reprogrammable memory cells arranged in the form of a matrix, the first memory cell array having a larger capacity than the second memory cell array; a plurality of word and bit lines connected to the memory cells; a data program and read control section including a plurality of decoders for, when performing data programming, read or erasure with respect to a corresponding memory cell, selecting, and applying a voltage to corresponding word and bit lines; and a power supply circuit for supplying power to the data program and read control section; wherein when the power supply circuit is to supply power to the second memory cell array, an output terminal of the power supply circuit is electrically connected to at least one of the decoders connected to the first memory cell array.

Abstract: A precharge voltage supply circuit and a semiconductor memory device using the same are described. The precharge voltage supply circuit includes a first voltage supplier configured to reduce a precharge voltage and supply the reduced precharge voltage in response to a power down mode signal that is activated in a power down mode, a second voltage supplier configured to supply a power voltage in a predetermined section from a point of time when exiting the power down mode, and a third voltage supplier configured to supply the precharge voltage after a lapse of the predetermined section.

Abstract: A non-volatile semiconductor memory device, comprising: an interface for receiving commands issued by a controller, the commands including an erase command; a functional entity with circuit components and having a terminal; a node; switchable circuitry capable of controllably switching between a first operational state in which the terminal is electrically connected to the node and a second operational state in which the terminal is electrically decoupled from the node, the node being configured to have a signal for the functional entity communicated through it when the switchable circuitry is in the first operational state; and a command processing unit configured to recognize the commands issued by the controller and, in response to recognizing the erase command, to cause the switchable circuitry to switch from the first operational state to the second operational state.

Abstract: A circuit for generating a voltage of a semiconductor memory apparatus includes a control unit that outputs a driving control signal in response to an enable signal and a burn-in signal, a first voltage generating unit that generates and outputs a first voltage in response to the enable signal, and a voltage maintaining unit that maintains the first voltage in response to the driving control signal.

Abstract: A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch.

Abstract: A method for suppressing a current leakage of a memory is provided. The memory at least includes a memory cell, an equalizing circuit, a current limiter, a word line and a pair of complementary bit lines. The method includes: having the memory cell entering a pre-charging mode; having the equalizing circuit and the current limiter being normally operated, so as for pre-charging the pair of complementary bit lines; applying a periodic control signal to the current limiter for controlling the current limiter to be either conducting or non-conducting, in which when the current limiter is non-conducting, a standby current leakage of the memory is suppressed, in which the standby current leakage is caused by a short circuit between the word line and the pair of complementary bit lines.

Abstract: An internal voltage generator of a semiconductor memory device controls generating an internal voltage according to an increase of the internal voltage during an active mode, to thereby decrease current consumption. The internal voltage generator of a semiconductor memory device includes a voltage sensor, a plurality of first control units, a plurality of second control units, and a plurality of voltage drivers. The voltage sensor detects an internal voltage. The plurality of first control units generate a plurality of internal control signals according to the voltage level of an output of the voltage sensor. The plurality of second control units generate a plurality of driver control signals in response to the plurality of internal control signals. The plurality of voltage drivers are turned on/off in response to the plurality of driver control signals.

Abstract: A system and method for providing voltage power gating. The system includes a device for providing voltage power gating. The device includes logic circuitry, a mechanism for receiving a control signal associated with the logic circuitry and a selector. The control signal indicates an active state or an idle state of the logic circuitry. The selector enables a power source to the logic circuitry in response to the control signal indicating the active state. The selector also disables the power source to the logic circuitry in response to the control signal indicating the idle state. Thus, the power source is dynamically eliminated from the logic circuitry on the device when it is in the idle state.

Abstract: Described herein are methods and apparatuses for write-assist voltage generation and power-down voltage scaling for static random access memory (SRAM) cells. According to various embodiments, an SRAM cell may include a local power supply voltage node for receiving a power supply voltage generated by a power supply voltage generator circuit, the generated power supply voltage being substantially equal to or less than a global power supply voltage provided to one or more transistors of the SRAM cell during a write-enable or power-down mode.

Abstract: One aspect in accordance with the present invention provides a memory system receiving a power supply from a host device. The memory system includes a non-volatile semiconductor memory and a controller for controlling writing and reading data to and from the semiconductor memory. The controller operates in such a manner that an amount of each of n currents is deducted from an amount of a current supplied from the power supply, the n currents having n values that gradually increase from the first to n-th.

Abstract: A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd? higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is in-creased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

Abstract: A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.

Abstract: A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes.

Abstract: A controlling circuit for controlling on-off switching of a power supply for a CMOS circuit includes a CMOS circuit (20) and a switch (30). The CMOS circuit includes a first circuit (50) for storing the system time of the computer and a second circuit (70) for storing other system settings of the computer. One terminal of the switch is connected to the first circuit and a power supply (10) in parallel via a resistor (R2). The one terminal of the switch is connected to the second circuit, and another terminal of the switch is connected to ground. When the one terminal of the switch is connected to the another terminal, the data stored in the second circuit is cleared while the system time stored in the first circuit remains.

Abstract: A semiconductor memory including a memory cell which is a MOSFET formed on an SOI substrate. The memory cell has a gate electrode connected to a word line, a drain region connected to a bit line, and a grounded source region. An operation of reading out data written in the memory cell is performed under a biasing condition by which a relationship Vd>Vg?Vth0 holds between a gate voltage Vg to be applied to said gate electrode, a drain voltage Vd to be applied to said drain region, a threshold voltage Vth1 of said MOSFET when a predetermined amount of holes are stored in a body region of the memory cell, and a threshold voltage Vth0 of said MOSFET when holes whose amount is smaller than the predetermined amount are stored in the body region.