Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Abstract: A temperature sensing system, which comprises: a temperature analyzing circuit, for sensing temperature and generating an analyzing result in response to the sensed temperature; and a control unit, for controlling a temperature sensing time interval; wherein the control unit continuously changes the temperature sensing time interval according to a predetermined temperature range in response to the sensed temperature.

Abstract: Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump.

Abstract: An internal power supply control circuit of a semiconductor memory includes a periodic signal generating unit that generates a periodic signal to generate a permission signal to intermittently permit supply of power from an internal power supply circuit of the semiconductor memory to an internal circuit thereof with a predetermined period, when a mode changes from a normal operation mode where power is always supplied from the internal power supply circuit to the internal circuit to a standby mode where consumption power is further suppressed as compared with consumption power in the normal operation mode, and a permission signal output unit that outputs the permission signal synchronized with the periodic signal to the internal power supply circuit, when a mode signal indicating any mode of the normal operation mode and the standby mode and the periodic signal are input and the input mode signal indicates the standby mode.

Abstract: A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost process when the first part code of a currently received address code is different from the first part code of a last received address code, otherwise a second boost process is activated.

Abstract: This disclosure has described a system for charging a capacitive energy storage device of at least one memory cell within an integrated circuit device from an initial voltage to a final voltage, wherein the integrated circuit device includes a plurality of memory cells which are formed at least in part by capacitive energy storage devices. During operation, the system charges the capacitive energy storage device from the initial voltage to the final voltage stepwise through one or more progressively higher intermediate voltage levels using one or more voltage sources. Specifically, each intermediate voltage level is between the initial voltage and the final voltage, and each voltage source generates a respective intermediate voltage level. Note that charging the capacitive energy storage device through one or more intermediate voltage levels reduces energy dissipation during the charging process.

Abstract: A memory device for use with a primary power source including: non-volatile memory; volatile memory; an interface for connecting to a backup power source; isolation logic for controlling access to the volatile memory by a host processor, said isolation logic having a first mode during which the isolation logic provides the host processor with access to the volatile memory for storing or reading data and a second mode during which the isolation logic isolates the volatile memory from access by the host processor; and a controller controlling the isolation logic, said controller programmed to place the isolation logic in the first mode when the volatile memory is being powered by the primary power source and, when power to the volatile memory from the primary power source is interrupted, to place the isolation logic in the second mode and transfer data from the volatile memory to the non-volatile memory.

Abstract: A method for data storage in a non-volatile memory includes storing data in the non-volatile memory using a first storage configuration while the non-volatile memory is supplied with electrical power. After storing the data, an indication is accepted, indicating that shut-off of the electrical power is imminent. Responsively to the indication and before the shut-off, at least some of the data is re-programmed in the non-volatile memory using a second storage configuration.

Abstract: A circuit configured to change a mode of a plurality of memory devices having a power saving mode includes a command queue configured to hold memory access, and a cancellation unit configured to cancel the power saving mode of target devices of the memory access held up to a predetermined stage of the command queue.

Abstract: Subject matter disclosed herein relates to improving memory cell retention for non-volatile flash memory.

Abstract: The present invention provides a solution to avoid the robustness problems of sub-threshold circuits by switching small parts of circuits to nominal-voltage only when they are being used, and switching them back to sub-threshold levels when the operation finishes. Such “hybrid sub-threshold” approach is capable of supporting ultra-low power operation without the disadvantages of sub-threshold circuits. Hybrid power saving mode for logic circuits provide significant power saving and fast recovery time without performance degradation.

Abstract: A memory module includes: an ODT circuit on a memory device and including pull-up and pull-down resistors connected between pull-up and pull-down transistors. A data masking (DM) pad is provided in a tap region of the module board. A current leakage monitoring unit is also provided and receives a ground state signal from the DM pad and a bit configuration signal from the memory device and disables the pull-up transistors to cut off a current path between the pull-up resistors of the ODT circuit and the DM pad during a ODT enable mode.

Abstract: A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.

Abstract: Embodiments of the present invention may provide a power-gating switch circuit. The power-gating switch circuit may comprise a first switch to connect a power supply to a virtual power supply and a second switch to connect the power supply to the virtual power supply in parallel to the first switch. The first switch may have a lower impedance than the second switch. When a wake up signal is received, the second switch may be turned on first and the first switch may be turned on after the virtual power supply reaches a predetermined voltage level.

Abstract: Disclosed herein is a semiconductor memory device which prevents the voltage of a select bit line from being reduced due to the action of coupling capacitance between the select bit line and a non-select bit line, reduces current consumption, and enables high speed reading of bit lines. The semiconductor memory device includes a plurality of memory banks, a plurality of second bit lines, a plurality of selector circuits, a voltage supply circuit. Each of the memory banks includes a plurality of first bit lines, a plurality of word lines, and a plurality of memory banks which are installed between the first bit lines and the word lines. The voltage supply circuit holds non-select bit lines of the first bit lines at the GND level at all times.

Abstract: The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period.

Abstract: When a leakage type determining circuit determines that leakage current components of a gate leakage and a substrate leakage are larger in a resume standby mode, a VDDR regulator generates a power supply voltage VDDR at a first voltage level lower than a power supply voltage VDD, and supplies the voltage as a power supply voltage VDDR1 to an SRAM module via a selector switch. When the leakage type determining circuit determines that a leakage current of a channel leakage is larger, the VDDR regulator supplies the power supply voltage VDDR1 higher than the first voltage level and lower than the power supply voltage VDD to the SRAM module. Also, an ARVSS regulator supplies a cell source power supply voltage higher than a reference voltage to an SRAM module in another region.

Abstract: A semiconductor memory device includes a first power switch for interrupting supply of a first power voltage to a first node in a standby mode, and a second power switch connected between the first node and a second node applied with a second power voltage.

Abstract: A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power consumed by the memory.

Abstract: A system and method for implementing a common control bus in a multi-regulator power supply integrated circuit. The integrated circuit may, for example, comprise first and second power regulator modules that control at least one characteristic of respective power signals. The integrated circuit may also, for example, comprise a communication interface module that receives power control information related to operation of the first and second power regulator modules over a shared data bus. An exemplary method may, for example, comprise receiving power control information over a data bus. The method may also, for example, comprise determining which of a plurality of power regulators corresponds to the received power control information. The method may further, for example, comprise determining a regulator control signal, based at least in part on the received power control information, and provide the regulator control signal to the determined regulator(s) to control operation of the determined regulator(s).

Abstract: A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.

Abstract: Semiconductor devices comprising at least one voltage sensor for sensing an operating voltage associated with an operational circuit of the semiconductor device. The at least one voltage sensor is configured to generate a signal indicative of a state of the operating voltage. Methods of monitoring a voltage in a semiconductor device include determining a magnitude of an operating voltage for an operational circuit in a semiconductor device. A signal may be generated indicating a state of the operating voltage.

Abstract: A memory circuit includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Configurations of the plurality of memory cells are determined depending on the data (“high” or “low”) which is stored in the memory cells. Data array such as a program stored in the memory circuit is analyzed in advance. In the case where “high” is the majority data, memory cells storing “high” are formed with vacant cells in which a semiconductor element is not formed.

Abstract: In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.

Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Abstract: A semiconductor memory device can automatically control signal transmission power on-chip based on a wireless signal transmission. The semiconductor memory device can have a multi-chip stack structure. A power initializing method of the semiconductor memory device can comprise providing a test signal generated by a signal-providing chip to a first chip, checking whether the test signal provided to the first chip has an error, providing the checking result to the signal-providing chip, setting the power of a first signal provided to the first chip according to the checking result, and setting the power of a signal provided to a second chip adjacent to the first chip and close to the signal-providing chip using the power of the first signal.

Abstract: An error correction circuit coupled to a plurality of memory cells in a memory device includes an error correcting code (“ECC”) generator and an ECC controller. The ECC generator is coupled to the memory cells and recognizes data bits stored in the memory cells as a plurality of data bit strings in a first direction and as a plurality of data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC generator generates a respective correction code in the first direction for each data bit string in the first direction and also generates a respective correction code in the second direction for each data bit string in the second direction. The ECC controller is coupled to the memory cells and the ECC generator.

Abstract: A communication device includes a voice data and RF integrated circuit (IC) that includes a memory module that stores a plurality of applications corresponding to a plurality of uses of the communication device. A processing module executes a selected one of the plurality of applications and selects one of a plurality of power modes based on a current one of the plurality of uses of the communication device corresponding to the selected one of the plurality of applications. The processing module generates a power mode signal based on the selected one of the plurality of power modes. An off-chip power management circuit receives the power mode signal and that generates a plurality of power supply signals to the voice data and RF IC based on the power mode signal.

Abstract: A bulk bias voltage generating device is configured to generate a first bulk bias voltage in a deep power down mode and a second bulk bias voltage in a normal mode. The first bulk bias voltage comprises an internal voltage level, and the second bulk bias voltage comprises an external voltage level.

Abstract: There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and a control circuit performing control in which, in a case where the temperature detected by the temperature sensor is higher than a threshold value, the switch is turned on when the inner circuit is in operation and the switch is turned off when the inner circuit is in non-operation, and in a case where the temperature detected by the temperature sensor is lower than the threshold value, the switch is turned on when the inner circuit is in operation and in non-operation.

Abstract: A semiconductor memory device includes n-wells (22) and p-wells (24) used to make up a plurality of memory cell elements (40). The n-wells (22) and p-5 wells (24) can be back-biased to improve reading and writing performance. One of the n-wells and p-wells can be globally biased while the other one of the n-wells and p-wells can be biased by groups, such as blocks, rows or columns. Error reduction and/or correction can be performed by adjusting the well bias.

Abstract: The invention relates to a controlled shut-down of an electronic circuit or circuits such that the electrical power consumption of that circuit or circuits is minimized and that each said circuit is at a status which is a pre-determined state (42; 52) of that said circuit wherein all of its own control and messaging signals are taken to their zero level. The present invention claimed relates to the methodology of entering said circuit into this pre-determined state (42;52); where all said signal and messaging lines are taken to zero; thereby reducing power consumption within an electronic circuit when its status is defined as being shut-down or standby.

Abstract: A SRAM that keeps the memory cell array under a low voltage in the Standby mode and Write mode, and raises the memory cell array supply voltage to a high voltage in the Read mode. A SRAM comprising: at least one memory cell circuit, comprising a latch circuit with at least two inverters, and comprising two power receiving terminals for receiving power; and a power supplying circuit, for providing the power to the memory cell circuit, such that the voltages at the power receiving terminals of the latch circuit is below a predetermined voltage level when data is written to the latch circuit. In one embodiment, the memory cell circuit includes a plurality of data accessing terminals and the data accessing terminals are respectively controlled by at least two pass-transistor switch devices.

Abstract: An integrated circuit memory 10, 12 has clock control circuitry 36 responsive to a clock signal CLK and a chip enable signal CEN to generate control signals for controlling the integrated circuit memory 10 in response to the clock signal CLK when the chip enable signal CEN indicates that the integrated circuit memory 10, 12 is active. When the chip enable signal CEN indicates that the integrated circuit memory 10, 12 is disabled, then power control circuitry 38 serve to switch portions of the integrated circuit memory 10, 12, such as word line driver circuitry 24, sense amplifiers 22 and buffer circuitry 30, into a low power state from an operating state. When the chip enable signal CEN activates the integrated circuit memory 10, 12, the power control circuitry 38 switches these portions 24, 22, 30 which are in the low power state back to the operating state.

Abstract: A nonvolatile memory system has a controller chip connected to a memory medium and several nonvolatile memory chips. The memory medium stores program codes for the controller chip to distribute an operation of the nonvolatile memory chips upon an instruction over time, so as to decentralize the peak current caused by the operation and thereby improve the stability of the system.

Abstract: A method of managing power consumption by a memory in a memory device includes determining whether the device is powered by a depletable power supply, and if it is determined that the device is powered by a depletable power supply, changing a behavior of the memory to regulate power consumed by the memory.

Abstract: A combo semiconductor memory apparatus capable of reducing current and power consumption is provided. The semiconductor memory apparatus includes: a signal generator that generates a voltage control signal according to the level of an external voltage; and a voltage generator that pumps up the level of the external voltage in response to the voltage control signal and outputs the pumped voltage to a high-level voltage output terminal, or supplies the external voltage as a high-level voltage.

Abstract: Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors. To overcome difficulties in writing data into the memory elements, signal strengths for one or more of the signals provided to the array may be adjusted. There may be two positive power supply voltages that are used in powering each memory element. One of the power supply voltages may be temporarily lowered relative to the other power supply voltage to enhance write margin during data loading operations. Other signal strengths that may be adjusted in this way include other power supply signals, data signal levels, address and clear signal magnitudes, and ground signal strengths. Adjustable power supply circuitry and data read-write control circuitry may be used in making these signal strength adjustments.

Abstract: Integrated circuits are provided with circuitry such as multiplexers that can be selectively configured to route different adjustable power supply voltages to different circuit blocks on the integrated circuits. The circuit blocks may contain memory elements that are powered by the power supply voltages and that provide corresponding static output control signals at magnitudes that are determined by the power supply voltages. The control signals from the memory elements may be applied to the gates of transistors in the circuit blocks. Logic on an integrated circuit may be powered at a given power supply voltage level. The memory elements may provide their output signals at overdrive voltage levels that are elevated with respect to the given power supply voltage level. Memory elements associated with circuit blocks that contain critical paths can be overdriven at voltages that are larger than memory elements associated with circuit blocks that contain noncritical paths.

Abstract: A circuit with leakage and data retention control includes at least one memory cell in a first memory array. The at least one memory cell is coupled to a first power supply voltage and a virtual ground. The circuit includes a current source and an NMOS transistor. The drain of the NMOS transistor is coupled to the virtual ground and the gate of the NMOS transistor is coupled to the current source.

Abstract: A computer system and a method of controlling a computer system, the computer system including: a first memory corresponding to a first channel and a second memory corresponding to a second channel; a data processor to process the data of the first and second channels in a time division manner; and a controller to inactivate the second channel if an amount of the data processed by the data processor is less than or equal to a predetermined value.

Abstract: A method of managing power states of memory modules while performing memory access operations is disclosed. Memory modules are in a power saving state until an access operation involving the module is to be performed. The module is placed in an operational mode, then the access operation is performed, then the module is returned to the power saving state. Apparatus and systems using the method are also disclosed and claimed.

Abstract: A semiconductor memory device comprises a power control circuit for outputting a power voltage in a read operation period and a write operation period, and an internal circuit operating by the power voltage supplied thereto.

Abstract: An electrically programmable fuse (e-fuse) apparatus includes an e-fuse macro and a switch device. The e-fuse macro is disposed in an integrated circuit, and has a plurality of e-fuse units. The switch device is disposed in the integrated circuit, and has an output node coupled to the e-fuse units and a first input node coupled to a first power source which supplies a first reference voltage acting as a programming voltage of the e-fuse macro. The switch device connects the first power source to the e-fuse units when the e-fuse macro is operated under a programming mode.

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Abstract: A voltage regulator circuit for a memory circuit comprises a voltage divider, a capacitor, an active-mode voltage regulator and a standby-mode voltage regulator. The active-mode voltage regulator is always on while in active mode, and turned on whenever a refresh is requested. The standby-mode voltage regulator is periodically turned on while in standby mode, and turned on whenever a refresh is requested. In addition, the active voltage regulator uses stronger transistors than those used by the standby-mode voltage regulator, and both the active-mode voltage regulator and the standby-mode voltage regulator are coupled to the voltage divider and the capacitor.

Abstract: In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.

Abstract: A voltage stabilization circuit includes a control signal generating unit to generate a control signal that is enabled when a supply voltage is unstable and a voltage level maintaining unit for selectively controlling total capacitance of a plurality of capacitors to stabilize the supply voltage in response to the control signal.

Abstract: A semiconductor integrated circuit device with reduced consumption current is provided. A first step-down circuit stationarily forms internal voltage lower than supply voltage supplied through an external terminal. A second step-down circuit is switched between first mode and second mode according to control signals. In first mode, the internal voltage is formed from the supply voltage supplied through the external terminal and is outputted through a second output terminal. In second mode, operating current for a control system that forms the internal voltage is interrupted and an output high impedance state is established. The first output terminal of the first step-down circuit and the second output terminal of the second step-down circuit are connected in common, and the internal voltage is supplied to internal circuits.

Abstract: In a method, system and apparatus for management of dynamic memory in battery-powered devices, information is stored in dynamic memory, such as SDRAM chips. Chip partitioning minimizes the number of chips requiring power, minimum refresh rates reduce the power needed to maintain information, and a threshold for determining when to power down a battery powered device are used to maximize battery life.