Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

Abstract: According to at least one embodiment, a method for writing, by a computing thread, data to a ring buffer is disclosed. The method includes determining whether the ring buffer is full. If the ring buffer is not full, the method further includes: reserving an element of the ring buffer for writing the data, wherein reserving the element includes incrementing a size variable corresponding to a number of stored elements in the ring buffer; reserving a portion of the ring buffer at which the data is to be written; and determining whether a state of the portion of the ring buffer is in change by at least one other computing thread. If the state is not in change, the method further includes: marking the state of the portion of the ring buffer as being in change by the computing thread; and writing the data to the portion of the ring buffer.

Abstract: Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a data determination module configured to read read data from a memory bank, and determine whether to invert the read data according to the number of bits of high data in the read data to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line; a data receiving module configured to determine whether to invert the global bus data according to the inversion flag data to output cache data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the cache data to generate output data of the DQ port; and a precharge module configured to set an initial state of the global bus to Low.

Abstract: A system includes a random access memory organized into individually addressable words. Streaming access control circuitry is coupled to word lines of the random access memory. The streaming access control circuitry responds to a request to access a plurality of individually addressable words of a determined region of the random access memory by generating control signals to drive the word lines to streamingly access the plurality of individually addressable words of the determined region. The request indicates an offset associated with the determined region and a pattern associated with the streaming access.

Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells that are connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver and local write drivers included correspondingly in the segments; and the global write driver including a first equalizer circuit, arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line, and the global write driver and the local write drivers each including first inversion couplings (coupled in parallel between the GWB line and the LWB line) and second inversion couplings (coupled in parallel between the GWB_bar line and the LWB_bar line).

Abstract: Examples are disclosed that relate to a multi-port synchronous dynamic random access memory (SDRAM). One example provides a multi-port SDRAM comprising a first port, a second port, a first memory portion, and a second memory portion. At least the first memory portion is configured as shared such that the first memory portion is accessible at the first port and not the second port in a first mode, and the first memory portion is accessible at the second port and not the first port in a second mode. The multi-port SDRAM further comprises a mode controller controllable to selectively change the multi-port SDRAM between at least the first mode and the second mode.

Abstract: A memory circuit includes: a memory configured to store a data unit and parity bits, the parity bits including data parity bits based on the data unit and write address parity bits based on a write address associated with the stored data unit; a write address port configured to receive the write address for the stored data unit; a first decoding circuit configured to determine when a data error exists based on the stored data unit and the data parity bits; a second decoding circuit configured to generate a decoded write address from a read address and the write address parity bits; and an error detecting circuit configured to determine when an address error exists based on a comparison of the decoded write address to the read address.

Abstract: A method of implementing a processor architecture and corresponding system includes operands of a first size and a datapath of a second size. The second size is different from the first size. Given a first array of registers and a second array of registers, each register of the first and second arrays being of the second size, selecting a first register and corresponding second register from the first array and the second array, respectively, to perform operations of the first size. This allows a user, who is interfacing with the hardware processor through software, to provide data of the datapath bit-width instead of the register bit-width. Advantageously, the user is agnostic to the size of the registers.

Abstract: A data synthesizer includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to latch a first data under control of a first latch clock signal. The second input circuit is configured to latch a second data under control of the first latch clock signal. A phase of the first data is the same as a phase of the second data. The output circuit is connected to the first input circuit and the second input circuit. The output circuit is configured to output the first data and the second data in sequence.

Abstract: A receiving device uses an elastic buffer that is wider than the number of data elements transferred in each cycle. To compensate for frequency differences between the transmitter and the receiver, the transmitting device periodically sends a skip request with a default number of skip data elements. If the elastic buffer is filling, the receiving device ignores one or more of the skip data elements. If the elastic buffer is emptying, the receiving device adds one or more skip data elements to the skip request. To maintain the ordering of data despite the manipulation of the skip data elements, two rows of the wide elastic buffer are read at a time. This allows construction of a one-row result from any combination of the data elements of the two rows. The column pointers are adjusted appropriately, to ensure that they continue to point to the next data to be read.

Abstract: A memory circuit includes a precharge circuit and control circuit. The precharge circuit comprises a first precharge circuit, second precharge circuit, first power supply end, second power supply end, first control end, second control end and data end. The first precharge circuit is connected with the first power supply end, first control end and data end. The second precharge circuit is connected with the second power supply end, second control end and data end. A first precharge voltage is input into the first power supply end, and a second precharge voltage is input into the second power supply end. The control circuit is configured to control connection and disconnection between the data end and second power supply end and to control connection and disconnection between the data end and first power supply end.

Abstract: A multichannel data packer includes a plurality of two-input multiplexers and a controller. The plurality of two-input multiplexers is arranged in 2N rows and N columns in which N is an integer greater than 1. Each input of a multiplexer in a first column receives a respective bit stream of 2N channels of bit streams. Each respective bit stream includes a bit-stream length based on data in the bit stream. The multiplexers in a last column output 2N channels of packed bit streams each having a same bit-stream length. The controller controls the plurality of multiplexers so that the multiplexers in the last column output the 2N channels of bit streams that each has the same bit-stream length.

Abstract: Error correction values for a memory device include row error correction values and column error correction values for the same memory array. The memory device includes a memory array that is addressable in two spatial dimensions: a row dimension and a column dimension. The memory array is written as rows of data, and can be read as rows in the row dimension or read as columns in the column dimension. A data write triggers updates to row error correction values and to column error correction values.

Abstract: A memory system includes a column circuit to generate a logic state of data stored in one of the memory bit cell circuits in a column in a read operation. The column circuit includes a read control circuit to cause a float control circuit to couple a read bit line to a charged evaluation output line in a read operation and cause the float control circuit to decouple the read bit line from the evaluation output line in an idle stage. Decoupling the read bit line from the charged evaluation output line reduces power lost between read operations by current leaking through read port circuits in the memory bit cell circuits to which the read bit line is coupled. The memory system may include at least one read bit line, each coupled to a respective float control circuit and a respective plurality of memory bit cell circuits in a column.

Abstract: A memory device may include a memory array having a plurality of memory cells and a first column plane having multiple column select lines. The first column select lines of the first column plane may access a first set of the memory cells associated with the first column plane. Additionally, the memory device may include a second column plane having a multiple column select lines to access a second set of the memory cells associated with the second column plane. The memory device may also include a column select line shared between the first column plane and the second column plane. The column select line may access a third set of the memory cells associated with the first column plane and a fourth set of the memory cells associated with the second column plane.

Abstract: Memory device data-access schemes are disclosed. Various embodiments may include a memory device including a first column plane, a second column plane, and a data-steering circuit. The first column plane may include a first edge, a second edge, and a first number of digit lines arranged between the first edge and the second edge. The second column plane may include a third edge positioned adjacent to the second edge, a fourth edge, and a second number of digit lines arranged between the third edge and the fourth edge. The data-steering circuit may be configured to logically relate a first digit line of the first number of digit lines to a second digit line of the second number of digit lines, the first digit line proximate to the first edge and the second digit line proximate to the fourth edge. Associated systems and methods are also disclosed.

Abstract: A method for memory block management includes identifying a first group of bit lines corresponding to memory blocks of a 3-dimensional memory array. The method also includes biasing the first group of bit lines to a first voltage using respective bit line biasing transistors. The method also includes identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines. The method also includes logically grouping memory addresses of memory cells for each respective sub-memory block associated with the first group of bit lines.

Abstract: A memory controller circuit is disclosed which is coupleable to a first memory circuit, such as DRAM, and includes: a first memory control circuit to read from or write to the first memory circuit; a second memory circuit, such as SRAM; a second memory control circuit adapted to read from the second memory circuit in response to a read request when the requested data is stored in the second memory circuit, and otherwise to transfer the read request to the first memory control circuit; predetermined atomic operations circuitry; and programmable atomic operations circuitry adapted to perform at least one programmable atomic operation. The second memory control circuit also transfers a received programmable atomic operation request to the programmable atomic operations circuitry and sets a hazard bit for a cache line of the second memory circuit.

Abstract: A memory device includes a memory group and a control circuit. The memory group includes several memory banks. The control circuit is coupled to the memory group. The control circuit includes a tri-state logic enable circuit and an address decoding circuit. The tri-state logic enable circuit is configured to temporarily store several temporarily stored address signals, to output the several temporarily stored address signals according to a synchronization signal, to decode the several temporarily stored address signals to generate an enable signal, and to transmit the enable signal to one of the several memory banks. The address decoding circuit is configured to decode the several temporarily stored address signals to drive the one of the several memory banks.

Abstract: Methods, systems, and devices for command triggered power gating for a memory device are described. Row logic circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. The row logic circuitry may be on when a bank of the memory array is an active state but may be off when the bank is in a stand-by or power-down state. Additionally or alternatively, error correction circuitry for a memory array may be powered up (on) or powered down (off) independent of at least some other components of a memory device. The error correction circuitry may be on during an access portion of an access sequence but may otherwise be off.

Abstract: A method of fabricating (a distributed write driving arrangement for a semiconductor memory device) includes: forming bit cells and a local write driver in a first device layer; forming a local write bit (LWB) line and a local write bit_bar (LWB_bar) line in a first metallization layer; connecting each of the bit cells correspondingly between the LWB and LWB_bar lines; connecting the local write driver to the LWB line and the LWB_bar line; forming a global write bit (GWB) line and a global write bit_bar (GWBL_bar) line in a second metallization layer; connecting the GWB line to the LWB line; connecting the GWB line and the GWBL_bar line to the corresponding LWB line and LWB_bar line; forming a global write driver in a second device layer; and connecting the global write driver to the GWB line and the GWBL_bar line.

Abstract: Various implementations described herein are related to a device having memory circuitry with a bitcell array. The device may include a frontside power network that is coupled to the bitcell array, and the device may include a backside power network that provides power to the bitcell array. The device may include transition vias that couple the backside power network to the frontside power network, and the backside power network may provide power to the bitcell array by way of the transition vias being coupled to the frontside power network.

Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

Abstract: The data transfer has room for improvement of reduction in the operating electric current flowing on the signal bus and correct acquisition of the large amount of data. Each of data, a first clock signal and a second clock signal, a phase of which shifts by a predetermined amount from the first clock signal, has an amplitude that is smaller than an amplitude of a power supply voltage, and each of a semiconductor device and a memory device takes input of data in synchronization with rise edges of first and second clock signals.

Abstract: The disclosed computer-implemented method for performing load balancing and distributed high-availability may include (i) detecting through a group communication channel that links all nodes of a computing cluster that an overburdened node of the computing cluster has fallen below a predefined performance level, (ii) determining to transfer a specific microservice transaction from the overburdened node to a helper node in the computing cluster, (iii) copying data for the specific microservice transaction from a portion of a central data store that is reserved for the overburdened node to another data store that is reserved for the helper node, and (iv) completing, by the helper node, the specific microservice transaction by referencing the copied data for the specific microservice transaction in the data store that is reserved for the helper node. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit. A resilient system and method, in accordance with the invention, are disclosed for detecting a fault or an uncorrectable error and isolating the fault. Isolation of the fault prevents further propagation of the fault throughout the system. The resilient system includes isolation logic or an isolation unit that isolates the fault.

Abstract: A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a Syndrome stage for generating syndromes based on a BCH encoded word, a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients, a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iteration information, and a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information. The BCH decoder decodes the BCH encoded word using the reordered error bits.

Abstract: A memory controller circuit is disclosed which is coupleable to a first memory circuit, such as DRAM, and includes: a first memory control circuit to read from or write to the first memory circuit; a second memory circuit, such as SRAM; a second memory control circuit adapted to read from the second memory circuit in response to a read request when the requested data is stored in the second memory circuit, and otherwise to transfer the read request to the first memory control circuit; predetermined atomic operations circuitry; and programmable atomic operations circuitry adapted to perform at least one programmable atomic operation. The second memory control circuit also transfers a received programmable atomic operation request to the programmable atomic operations circuitry and sets a hazard bit for a cache line of the second memory circuit.

Abstract: A nonvolatile memory device includes a first memory cell array, a first bi-directional multiplexer, a first register, a second register, a first I/O pad and a second I/O pad. The first memory cell array stores first data. The first bi-directional multiplexer receives the first data and distributes the first data into first sub-data and second sub-data. The first register stores first sub-data from the first bi-directional multiplexer. The second register stores second sub-data from a second bi-directional multiplexer. The first I/O pad outputs the first sub-data from the first register to outside. The second I/O pad outputs the second sub-data from the second register to the outside.

Abstract: The present invention discloses a data processing method and system for a scalable multi-port memory. The multi-port memory is a 2-read n-write multi-port memory unit. The method comprises: assembling two 2R1W memories into one Bank memory unit; assembling n/2 Bank memory units in depth into a hardware architecture of one 2-read n-write multi-port memory unit; under one clock cycle, when data is written into the 2-read n-write multi-port memory unit, if the size of the data is less than or equal to the bit width of the 2R1W memory, writing the data into different 2R1W memories respectively; and if the size of the data is greater than the bit width of the 2R1W memory, waiting for a second clock cycle, and when the second clock cycle comes, writing the high and low bits of the written data into the two 2R1W memories of one Bank memory unit respectively.

Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes an output buffer. The output buffer is configured to simultaneously obtain first data from the first memory array and second data from the second memory array according a first address signal, and selectively provide the first data or the second data as an output according to a control signal. Binary representation of the first data is complementary to that of the second data.

Abstract: A system and methods for in-storage on-demand data decompression. Compressed data are stored in a storage device connected to a host computer. When decompressed data are needed, the host computer sends a decompression command to the storage device indicating which data are to be decompressed, and instructing it how to decompress the data. The storage device decompresses the data and stores the decompressed data, making it available to the host.

Abstract: Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.

Abstract: A level shifter generates at least three separate voltage rails. The level shifter features two cross-coupled devices coupled together in parallel by a capacitor. A first stage includes a PMOS cross-coupled device in series with a PMOS cascode circuit that generates an upper voltage rail. A second stage includes a NMOS cross-coupled device in series with a NMOS cascode circuit that generates a lower rail. A third stage includes the PMOS cascode circuit and the NMOS cascode circuit that together are configured to generate a third voltage rail.

Abstract: A refresh control device may include, an address processing circuit configured to divide an input address into a plurality of partial addresses, and generate an updated partial address input count based on an input count for each partial address value. The refresh control device also includes a target refresh address generation circuit configured to generate a target refresh address based on the updated partial address input count, and a target refresh circuit configured to perform a refresh operation on a word line corresponding to the target refresh address.

Abstract: A clock-receiving system may receive a host clock signal on a communications bus from a clock-sending system. Circuitry of a critical path of the clock-receiving system may communicate the clock signal to a multiplexer configured directly behind output driver circuitry. Core logic circuitry and data path circuitry may communicate pairs of phase-shifted data signals to the multiplexer. The multiplexer may use the clock signal and the pairs of phase-shifted data signals to generate an output pair of data signals, and send the output pair of data signals to the output driver circuitry. In turn, the output driver circuitry may generate an output data signal for communication on the communications bus. The clock-receiving system may enable the critical path and use the multiplexer to generate the output data signal when in a low operating voltage mode.

Abstract: A semiconductor memory in accordance with an embodiment includes: a control unit configured to generate a plurality of second control signals in response to a page size signal and a plurality of first control signals; a plurality of input/output switches configured to be coupled to each of a plurality of unit memory blocks and activated in response to the plurality of second control signals; and a plurality of page change switches configured to couple data lines of the plurality of unit memory blocks in response to the page size signal.

Abstract: Apparatuses and methods are provided that include a multiplexer configured to generate a plurality of sums of a plurality of data words, wherein the plurality of data words is received by the multiplexer and identified as unmasked based on a data mask. The multiplexer is also configured to determine whether each sum of the plurality of sums indicates that a corresponding data word of the plurality of data words is masked. The multiplexer is further configured to shift the plurality of data words to remove the corresponding masked data word from the plurality of data words. The multiplexer is also configured to output only the data words identified as unmasked based on the data mask.

Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.

Abstract: The semiconductor memory device includes a memory cell array and an error correction code (ECC) circuit. The memory cell array is divided into a first memory region and a second memory region. Each of the first and second memory regions includes a plurality of pages each page including a plurality of memory cells connected to a word line. The ECC circuit corrects single-bit errors of the first memory region using parity bits. The first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region.

Abstract: An operating method for a memory. The method includes obtaining a first address via an address bus and a first command via a command bus from a controller, obtaining a second address via the address bus and a second command via the command bus from the controller after the first command is obtained, and combining the first address and the second address to obtain a valid address. The valid address is a row address when each of the first command and the second command is an active command, and the valid address is a column address when the second command is an access command.

Abstract: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

Abstract: An access method for a dynamic random access memory (DRAM) is provided. The method includes partitioning a row address into a first portion and a second portion; providing the first portion of the row address via an address bus and a first active command via a command bus to the memory; and providing the second portion of the row address via the address bus and a second active command via the command bus to the memory after the first active command is provided. The address bus is formed by a plurality of address lines, and a quantity of the address lines is smaller than the number of bits of the row address. A corresponding electronic device is also provided.

Abstract: A circuit is presented to reduce power while transmitting high speed signals across a long length of wire on an integrated circuit. A PMOS is used as a low swing driver, where the PMOS is connected between the driver's output and ground. The gate of the PMOS is also set to ground, while the input signal is connected to the bulk. The output is then transmitted over the signal path to an analog receiver, where both single ended and differential embodiments are presented. For a single ended version, a reference voltage for the receiver can be provided by a second, similarly connected PMOS whose bulk has an input signal at an intermediate level of input swing at the transmitter PMOS.

Abstract: A memory cell of a resistive random access memory and a manufacturing method thereof are provided. The method includes the following steps. A first electrode is formed. A metal oxide layer is formed on the first electrode. An electrode buffer stacked layer is formed on the metal oxide layer and includes a first buffer layer and a second buffer layer, and the first buffer layer is located between the second buffer layer and the metal oxide layer. The second buffer layer reacts with oxygen from the first buffer layer more strongly than the first buffer layer reacts with oxygen from the metal oxide layer. A second electrode layer is formed on the electrode buffer stacked layer.

Abstract: Provided are a computer system and a method of controlling the same. The computer system includes: a central processing unit (CPU) configured to drive an application program; and a main memory configured to provide the CPU with a memory space for driving of the application program and to store a processing result of the CPU. The main memory includes: a nonvolatile memory including a first memory area configured to store data and a second memory area configured to store address information of the data; a memory controller configured to control the nonvolatile memory; and a memory manager configured to read the address information from the second memory area and delete the data stored at the first area according to the read address information, in response to a data delete command from the CPU and a control of the memory controller.

Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

Abstract: The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register.

Abstract: The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.