Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

Abstract: The data transfer has room for improvement of reduction in the operating electric current flowing on the signal bus and correct acquisition of the large amount of data. Each of data, a first clock signal and a second clock signal, a phase of which shifts by a predetermined amount from the first clock signal, has an amplitude that is smaller than an amplitude of a power supply voltage, and each of a semiconductor device and a memory device takes input of data in synchronization with rise edges of first and second clock signals.

Abstract: The disclosed computer-implemented method for performing load balancing and distributed high-availability may include (i) detecting through a group communication channel that links all nodes of a computing cluster that an overburdened node of the computing cluster has fallen below a predefined performance level, (ii) determining to transfer a specific microservice transaction from the overburdened node to a helper node in the computing cluster, (iii) copying data for the specific microservice transaction from a portion of a central data store that is reserved for the overburdened node to another data store that is reserved for the helper node, and (iv) completing, by the helper node, the specific microservice transaction by referencing the copied data for the specific microservice transaction in the data store that is reserved for the helper node. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A resilient system implementation in a network-on-ship with at least one functional logic unit and at least one duplicated logic unit. A resilient system and method, in accordance with the invention, are disclosed for detecting a fault or an uncorrectable error and isolating the fault. Isolation of the fault prevents further propagation of the fault throughout the system. The resilient system includes isolation logic or an isolation unit that isolates the fault.

Abstract: A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a Syndrome stage for generating syndromes based on a BCH encoded word, a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients, a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iteration information, and a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information. The BCH decoder decodes the BCH encoded word using the reordered error bits.

Abstract: A nonvolatile memory device includes a first memory cell array, a first bi-directional multiplexer, a first register, a second register, a first I/O pad and a second I/O pad. The first memory cell array stores first data. The first bi-directional multiplexer receives the first data and distributes the first data into first sub-data and second sub-data. The first register stores first sub-data from the first bi-directional multiplexer. The second register stores second sub-data from a second bi-directional multiplexer. The first I/O pad outputs the first sub-data from the first register to outside. The second I/O pad outputs the second sub-data from the second register to the outside.

Abstract: A memory controller circuit is disclosed which is coupleable to a first memory circuit, such as DRAM, and includes: a first memory control circuit to read from or write to the first memory circuit; a second memory circuit, such as SRAM; a second memory control circuit adapted to read from the second memory circuit in response to a read request when the requested data is stored in the second memory circuit, and otherwise to transfer the read request to the first memory control circuit; predetermined atomic operations circuitry; and programmable atomic operations circuitry adapted to perform at least one programmable atomic operation. The second memory control circuit also transfers a received programmable atomic operation request to the programmable atomic operations circuitry and sets a hazard bit for a cache line of the second memory circuit.

Abstract: The present invention discloses a data processing method and system for a scalable multi-port memory. The multi-port memory is a 2-read n-write multi-port memory unit. The method comprises: assembling two 2R1W memories into one Bank memory unit; assembling n/2 Bank memory units in depth into a hardware architecture of one 2-read n-write multi-port memory unit; under one clock cycle, when data is written into the 2-read n-write multi-port memory unit, if the size of the data is less than or equal to the bit width of the 2R1W memory, writing the data into different 2R1W memories respectively; and if the size of the data is greater than the bit width of the 2R1W memory, waiting for a second clock cycle, and when the second clock cycle comes, writing the high and low bits of the written data into the two 2R1W memories of one Bank memory unit respectively.

Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.

Abstract: Memories with symmetric read current profiles are provided. A memory includes a first memory array formed by a plurality of memory cells, a second memory array formed by a plurality of memory cells, and a read circuit. The read circuit includes an output buffer. The output buffer is configured to simultaneously obtain first data from the first memory array and second data from the second memory array according a first address signal, and selectively provide the first data or the second data as an output according to a control signal. Binary representation of the first data is complementary to that of the second data.

Abstract: A system and methods for in-storage on-demand data decompression. Compressed data are stored in a storage device connected to a host computer. When decompressed data are needed, the host computer sends a decompression command to the storage device indicating which data are to be decompressed, and instructing it how to decompress the data. The storage device decompresses the data and stores the decompressed data, making it available to the host.

Abstract: Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.

Abstract: A level shifter generates at least three separate voltage rails. The level shifter features two cross-coupled devices coupled together in parallel by a capacitor. A first stage includes a PMOS cross-coupled device in series with a PMOS cascode circuit that generates an upper voltage rail. A second stage includes a NMOS cross-coupled device in series with a NMOS cascode circuit that generates a lower rail. A third stage includes the PMOS cascode circuit and the NMOS cascode circuit that together are configured to generate a third voltage rail.

Abstract: A clock-receiving system may receive a host clock signal on a communications bus from a clock-sending system. Circuitry of a critical path of the clock-receiving system may communicate the clock signal to a multiplexer configured directly behind output driver circuitry. Core logic circuitry and data path circuitry may communicate pairs of phase-shifted data signals to the multiplexer. The multiplexer may use the clock signal and the pairs of phase-shifted data signals to generate an output pair of data signals, and send the output pair of data signals to the output driver circuitry. In turn, the output driver circuitry may generate an output data signal for communication on the communications bus. The clock-receiving system may enable the critical path and use the multiplexer to generate the output data signal when in a low operating voltage mode.

Abstract: A refresh control device may include, an address processing circuit configured to divide an input address into a plurality of partial addresses, and generate an updated partial address input count based on an input count for each partial address value. The refresh control device also includes a target refresh address generation circuit configured to generate a target refresh address based on the updated partial address input count, and a target refresh circuit configured to perform a refresh operation on a word line corresponding to the target refresh address.

Abstract: A semiconductor memory in accordance with an embodiment includes: a control unit configured to generate a plurality of second control signals in response to a page size signal and a plurality of first control signals; a plurality of input/output switches configured to be coupled to each of a plurality of unit memory blocks and activated in response to the plurality of second control signals; and a plurality of page change switches configured to couple data lines of the plurality of unit memory blocks in response to the page size signal.

Abstract: Apparatuses and methods are provided that include a multiplexer configured to generate a plurality of sums of a plurality of data words, wherein the plurality of data words is received by the multiplexer and identified as unmasked based on a data mask. The multiplexer is also configured to determine whether each sum of the plurality of sums indicates that a corresponding data word of the plurality of data words is masked. The multiplexer is further configured to shift the plurality of data words to remove the corresponding masked data word from the plurality of data words. The multiplexer is also configured to output only the data words identified as unmasked based on the data mask.

Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.

Abstract: The semiconductor memory device includes a memory cell array and an error correction code (ECC) circuit. The memory cell array is divided into a first memory region and a second memory region. Each of the first and second memory regions includes a plurality of pages each page including a plurality of memory cells connected to a word line. The ECC circuit corrects single-bit errors of the first memory region using parity bits. The first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region.

Abstract: An operating method for a memory. The method includes obtaining a first address via an address bus and a first command via a command bus from a controller, obtaining a second address via the address bus and a second command via the command bus from the controller after the first command is obtained, and combining the first address and the second address to obtain a valid address. The valid address is a row address when each of the first command and the second command is an active command, and the valid address is a column address when the second command is an access command.

Abstract: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

Abstract: An access method for a dynamic random access memory (DRAM) is provided. The method includes partitioning a row address into a first portion and a second portion; providing the first portion of the row address via an address bus and a first active command via a command bus to the memory; and providing the second portion of the row address via the address bus and a second active command via the command bus to the memory after the first active command is provided. The address bus is formed by a plurality of address lines, and a quantity of the address lines is smaller than the number of bits of the row address. A corresponding electronic device is also provided.

Abstract: A circuit is presented to reduce power while transmitting high speed signals across a long length of wire on an integrated circuit. A PMOS is used as a low swing driver, where the PMOS is connected between the driver's output and ground. The gate of the PMOS is also set to ground, while the input signal is connected to the bulk. The output is then transmitted over the signal path to an analog receiver, where both single ended and differential embodiments are presented. For a single ended version, a reference voltage for the receiver can be provided by a second, similarly connected PMOS whose bulk has an input signal at an intermediate level of input swing at the transmitter PMOS.

Abstract: A memory cell of a resistive random access memory and a manufacturing method thereof are provided. The method includes the following steps. A first electrode is formed. A metal oxide layer is formed on the first electrode. An electrode buffer stacked layer is formed on the metal oxide layer and includes a first buffer layer and a second buffer layer, and the first buffer layer is located between the second buffer layer and the metal oxide layer. The second buffer layer reacts with oxygen from the first buffer layer more strongly than the first buffer layer reacts with oxygen from the metal oxide layer. A second electrode layer is formed on the electrode buffer stacked layer.

Abstract: Provided are a computer system and a method of controlling the same. The computer system includes: a central processing unit (CPU) configured to drive an application program; and a main memory configured to provide the CPU with a memory space for driving of the application program and to store a processing result of the CPU. The main memory includes: a nonvolatile memory including a first memory area configured to store data and a second memory area configured to store address information of the data; a memory controller configured to control the nonvolatile memory; and a memory manager configured to read the address information from the second memory area and delete the data stored at the first area according to the read address information, in response to a data delete command from the CPU and a control of the memory controller.

Abstract: The semiconductor integrated circuit includes a command decoder, a shift register unit and a command address latch unit. The command decoder is responsive to an external command defining write and read modes and configured to provide a write command or a read command according to the external command using a rising or falling clock. The shift register unit is configured to shift an external address and the write command by a write latency in response to the write command. The column address latch unit is configured to latch and provide the external address as a column address in the read mode, and to latch a write address, which is provided from the shift register unit, and provide the write address as the column address in the write mode.

Abstract: The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register.

Abstract: The present application describes a crossbar memory array. The memory array includes a first array of parallel nanowires of a first material and a second array of parallel nanowires of a second material. The first and the second array are oriented at an angle with each other. The array further includes a plurality of nanostructures of non-crystalline silicon disposed between a nanowire of the first material and a nanowire of the second material at each intersection of the two arrays. The nanostructures form a resistive memory cell together with the nanowires of the first and second materials.

Abstract: A NAND flash memory in which a command/address pin is separated from a data input/output pin. The NAND flash memory includes a memory cell array used for storing data, a command/address pin through which a command and an address are received for transmitting data in the memory cell array, and a data input/output pin through which data are transmitted in the memory cell array. The command/address pin is separated from the data input/output pin in the NAND flash memory. Data input/output speed is increased. Furthermore, the NAND flash memory can perform a bank interleaving operation with a minimal delay time.

Abstract: A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer.

Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract: A circuit arrangement, having a plurality of electronic components; a plurality of first access lines and second access lines, wherein each electronic component is coupled with at least one first access line and at least one second access line; an access controller configured to control an access to at least one electronic component of the plurality of electronic components via the at least one first access line and the at least one second access line; a bias circuit configured to provide a defined potential to at least one of the first access lines, wherein the bias circuit is configured, during an access to an electronic component via one selected first access line of the plurality of first access lines, to provide the defined potential to one or two first access lines of the plurality of first access lines, wherein the one or two first access lines are arranged adjacent to the selected first access line, and, wherein during the access to the electronic component, the potentials of the first access lines of

Abstract: A memory device comprises a nonvolatile memory device and a controller. The nonvolatile memory comprises a first memory area comprising single-bit memory cells and a second memory area comprising multi-bit memory cells. The controller is configured to receive a first unit of write data, determine a type of the first unit of write data, and based on the type, temporarily store the first unit of write data in the first memory area and subsequently migrate the temporarily stored first unit of write data to the second memory area or to directly store the first unit of write data in the second memory area, and is further configured to migrate a second unit of write data temporarily stored in the first memory area to the second memory area where the first unit of write data is directly stored in the second memory area.

Abstract: The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.

Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.

Abstract: A refresh circuit and a semiconductor memory device including the refresh circuit are disclosed. The refresh circuit includes a mode register, a refresh controller and a multiplexer circuit. The mode register generates a mode register signal having information relating to a memory bank on which a refresh operation is to be performed. The refresh controller generates a self-refresh active command and a self-refresh address based on a self-refresh command and an oscillation signal. The multiplexer circuit may include a plurality of multiplexers. Each of the multiplexers selects one of an active command and the self-refresh active command in response to bits of the mode register signal. Each of the multiplexers generates a row active signal based on the selected command, and selects one of an external address and the self-refresh address to generate a row address.

Abstract: A semiconductor memory device includes a first semiconductor chip including a first pad group configured to input/output first data and a second pad group configured to input/output second data; and a second semiconductor chip in a stack with the first semiconductor chip and configured to be electrically connected to the first semiconductor chip by at least one chip through via, wherein the second semiconductor chip includes a first unit bank group including at least one first upper bank group and at least one first lower bank group, a second unit bank group including at least one second upper bank group and at least one second lower bank group, and a data path selector configured to electrically connect one among the first and second upper bank groups and the first and second lower bank groups with the chip through via.

Abstract: A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements.

Abstract: An output circuit includes first and second output drivers. The first output driver is configured to transfer a first data signal directly to an output pad in synchronization with a clock signal. The second output driver is configured to transfer a second data signal directly to the output pad in synchronization with an inversion clock signal. The clock signal and the inversion clock enable multiplexing of the first data signal and the second data signal to provide a multiplexed output data signal.

Abstract: Systems and methods are provided for a random access memory controller. A random access memory controller includes a column multiplexer and sense amplifier pair, where the column multiplexer and sense amplifier pair includes a column multiplexer and a sense amplifier that are configured to utilize common circuitry. The common circuitry is shared between the column multiplexer and the sense amplifier so that the memory controller includes a single instance of the common circuitry for the column multiplexer and sense amplifier pair. The common circuitry includes a common pre-charge circuit, a common equalizer, or a common keeper circuit.

Abstract: A hierarchical memory architecture includes an array of memory sub-arrays, each of which includes an array of memory cells. Each sub-array is supported by local wordlines, local column-select lines, and bitlines. The local wordlines are controlled using main wordlines that extend past multiple sub-arrays in a direction parallel to a first axis, whereas the local column-select lines are controlled using main column-select lines that extend between sub-arrays in a direction perpendicular to the first axis. At the direction of signals presented on the local wordlines and column-select lines, subsets of the bitlines in each sub-array are connected to main data lines that extend over a plurality of the sub-arrays in parallel with the second axis. Some embodiments include redundant data resources that are selected based on a decoding of row addresses.

Abstract: A memory device comprises a nonvolatile memory device and a controller. The nonvolatile memory comprises a first memory area comprising single-bit memory cells and a second memory area comprising multi-bit memory cells. The controller is configured to receive a first unit of write data, determine a type of the first unit of write data, and based on the type, temporarily store the first unit of write data in the first memory area and subsequently migrate the temporarily stored first unit of write data to the second memory area or to directly store the first unit of write data in the second memory area, and is further configured to migrate a second unit of write data temporarily stored in the first memory area to the second memory area where the first unit of write data is directly stored in the second memory area.

Abstract: A semiconductor memory device includes a memory bank configured to store data, a buffering unit including a plurality of buffers, which are disposed to extend to a X-axis of the memory bank to store data transferred from the memory bank, a plurality of data transmission lines configured to transfer the data stored in the plurality of buffers, and a path multiplexing unit configured to select one of a plurality of data transmission paths in response to addresses and transfer the data through the selected data transmission path.

Abstract: A memory includes a redundant sense amplifier and a plurality of sense amplifier pairs. Each sense amplifier pair includes a first sense amplifier and a second sense amplifier. Each sense amplifier pair drives a common load line. The memory is configured to implement column redundancy using a single redundant sense amplifier without requiring local read lines for each sense amplifier.

Abstract: A semiconductor memory device includes a data transmission unit configured to transmit first input data to only a first global line driver or to the first global line driver and a second global line driver in response to a test signal, and a transmission element configured to transmit second input data only to the second global line driver in response to the test signal.

Abstract: A nonvolatile programmable logic switch according to an embodiment includes first and second cells, each of the first and second cells including: a first memory having a first to third terminals, the third terminal being receiving a control signal; a first transistor connected at one of source/drain to the second terminal; and a second transistor connected at a gate to the other of the source/drain of the first transistor, the third terminal of the first memory in the first cell and the third terminal of the first memory in the second cell being connected in common. When conducting writing into the first memory in the first cell, the third terminal is connected to a write power supply generating a write voltage, the first terminals in the first and second cells are connected to a ground power supply and a write inhibit power supply generating a write inhibit voltage respectively.

Abstract: A semiconductor system including a semiconductor integrated circuit or a semiconductor chip, and a method of driving the semiconductor system are described. The semiconductor integrated circuit includes a plurality of semiconductor chips, at least one first chip through via suitable for penetrating through the plurality of semiconductor chips and interfacing a source ID code between the plurality of semiconductor chips, a plurality of second chip through vias suitable for penetrating through the plurality of semiconductor chips and interfacing a plurality of chip selection signals between the plurality of semiconductor chips, wherein the semiconductor chip uses one of chip selection signals as an internal chip selection signal in response to a chip ID code by selecting one of a unique ID code for the semiconductor chip and an alternative ID code for a preset semiconductor chip when the semiconductor chip fails.

Abstract: An integrated driver system is disclosed. The driver system includes decoding logic and a driver portion. The decoding logic is configured to receive select signals and data signals. The driver portion is configured to generate driver signals according to the decoded signals.

Abstract: Described herein are embodiments of selectively setting a memory command clock as a memory buffer reference clock. An apparatus configured for setting a memory command clock as a memory buffer reference clock may include a memory buffer configured to interface between a host and memory, and reference clock selection logic configured to selectively set a memory command clock as a memory buffer reference clock. Other embodiments may be described and/or claimed.

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.