Abstract: Methods and apparatuses of providing word line voltages are disclosed. An example method includes: activating and deactivating a word line. Activating the word line includes: rendering the first, second and third transistors conductive, non-conductive and non-conductive, respectively, wherein the first transistor is rendered conductive by supplying a gate of the first transistor with a first voltage; and supplying the first node with an active voltage. Deactivating the word line includes: changing a voltage of the first node from the active voltage to an inactive voltage; changing a voltage of the gate of the first transistor from the first voltage to a second voltage, wherein the first transistor is kept conductive by the second voltage; rendering the third transistor conductive during the gate of the first transistor being at the second voltage; and rendering the first and second transistors non-conductive and conductive, respectively, after the third transistor has been rendered conductive.

Abstract: Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. The first die receives a first command including first command information and second command information provided after the first command information. The first die changes an order of providing the first command information and the second command information and provides a second command to a second die, the second command including the second command information and the first command information provided after the second command information in the changed order. The first command information is related to a command function and the second command information is related to a destination of the command function.

Abstract: Systems, methods and fabrication processes relating to memory devices involving data bus inversion are disclosed. According to one illustrative implementation, a memory device may comprise a memory core, circuitry that receives a data bus inversion (OBI) bit associated with a data signal as input directly, without transmission through OBI logic associated with an input buffer, and circuitry that stores the OBI bit into the memory core, reads the OBI bit from the memory core, and provides the OBI bit as output. In further implementations, memory devices herein may store and process the OBI bit on an internal data bus as a regular data bit.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Abstract: A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, and a sense amplifier connected to the memory cell through the bit line. The sense amplifier includes a sense node connected to the bit line, a first capacitive element connected to the sense node, and a static latch circuit connected to the sense node and retains data of the sense node.

Abstract: A transpose accessing memory device is provided, the global word-lines configured to be selected as horizontal word-lines in a row access mode in that at least one row of the memory array is selected to be access, and the corresponding local I/O circuit is configured to guide signals of the local bit-lines coupled to the selected SRAM memory cells to the corresponding horizontal global bit-lines in response to select signals from the global word-lines, and the global word-lines configured to be selected as vertical word-lines in a column access mode in that at least one column of the memory array is selected to be access, and the corresponding local I/O circuit is configured to guide signals of the local bit-lines coupled to the selected SRAM memory cells to the corresponding vertical global bit-lines in response to select signals from the global word-lines.

Abstract: An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.

Abstract: A method of mapping target design memory blocks to embedded memory blocks in a semiconductor device of an embedded system is disclosed. The method includes categorizing a plurality target design memory blocks based on memory operation patterns into one of an overlapping category and a non-overlapping category; identifying a set of target design memory blocks that satisfy capacity criteria of a single embedded memory block in the semiconductor device, each target design memory block in the set is identified from either the overlapping category or the non-overlapping category; designing semiconductor device components to be created on the semiconductor device based on one of the overlapping category and the non-overlapping category, which the set of target design memory blocks is associated with; implementing the set of target design memory blocks and the semiconductor device components onto the single embedded memory block of the semiconductor device.

Abstract: A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.

Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Abstract: A memory device with reduced latency is provided. The memory device includes a burst read mode with a burst length of M0 (M0 is an integer greater than or equal to 2), a global sense amplifier array, M0 local memory cell arrays <1> to <M0>, and M0 local sense amplifier arrays <1> to <M0>. A memory cell includes a transistor and a capacitor. A local memory cell array <J> (J is an integer from 1 to M0) is stacked over a local sense amplifier array <J>. The local memory cell array <J> comprises M0 blocks <J_1> to <J_M0> differentiated by row, The local sense amplifier array <J> in an idle state retains the data of the block <J_J>. The block <J_J> is specified when the local memory cell array <J> is the first local memory cell array to be accessed in a burst read mode.

Abstract: A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. In one aspect, each stack of components has individual components factorizing out their common subcomponents that do not require parallel usage and sharing them as a common component serially. Other aspects, include serial bus communication between the different components, compact I/O enabled data latches associated with the multiple read/write circuits, and an architecture that allows reading and programming of a contiguous row of memory cells or a segment thereof. The various aspects combined to achieve high performance, high accuracy and high compactness.

Abstract: Concepts and technologies are described herein for cache management. In accordance with the concepts and technologies disclosed herein, the server computer can be configured to communicate with a client device configured to execute a cache module to maintain a cache storing data downloaded from and/or uploaded to the server computer by the client device. The server computer can be configured to receive requests for data stored at the server computer. The server computer can be configured to respond to the request with hashes that correspond to the requested data. The client device can search the cache for the hashes, obtain the data from the cache if the hashes are found, and/or download the data from the server computer if the hashes are not found. The client device also can be configured to update the cache upon uploading the data to the server computer.

Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: Memory systems may include a memory device with multiple dies, a first super block, and a second super block, the first super block including a first meta-page stored at a location on a die and the second super block including a second-meta page stored at a location on a die; and a controller suitable for reading the meta-pages in the super blocks, wherein the stored location of the first meta-page is staggered with respect to the stored location of the second meta-page such that the first meta-page and the second meta-page are read by the controller during a single read.

Abstract: An address translation device (ATD) can be used to translate a physical address of a memory line to a storage location within a main memory. The main memory can include multiple memory devices, each including at least one memory portion. Each of the memory portions can be contiguous and have a uniform size. The memory line can be stored within one of the memory portions. The ATD can include a data table structure. Consecutive rows of the data table structure can be configured such that each of the rows uniquely identifies one of the memory portions. The ATD can also include an index calculation unit configured to calculate a row index. The row index can be used to identify the row of the data table structure that identifies the memory portion that includes the storage location of the memory line.

Abstract: An address translation device (ATD) can be used to translate a physical address of a memory line to a storage location within a main memory. The main memory can include multiple memory devices, each including at least one memory portion. Each of the memory portions can be contiguous and have a uniform size. The memory line can be stored within one of the memory portions. The ATD can include a data table structure. Consecutive rows of the data table structure can be configured such that each of the rows uniquely identifies one of the memory portions. The ATD can also include an index calculation unit configured to calculate a row index. The row index can be used to identify the row of the data table structure that identifies the memory portion that includes the storage location of the memory line.

Abstract: A technique provides memory efficient caching of metadata managed by a volume layer of a storage input/output stack executing on one or more nodes of a cluster. Efficient caching of the metadata in a memory of a node may be realized through the use of a caching data structure, i.e., a page cache, configured to store a key-value pair, wherein the key is an extent key and the value is a metadata page containing the index entries. The page cache illustratively includes two data structures configured to maintain the properties of Least Recently Used (LRU) and Least Frequently Used (LFU) for the cache. The first data structure is a hash table that stores a dense tree metadata page (value) indexed by the extent key. The second data structure is a recycle queue that controls the metadata page stored in the hash table based on spatial and temporal locality of the page.

Abstract: In a method for populating an exact match lookup table in a network device, a lookup key to be stored in a database of the network device is determined. The database is distributed among two or more memory banks. At least based on a size of the lookup key, (i) a first memory bank from among the two or more memory banks, and (ii) a hash function from among a plurality of possible hash functions, are selected. A hash operation is performed on the lookup key using the selected hash function to compute a first hashed lookup key segment. The first hashed lookup key segment is stored in the selected first memory bank, and one or more hashed lookup key segments corresponding to the lookup key are stored in one or more subsequent memory banks of the two or more memory banks.

Abstract: A memory module uses dynamic data buffers for providing extended capacity for computing systems. The memory module comprises an external interface having a first set of data pins and a second set of data pins. The memory module includes a first set of memory chips and a second set of memory chips. The memory module includes a first registering clock driver to control the first set of memory chips and a second registering clock driver to control the second set of memory chips. The memory module further includes a first data buffer to connect the first set of memory chips to the first set of data pins and a second data buffer to connect the second set of memory chips to the second set of data pins.

Abstract: A memory driver, a method of driving a command bus for a synchronous dual data rate (sDDR) memory and a memory controller for controlling dynamic random-access memory (DRAM). In one embodiment, the memory driver includes: (1) pull-up and pull-down transistors couplable to a command bus of a memory controller and operable in 1N and 2N timing modes and (2) gear down offset circuitry coupled to the pull-up transistor and operable to offset the command bus when transitioning out of the 1N timing mode and increase an extent and duration of 1-0-1 transitions on the command bus.

Abstract: Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled to the first and a second control line that drives a first and a second control signal toward first or second voltage levels. The integrated circuit may include a shaper circuitry coupled to the control lines that includes a first clamping transistor that couples the first control line to a timed supply node in response to the driving of the second control signal toward the first voltage. The integrated circuit may include a timing circuitry coupled to the first shaper circuitry that includes a header transistor that couples the timed supply node to a voltage supply source.

Abstract: A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of the plurality of mode registers. The set of global wiring lines may include a first global wiring line to transmit data to each of the plurality of mode registers, a second global wiring line to transmit an address signal to each of the plurality of mode registers, a third global wiring line to transmit a read command signal to each of the plurality of mode registers, and a fourth global wiring line to transmit a write command signal to each of the plurality of mode registers.

Abstract: The present invention provides a storage device adopting a semiconductor device as a storage media having a nonvolatile property and must be erased for writing data, wherein the device divides and manages a logical storage space provided to a higher level device in logical page units, and manages a virtual address space which is a linear address space to which multiple physical blocks of the semiconductor device are mapped. The storage device uses a page mapping table managing a correspondence between a logical page and an address in the virtual address space, and a virtual address configuration information managing a correspondence between an area in the virtual address space and a physical block, in order to manage the correspondence between the respective logical pages and storage areas of the semiconductor device.

Abstract: Names of finishing-job storage folders stored within a portable electronic memory apparatus are limited to only names of known finishing workflows. Connection of the portable electronic memory apparatus to a printing system is automatically detected, and for each print job, the printing system is automatically instructed to perform a finishing workflow that corresponds to the name of the finishing-job storage folder in which the print job is located. The printing system is required to evaluate whether the printing system can perform the finishing workflow, based on the status of the finishing components. Thus, the printing system is required either to perform the finishing workflow (if the printing system can perform the finishing workflow) or provide a menu on a user interface of the printing system (if the printing system cannot perform the finishing workflow).

Abstract: According to one embodiment, a semiconductor memory device includes: a first insulating layer; a global bit line and a reference bit line provided on the first insulating layer; a second insulating layer provided on the global bit line and the reference bit line; a select gate line provided on the second insulating layer; a first transistor provided on the global bit line; a local bit line coupled to the first transistor; first and second memory cells; and a sense amplifier. The global bit line and the reference bit line three-dimensionally intersect the select gate line via the second insulating layer.

Abstract: To handle different Quality of Service (QoS) requirements, there may be a need for supporting multiple parallel data paths to exchange data between two or more peer entities of a data communication system. Each data path between the peer entities may be characterized by various QoS parameters such as priority, delay, jitter, data rate, etc. A communication system may allocate transmission resources for each data path based on the QoS parameters associated with them. Since the allocated transmission resources may not be always sufficient to send all the pending data from an application, the data packets may be segmented or packed depending on the available transmission resources. In such a case, doing segmentation may lead to inefficient usage of the transmission resources. A method and apparatus are disclosed that avoid such segmentation and allocates the transmission resources to the other active data paths which can better utilize the transmission resources.

Abstract: A semiconductor memory apparatus, including a first mat which includes a first bit line and a first word line and a second mat which includes a second bit line and a second word line, includes a first bit line driving circuit configured to enable the first bit line in response to a first bit line select signal and a first machine bit line select signal; a second bit line driving circuit configured to enable the second bit line in response to a second bit line select signal and a second machine bit line select signal; a column-related decoding circuit configured to selectively enable the first and second bit line select signals in response to a column address; and a state machine configured to selectively enable the first and second machine bit line select signals in response to the column address.

Abstract: A memory architecture includes K first control lines, M groups of second control lines and a memory cell array. K and M are positive integers. Each group of second control lines includes at least one second control line. The memory cell array includes M memory banks. Each memory bank is coupled to the K first control lines. The M memory banks are selected according to M bank select signals respectively so as to receive a shared set of first control signals through the K first control lines. The M memory banks are coupled to the M groups of second control lines respectively, and receive independent M sets of second control signals through the M groups of second control lines respectively. Each memory bank performs one of a column select operation and a sense amplification operation according to the set of first control signals and a set of second control signals.

Abstract: To provide an electronic device capable of improving a signal quality, the electronic device includes a semiconductor memory device, a semiconductor device configured to access data stored in the semiconductor memory device, and a wiring substrate on which the semiconductor memory device and the semiconductor device are mounted. The wiring substrate includes first and second data wirings electrically connecting the semiconductor device with each first and second data terminal of the semiconductor memory device through first and second wiring layers. The first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer, and the first data terminal is located farther from the semiconductor device than the second data terminal.

Abstract: A semiconductor device may be provided. The semiconductor device may include an address input circuit and a target address generation circuit. The address input circuit may be configured to latch a bank address and an address to generate a bank active signal and a latch address based on the execution of an active operation. The target address generation circuit may be configured to generate the latch address as a target address.

Abstract: A storage control device includes a first processor, a second processor, and transfer units for transferring data from the first processor to the second processor. The first processor receives a write request for writing first data from a first device and sequentially transmits the first data, additional data, and pieces of dummy data. A number of the pieces is same as a number of the transfer units. The first processor notifies the first device of completion of the writing upon receiving an acknowledgement for a last transmitted piece of dummy data. Each transfer unit includes a third processor. The third processor receives the additional data from a preceding processor, and transmits an acknowledgement to the preceding processor upon storing the received additional data. The third processor receives one piece of dummy data from the preceding processor, and transmits an acknowledgement to the preceding processor upon storing the one piece.

Abstract: A device includes a first data terminal, a second data terminal, a first switching buffer coupled between a data node and the first data terminal and a second switching buffer coupled between the data node and the second data terminal. The first switching buffer and the second switching buffer are arranged such that a distance between the first switching buffer and the second data terminal is shorter than a distance between the second switching buffer and the second data terminal and that a distance between the first switching buffer and the first data terminal is shorter than a distance between the second switching buffer and the first data terminal.

Abstract: To perform refresh without saving data, and prevent corruption of data in non-volatile memories. A number-of-write-operations information holding unit holds number-of-write-operations information, which is the number of write operations of a non-volatile memory to which access is made in units of pages which are divided by a page size. A determination unit determines whether or not refresh, which is reversing of values of all memory cells constituting the pages, is necessary on the basis of the held number-of-write-operations information. A write control unit further performs the refresh in addition to writing when the refresh is necessary on the basis of a result of the determination at a time of the writing with respect to the pages.

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a first power supply having a first fixed voltage, a second power supply having a second fixed voltage, a plurality of circuits coupled to the first power supply via a first switch and the second power supply via a second switch, and a power control circuit configured to selectively enable one of the first switch and the second switch responsive to power demand information.

Abstract: A memory device includes a memory cell array, a plurality of bit lines, and a plurality of page buffers including a plurality of cache latches, exchanging data with the memory cell array through the plurality of bit lines, wherein the plurality of cache latches are arranged in a column direction in parallel with the plurality of bit lines and a row direction perpendicular to the plurality of bit lines, and have a two-dimensional arrangement of M stages in the column direction, where M is a positive integer not corresponding to 2L and L is zero or a natural number.

Abstract: In a method for performing an exact match lookup in a network device, a network packet is received at the network device. A lookup key for the network packet is determined at least based on data included in a header of the received network packet. A hash function is selected, from among a plurality of possible hash functions, at least based on a size of the lookup key, and a hash operation is performed on the lookup key using the selected hash function to compute a hashed lookup key segment. A database is queried using the hashed lookup key segment to extract a value exactly corresponding to the lookup key.

Abstract: The invention provides a flash memory which may effectively protect information with a high security level. A flash memory includes a setting part. When the setting part is inputted a specific command, the setting part sets up specific address information to a nonvolatile configuration register, and sets up specific data in a hidden storage region. The flash memory also includes: a comparing part, which compares inputted address information and the specific address information during a reading operation; and a control part, which reads specific data set in the storage region and erases a specific address when two address information are consistent, and reads data stored in a memory array according to the inputted address information when two address information are inconsistent.

Abstract: An Integrated Circuit device, including: first transistors and second transistors, where the first transistors and the second transistors each include a single crystal channel, where at least one of the second transistors overlays at least one of the first transistors with less than 1 micron distance apart, and where at least one of the second transistors is a dopant segregated schottky barrier transistor.

Abstract: A shared command/address (C/A) bus for memory devices in a multi-channel configuration can enable reducing the number of pins and signal lines in a memory subsystem. In one embodiment, a memory controller includes hardware logic to generate commands to access a plurality of memory devices via a plurality of channels and input/output (I/O) circuitry to transmit command/address (C/A) information for the commands to the plurality of memory devices over a single C/A bus for the plurality of channels. In one embodiment, double-speed strobe signal lines can also enable reducing the number of pins and signal lines in a memory subsystem.

Abstract: Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

Abstract: A memory device may include: a plurality of cell mats arranged in a plurality of rows and columns; a plurality of first drivers, each first driver being disposed on a left side of a corresponding cell mat of the plurality of cell mats and configured to drive a first sub-word line of the corresponding cell mat; and a plurality of second drivers, each second driver being disposed on a right side of the corresponding cell mat of the plurality of cell mats and configured to drive a second sub-word line of the corresponding cell mat, wherein, during an active operation, among the plurality of cell mats, sub-word lines of cell mats disposed in odd-numbered columns or sub-word lines of cell mats disposed in even-numbered columns are selectively activated.

Abstract: Main memory access from a CPU is reduced, and thus an increase in speed of data processing is achieved. Provided is a reconfigurable device (20) connected to a main memory (600). The reconfigurable device (20) includes a plurality of logic sections connected to each other by an address line or a data line. Each of the logic sections includes a plurality of address lines, a plurality of data lines, an address decoder that decodes addresses input from part of the plurality of address lines, and a memory cell array unit that includes a plurality of memory cells specified by decode lines of the address decoder, and outputs data read from the specified memory cells to the data lines. An address line of the memory cell array unit is connected to a data output line (RD1) of the main memory.

Abstract: Example implementations relate to using an alternative memory (AltMem) to reduce read latency of a memory module having a dynamic random-access memory (DRAM). In example implementations, write data may be written to the DRAM and to the AltMem. A read command may be issued to the AltMem if a DRAM read latency time for executing the read command is greater than an AltMem read latency time for executing the read command. Data read from the AltMem in response to the read command may be received.

Abstract: Method, apparatus, and system for improving semiconductor device writeability at row/bit level through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage. By virtue of BTI, application of the first array supply voltage may lead to improved writeability of one or more cells of the device.

Abstract: A memory module uses dynamic data buffers for providing extended capacity for computing systems. The memory module comprises an external interface having a first set of data pins and a second set of data pins. The memory module includes a first set of memory chips and a second set of memory chips. The memory module includes a first registering clock driver to control the first set of memory chips and a second registering clock driver to control the second set of memory chips. The memory module further includes a first data buffer to connect the first set of memory chips to the first set of data pins and a second data buffer to connect the second set of memory chips to the second set of data pins.

Abstract: Provided are a memory device, a memory system, and a method of operating the memory device. A method of operating a memory device including a plurality of random access memory (RAM) chips includes inputting a read command, reading a plurality of pieces of block data including first block data corresponding to the read command from each of the plurality of RAM chips, generating two-dimensional (2D) data by combining the plurality of pieces of block data read from each of the RAM chips, and processing the read command by using the 2D data.

Abstract: A method for operating a fieldbus protocol capable field device, wherein the fieldbus protocol includes at least one command, which serves, depending on a value of an auxiliary variable, for performing a first function, respectively for performing a second function, of field device, wherein the first and second functions differ from one another.