Abstract: Embodiments include herein are directed towards a dynamic random access memory system. Embodiments may include a command queue that is configured to hold all commands that are currently selectable for bank operation and execution. Embodiments may further include bank logic operatively connected with the command queue. The bank logic may include a bank management module and a plurality of bank slices, wherein each of the plurality of bank slices is an independent, re-assignable bank tracking module.

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

Abstract: An electronic device may include a main circuit including multiple sub-circuits powered by a direct-current (DC) power supply circuit. The main circuit has a main circuit current demand being a time-varying demand for a DC voltage-regulated supply current being a function of a number of the sub-circuits being active. The DC power supply circuit may include multiple DC voltage regulators to provide the main circuit with the supply current and a command decoding and power management circuit to control enablement of the voltage regulators. The command decoding and power management circuit may be configured to detect an instant value of the main circuit current demand and to selectively enable one or more of the voltage regulators based on the detected instant value.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of SRAM cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies.

Abstract: The present disclosure relates to a method for generating a pattern of a memory, a computer-readable storage medium and a computer device, the method for generating a pattern of a memory includes: presetting mapping relationships between a physical address and a row, a column and a bank, and determining bits of the physical address corresponding to the row, the column and the bank; taking a preset number of values as setting data, the preset number being the same as a number of signal address lines in the memory; obtaining a command truth value table, which is used to define relationships between bits of the physical address and commands; determining values of the row, the column and the bank based on the command truth value table and the setting data; generating the pattern based on the values of the row, the column and the bank and the mapping relationships.

Abstract: A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.

Abstract: An apparatus includes a clock terminal configured to receive an external clock signal, a clock generator configured to generate an internal clock signal in response to the external clock signal, first and second output circuits each coupled to the clock generator, a first clock line coupled between the clock generator and the first output circuit, and the second clock line coupled between the clock generator and the second output circuit. The first clock line represents a first capacitance and a first resistance while the second clock line represents a second capacitance and a second resistance. A first value defined as the product of the first capacitance and the first resistance is substantially equal to a second value defined as the product of the second capacitance and the second resistance.

Abstract: A system includes a global generator and local generators. The global generator is coupled to a memory array, and is configured to generate global signals, according to a number of a computational output of the memory array. The local generators are coupled to the global generator and the memory array, and are configured to generate local signals, according to the global signals. Each one of the local generators includes a first reference circuit and a local current mirror. The first reference circuit is coupled to the global generator, and is configured to generate a first reference signal at a node, in response to a first global signal of the global signals. The local current mirror is coupled to the first reference circuit at the node, and is configured to generate the local signals, by mirroring a summation of at least one signal at the node.

Abstract: A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

Abstract: An integrated circuit (IC) includes a plurality of volatile memory (VM) blocks, and a power gate control circuit configured to control power gating for each VM block of a plurality of VM blocks. The IC includes a power mode controller circuit configured to select a power mode, and in response to selecting a retention mode as the power mode, the power mode controller circuit gates a supply voltage from each block of a selected subset of the plurality of VM blocks and allows a retention voltage to power each VM block of a remaining subset of the plurality of VM blocks outside the selected subset. The IC includes a voltage controller circuit configured to determine a voltage level of the retention voltage based on a minimum retention voltage required for each VM block of the remaining subset.

Abstract: In various embodiments, a parallel processor includes a parallel processor module implemented within a first die and a memory system module implemented within a second die. The memory system module is coupled to the parallel processor module via an on-package link. The parallel processor module includes multiple processor cores and multiple cache memories. The memory system module includes a memory controller for accessing a DRAM. Advantageously, the performance of the parallel processor module can be effectively tailored for memory bandwidth demands that typify one or more application domains via the memory system module.

Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.

Abstract: A method and apparatus for video processing on a data storage device. A chip bound architecture includes a CMOS coupled to one or more NAND die, the CMOS including one or more processors, memories, and error correction code (ECC) engines capable of processing video data. According to certain embodiments, macroblocks are correlated between two I-frames, including motion vectors to define different locations of correlated macroblocks. A P-frame may be determined from a previous I-frame and its correlated macroblocks and motion vectors, while a B-frame may be determined from two or more adjacent I-frames with concomitant macroblocks and motion vectors, as well as P-frames associated with an adjacent I-frame.

Abstract: A memory device includes a system block for storing test information and includes a data block including memory cells connected to a plurality of low bank column lines and a plurality of high bank column lines. The memory device also includes a column repair controller configured to detect, based on the test information, a concurrent repair column line in which a low bank column line among the plurality of low bank column lines and a high bank column line the plurality of high bank column lines corresponding to the same column address are concurrent repaired.

Abstract: A memory device includes: a first circuit; a second circuit; and an adaptive body bias generator configured to receive frequency detection information or temperature detection information, to apply a first forward body bias or a first reverse body bias to the first circuit in response to the frequency detection information or the temperature detection information, and to apply a second forward body bias or a second reverse body bias to the second circuit in response to the frequency detection information or the temperature detection information.

Abstract: Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

Abstract: A semiconductor device includes a cell area in which a plurality of memory cells are arranged in an array structure, and a peripheral area in which circuits configured to drive the memory cells are arranged, the peripheral area being next to the cell area. The cell area is divided into a plurality of banks, and the plurality of banks comprise first banks having a base size and second banks having a size of 1/(2*n) (wherein n is an integer greater than or equal to 1) of the base size. The plurality of banks are arranged in a first direction and a second direction perpendicular to the first direction, and the semiconductor device has a shape of a rectangular chip which is elongated in the second direction.

Abstract: A DRAM memory includes: a substrate; a plurality of memory banks arranged in rows and columns on the substrate, each memory bank is divided into three memory blocks in the column direction. Each memory block has a number of memory cells arranged in rows and columns. Dividing each memory bank into three memory blocks in the column direction shortens the length of the memory bank in the row direction, as each memory bank has a certain capacity, so a large drive is no longer required. In addition, the distance from the control circuit and the data transmission circuit to the corresponding memory cell in the memory array in each memory bank will be shorter too, reducing parasitic resistance and parasitic capacitance generated from the data transmission circuit. As a result, the data transmission rate and data transmission accuracy are improved. The overall power consumption is reduced.

Abstract: A semiconductor memory device includes a memory cell array, a bit-line switch, a block switch, and a column decoder. The memory cell array includes memory blocks coupled to at least one word-line and each of the memory blocks includes memory cells. The bit-line switch is connected between a first half local input/output (I/O) line of a first memory block and a second half local I/O line of the first memory block. The block switch is connected between the second half local I/O line of the first memory block and a first half local I/O line of a second memory block adjacent to the first memory block. The column decoder includes a repair circuit that controls connections by applying a first switching control signal to the bit-line switch and a second switching control signal to the block switch.

Abstract: A chip includes a processor, a memory, and a storage controller of the memory. There is an access path between the processor and the storage controller, and the processor reads data from or writes data into the memory by using the storage controller through the access path. The chip further includes a shielding circuit. The shielding circuit is configured to shield a signal on the access path when the processor is powered off.

Abstract: A memory system includes a memory device including a plurality of memory units capable of inputting or outputting data individually, and a controller coupled with the plurality of memory units via a plurality of data paths. The controller is configured to perform a correlation operation on two or more read requests among a plurality of read requests input from an external device, so that the plurality of memory units output plural pieces of data corresponding to the plurality of read requests via the plurality of data paths based on an interleaving manner. The controller is configured to determine whether to load map data associated with the plurality of read requests before a count of the plurality of read requests reaches a threshold, to divide the plurality of read request into two groups based on whether to load the map data, and to perform the correlation operation per group.

Abstract: A volatile memory device includes: a first sense amplifier connected to a first memory cell through a first bit line, and configured to sense 2-bit data stored in the first memory cell; a second sense amplifier connected to a second memory cell through a second bit line, and configured to sense 2-bit data stored in the second memory cell, the second bit line having a length greater than a length of the first bit line; and a driving voltage supply circuit configured to supply a first driving voltage to the first sense amplifier, and supply a second driving voltage to the second sense amplifier, the second driving voltage having a voltage level different from a voltage level of the first driving voltage.

Abstract: A semiconductor integrated circuit device includes a first power wiring that is formed on a semiconductor substrate and that extends in a first direction, a second power wiring that extends in the first direction such that the second power wiring is separated from the first power wiring, a first diffusion layer that is used for a p-channel type MOSFET and that is formed in a region between the first power wiring and the second power wiring, a second diffusion layer that is used for an n-channel type MOSFET and that is formed on a side of the second power wiring with respect to the first diffusion layer in the region between the first power wiring and the second power wiring, a first gate electrode that extends in a second direction perpendicular to the first direction and that straddles the first diffusion layer, a second gate electrode that extends in the second direction and that straddles the second diffusion layer, and a third diffusion layer for backgates that is formed below at least one of the first po

Abstract: A three-dimensional (3D) storage circuit includes two or more tiers of semiconductor dies, and a storage array of bitcells distributed on the two or more tiers to form a plurality of storage subarrays. One of the storage subarrays is arranged on a respective one of the tiers. Row and column replica/dummy tracking cells are arranged on each of the tiers. A timing circuit is coupled to the tracking cells of each of the tiers. In response to receipt of tier-specific trim bits for each of the tiers, the timing circuit independently controls a timing and/or voltage state of each of the tiers during an access operation of the 3D storage circuit to account for process and/or thermal variation between tiers of the 3D storage circuit.

Abstract: Systems and methods are provided to perform fine-grained memory accesses using a memory controller. The memory controller can access elements stored in memory across multiple dimensions of a matrix. The memory controller can perform accesses to non-contiguous memory locations by skipping zero or more elements across any dimension of the matrix.

Abstract: A method of operating a memory device is disclosed. A method may include generating a first control signal to activate a first number of main input/output (MIO) lines associated with a first data terminal region of a memory bank at a first time. The method may also include generating a second control signal to activate a second number of MIO lines associated with a second data terminal region of the memory bank at a second, subsequent time. Further, the method may include resetting each of the first control signal and the second control signal in response to a command.

Abstract: A semiconductor device includes an operation flag generation circuit configured to generate an operation flag at a time when a flag period elapses from a time when an internal setting signal is generated to perform a write operation accompanied by an auto-precharge operation; and an auto-precharge pulse generation circuit configured to generate an auto-precharge pulse by shifting the operation flag by a pulse generation period set by a period code based on divided clocks generated by dividing an internal clock.

Abstract: Some embodiments include an integrated assembly having a primary access transistor. The primary access transistor has a first source/drain region and a second source/drain region. The first and second source/drain regions are coupled to one another when the primary access transistor is in an ON mode, and are not coupled to one another when the primary access transistor is in an OFF mode. A charge-storage device is coupled with the first source/drain region. A digit line is coupled with the second source/drain region through a secondary access device. The secondary access device has an ON mode and an OFF mode. The digit line is coupled with the charge-storage device only when both the primary access transistor and the secondary access device are in their respective ON modes.

Abstract: A SRAM system having an address scheme and/or wire control layout. By preferentially accessing a defined address range mapped to SRAM array blocks located near a controller, significant power savings can be realized. In one embodiment, the address scheme determines a range physically closer to a central control location. In another embodiment, the wire control layout reduces number and length of active wires, further reducing power consumption.

Abstract: Various implementations described herein refer to an integrated circuit having a memory cell array with a first number of rows and a second number of rows. The integrated circuit may include a first pre-decoder that receives a row address and selects a first row from the first number of rows based on the row address. The integrated circuit may include a second pre-decoder that receives the row address from the first pre-decoder and selects a second row from the second number of rows based on the row address received from the first pre-decoder. The integrated circuit may include a single row decoder that receives the row address and selects either the first row or the second row based on a row selection bit from the row address.

Abstract: A sense amplifier can be formed outside of/horizontally adjacent to an array of vertically stacked tiers of memory cells. Memory cells can be sensed via multiplexors formed under the array that can operate to couple vertical sense lines (to which the memory cells are coupled) to horizontal sense lines (to which the sense amplifier is coupled).

Abstract: A method for selectively inverting a word to be written to a memory is provided. The memory includes memory cells, each memory cell allowing at least two values associated with at least one bit to be stored, the decision as to whether to invert a word being made depending on a number of vulnerable values, which number is determined on the basis of the data bits, of the inversion bit and of uneven check bits.

Abstract: A memory system includes a memory device including a plane including a plurality of memory blocks, each memory block including a plurality of memory cells, each memory cell capable of storing multi-bit data, and a controller configured to determine that a second memory block is a candidate block when an issue-triggering operation is performed for a first memory block, adjust levels of read voltages when receiving a read command for data stored in the second memory block determined as the candidate block, and control the memory device to supply adjusted levels of the read voltages to the second memory block to perform a read operation corresponding to the read command. The second memory block and the first memory block are included in the same plane. The issue-triggering operation includes either a program operation or an erase operation.

Abstract: A pseudo static memory device includes multiple memories, an arbiter and a controller. The memories respectively generate multiple self-refresh request signals. Each of the self-refresh request signals indicates a time period for performing self-refresh operation of corresponding memory. The arbiter receives the self-refresh request signals and generates a latency synchronize flag during the memories being enabled. The controller decides an accessing latency for accessing the memories during an accessing operation according to the latency synchronize flag.

Abstract: A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.

Abstract: A memory system is provided. In the memory system, a memory controller transmits a write enable signal and a data strobe signal to a flash memory device, a command or an address is transmitted at a rising edge or a falling edge of the write enable signal through a data line in a single data rate (SDR) scheme, and input data is transmitted at each of a rising edge and a falling edge of the data strobe signal through the data line in a double data rate (DDR) scheme. The memory controller includes a parity signal generation unit configured to receive the write enable signal transmitted in the DDR scheme and output a parity signal by generating a first parity bit for the input data. The flash memory device includes a bit error detection unit configured to receive the parity signal output from the memory controller, generate a second parity bit for the input data received by the flash memory device, and determine whether a bit error has occurred to the input data by performing a parity check.

Abstract: A semiconductor memory device, and a method of operating the semiconductor memory device, includes a memory cell array including a plurality of normal memory blocks and at least one system block, and a peripheral circuit configured to perform a program operation, a read operation, or an erase operation on the plurality of normal memory blocks or the at least one system block, wherein a data storage capacity of the at least one system block is less than a data storage capacity of each of the plurality of normal memory blocks.

Abstract: A nonvolatile memory device includes a memory cell region and a peripheral circuit region. The memory cell region includes a memory block, and the peripheral circuit region includes a control circuit. The memory cell region includes a first metal pad. The peripheral circuit region includes a second metal pad and is vertically connected to the memory cell region by the first metal pad and the second metal pad. The memory block includes a plurality of memory cells disposed in a vertical direction. The control circuit determines whether a data erase characteristic for the memory block is degraded for each predetermined cycle of data erase operation, and performs a data erase operation by changing a level of a voltage applied to selection transistors for selecting the memory block as an erase target block when it is determined that the data erase characteristic is degraded.

Abstract: A semiconductor device includes a first chip, divided into a plurality of regions, including a plurality of first pads and a plurality of first test pads in each of the plurality of regions; and a second chip including a plurality of second pads corresponding to the plurality of first pads and a plurality of second test pads corresponding to the plurality of first test pads, and bonded onto the first chip such that the plurality of second pads are coupled to the plurality of first pads. The second chip includes a voltage generation circuit linked to the plurality of second pads, that provides a compensated voltage to the plurality of second pads for each of the plurality of regions, based on a voltage drop value for each region due to a contact resistance between the plurality of first test pads and the plurality of second test pads.

Abstract: An API selection system that selects an API (Application Programming Interfaces) includes an API repository that accumulates an API in association with a functional requirement of the API, a save processing unit that receives, from an application developer, an input of an API request definition that defines the functional requirement and a non-functional requirement required for an API with which an application developed by the application developer is linked and saves the input in a storage unit, and a candidate API extraction processing unit that executes a candidate API extraction process of extracting, from the API repository, a plurality of candidate APIs having a functional requirement which matches or is similar to a functional requirement of the API request definition saved in the storage unit by the save processing unit.

Abstract: A storage device includes a plurality of nonvolatile memory devices; and a controller connected in common to the plurality of nonvolatile memory devices through data lines, the controller being configured to detect first offset information by performing a first training operation with respect to a first nonvolatile memory device from among the plurality of nonvolatile memory devices, the controller being further configured to, based on the first offset information, perform a second training operation with respect to a second nonvolatile memory device from among the plurality of nonvolatile memory devices.

Abstract: A system includes a memory system comprising a memory module and a processor adapted to access the memory module using a memory controller that includes a controller having an input for receiving a power state change request signal and an output for providing memory operations, and a memory operation array comprising a plurality of entries. Each entry includes a plurality of encoded fields. The memory operation array is programmable to store different sequences of commands for particular types of memory of a plurality of types of memory in the plurality of entries that initiate entry into and exit from supported low power modes for the particular types of memory. The controller is responsive to an activation of the power state change request signal to access the memory operation array to fetch at least one entry, and to issue at least one memory operation indicated by the at least one entry.

Abstract: Techniques are described for maintaining a stable voltage difference in a memory device, for example, during a critical operation (e.g., a sense operation). The voltage difference to be maintained may be a read voltage across a memory cell or a difference associated with a reference voltage, among other examples. A component (e.g., a local capacitor) may be coupled, before the operation, with a node biased to a first voltage (e.g., a global reference voltage) to sample a voltage difference between the first voltage and a second voltage while the circuitry is relatively quiet (e.g., not noisy). The component may be decoupled from the node before the operation such that a node of the component (e.g., a capacitor) may be allowed to float during the operation. The voltage difference across the component may remain stable during variations in the second voltage and may provide a stable voltage difference during the operation.

Abstract: A semiconductor device includes an internal column control signal generation circuit, a bank address transfer circuit, and a first bank control circuit. The internal column control signal generation circuit generates a column control signal to output an internal column control signal. The bank address transfer circuit receives a bank address to generate an inverted bank address and outputs the bank address and the inverted bank address. The first bank control circuit generates a first bank active signal based on at least one of the bank address and the inverted bank address and latches the first bank active signal based on the internal column control signal to generate a first bank column control signal.

Abstract: A memory device includes a plurality of memory cells arranged in an array having a plurality of rows and a plurality of columns. A first word line is connected to a first plurality of the memory cells of a first row of the array, and a second word line is connected to a second plurality of the memory cells of the first row of the array. In some examples, the plurality of memory cells are arranged in or on a substrate, and the first word line is formed in a first layer of the substrate and the second word line is formed in a second layer of the substrate.

Abstract: A network device configured to perform scalable, in-network computations is described. The network device is configured to process pull requests and/or push requests from a plurality of endpoints connected to the network. A collective communication primitive from a particular endpoint can be received at a network device. The collective communication primitive is associated with a multicast region of a shared global address space and is mapped to a plurality of participating endpoints. The network device is configured to perform an in-network computation based on information received from the participating endpoints before forwarding a response to the collective communication primitive back to one or more of the participating endpoints. The endpoints can inject pull requests (e.g., load commands) and/or push requests (e.g., store commands) into the network. A multicast capability enables tasks, such as a reduction operation, to be offloaded to hardware in the network device.

Abstract: A method may include forming two vertical transport field effect transistors stacked one atop the other and separated by a resistive random access memory structure. The two vertical transport field effect transistors may include a source, a channel, and a drain, wherein a contact layer of the resistive random access memory structure functions as the drain of the two vertical transport field effect transistors. Forming the two vertical transport field effect transistors may further include forming a first source and a second source. The first source is a bottom source and the second source is a top source. The method may include forming a gate conductor layer surrounding the channel. The resistive random access memory structures may include faceted epitaxy defined by pointed tips. The pointed tips of the faceted epitaxy may extend vertically toward each other. The faceted epitaxy may be between the two vertical transport field effect transistors.

Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a reset signal, command/address signals and data. The second semiconductor device may be configured to enable a start signal and an oscillation signal based on the reset signal. The oscillation signal starts to oscillate in response to the reset signal.

Abstract: According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry; one or more core arrays, respective input/output (I/O) circuitry for each of the one or more core arrays, and control circuitry coupled to the first and second word-line decoder circuitries, the one or more core arrays, and the respective I/O circuitries. Also, one or more control signals, activated from one or more control signals generated in the control circuitry, may be configured to select corresponding one or more core arrays of the one or more core arrays.

Abstract: A FinFET gain cell includes a write port, read port and storage node. The write port includes at least one write FinFET transistor and has write word-line (WWL) and write bit-line (WBL) inputs. The read port includes at least one FinFET read transistor and has a read word-line (RWL) input and a read bit-line (RBL) output. The storage node stores a data level written from said WBL. The storage nodes includes a single layer interconnect which connects the write port output diffusion connection to the read port input gate connection. The height of the single layer interconnect at the write port output diffusion connection is different from the height of the single layer interconnect at the read port input gate connection.