Alternate Addressing (e.g., Even/odd) Patents (Class 365/230.04)
  • Patent number: 11468926
    Abstract: A memory system includes: a plurality of memory dies, and a controller selects a second read request, including at least a portion of a plurality of first read requests, so that the memory dies interleave and output data corresponding to the first read requests, and performs a correlation operation for the selected second read request, when the second read request is selected, the controller determines whether the correlation operation is performed or not before a time at which the second read request is selected, determines whether the correlation operation is successful or not, determines a pending credit in response to an operation state of the memory dies at the time at which the second read request is selected, and determines whether to perform the correlation operation or not for the second read request that is selected at the time at which the second read request is selected based on the pending credit.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: October 11, 2022
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 11392164
    Abstract: A signal receiving circuit is provided. The signal receiving circuit includes a receiving circuit, an adjustment circuit and a boundary detection circuit. The receiving circuit is configured to receive an input signal. The adjustment circuit is configured to adjust the input signal. The boundary detection circuit is configured to detect a first signal having a first data pattern in the input signal and a second signal having a second data pattern in the input signal. The boundary detection circuit is further configured to detect a gap value between a first signal boundary of the first signal and a second signal boundary of the second signal to reflect a status of the adjustment circuit.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: July 19, 2022
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Sheng-Wen Chen, Shih-Yang Sun, Zhen-Hong Hung
  • Patent number: 11069399
    Abstract: A memory device including a first memory cell array including first memory cells stacked vertically on a first memory cell array region of a top surface of a substrate; a second memory cell array including second memory cells stacked vertically on a second memory cell array region of the top surface; first word lines coupled to the first memory cells and including a subset of first word lines and remaining first word lines; second word lines coupled to the second memory cells and including a subset of second word lines and remaining second word lines; and a row decoder, including a plurality of merge pass transistors each commonly connected to a respective one of the subset of first word lines and a respective one of the subset of second word lines, disposed in a region of the top surface between the first and second cell array regions.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changbum Kim, Sunghoon Kim, Seungyeon Kim
  • Patent number: 10937476
    Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Toshiyuki Sato, Shinichi Miyatake, Satoshi Yamanaka
  • Patent number: 10877908
    Abstract: Systems, apparatuses, and methods related to an isolation circuit in a memory module are described. A dual-in line memory module (DIMM), for example, may include an isolation circuit to isolate components from one another in certain operating modes or phases of module operation. The isolation circuit may, for instance, isolate one integrated circuit (e.g., an electrically erasable read-only memory (EEPROM)) that includes serial presence detect (SPD) information from a controller (e.g., a field programmable gate array (FPGA)) if the controller is not energized. The isolation circuit may be employed in a non-volatile DIMM (NVDIMM), and an integrated circuit of the NVDIMM (e.g., an SPD EEPROM) may be isolated from an FPGA of the NVDIMM while the NVDIMM is de-energized. The isolation circuit may be employed in other examples to isolate or couple, or both, different components from or to one another.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventor: William A. Lendvay
  • Patent number: 10672481
    Abstract: Disclosed is a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit configured to perform an erase characteristic check operation and an erase operation on the plurality of memory blocks. The semiconductor memory device also includes a control circuit configured to control the peripheral circuit to perform the erase characteristic check operation and the erase operation, determine whether each of the plurality of memory blocks has a normal erase characteristic or an overerase characteristic according to a result of the erase characteristic check operation for each of the plurality of memory blocks, and set an erase voltage of the erase operation based on the determined erase characteristic according to the result of the erase characteristic check operation.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventors: Sang Hyun Jang, Kyoung Jin Park
  • Patent number: 10540097
    Abstract: The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The apparatus also includes a controller configured to direct a first movement of a number of data values from a subarray in the second subset to a subarray in the first subset and performance of a sequential plurality of operations in-memory on the number of data values by the first sensing circuitry coupled to the first subset.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: January 21, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Perry V. Lea
  • Patent number: 10504583
    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.
    Type: Grant
    Filed: August 12, 2018
    Date of Patent: December 10, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, James E. Harris
  • Patent number: 10176873
    Abstract: A semiconductor memory device and a reading method thereof are provided. A flash memory includes a memory cell array; a page buffer/reading circuit, holding data of a selected page of the memory cell array; a decoding/selecting circuit, selecting n bits data from the data held by the page buffer based on a column address; and a data bus for n bits, which is connected to the decoding/selecting circuit. The decoding/selecting circuit further connects n/2 bits data of an even address to a lower bit position of the data bus and connects n/2 bits data of an odd address to a upper bit position of the data bus based on the column address. When the start address is the odd address, data of the odd address and data of the even address next to the odd address are selected.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: January 8, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Hidemitsu Kojima
  • Patent number: 10176595
    Abstract: The present invention relates to an image processing apparatus having an automatic compensation function for an image obtained from a camera, and a method thereof, and provides an image processing apparatus having an automatic compensation function for an image obtained from a camera, the apparatus comprising: an automatic compensation pattern of which one or more can be provided in an arbitrary place near a camera; an input/output module which receives an image as an input from the camera and transmits the same to the image processing apparatus; and an image processing module which is a processing unit containing an algorithm for compensating for distortion of the image obtained from the camera, wherein the input/output module comprises an image input/output unit for transmitting/receiving data in between the camera and the image processing module, and a storage unit for storing information processed by the image processing module, and the image processing module comprises a distortion compensation unit, an
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: January 8, 2019
    Assignee: VADAS, LTD
    Inventor: Jun Seok Lee
  • Patent number: 9483411
    Abstract: According to one embodiment, a memory system includes a first memory, a second memory, a third memory, a data transmission controller, and a processing unit. The second memory is configured to store first management information to manage the first memory. The third memory is configured to be accessed at a speed higher than the second memory. The processing unit causes the data transmission controller to transmit second management information and third management information from the second memory to the third memory in a burst mode before a read process is performed on the first memory. The second management information and the third management information are related to the read process and are included in the first management information. The processing unit performs the read process on the first memory using the second management information and the third management information stored in the third memory.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: November 1, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Erika Ikeda, Yoshihisa Kojima
  • Patent number: 9451236
    Abstract: The present invention relates to three-dimensional visualization of the surrounding images of a vehicle, and comprises the steps of: enabling a plurality of wide angle cameras provided at a vehicle to receive a plurality of photographed images for reference patterns formed on the ground; extracting feature points from the photographed reference patterns and estimating a relative location and an installation angle of each camera using the known physical location information of the extracted feature points; obtaining optical parameters comprising an optical center of a lens for correcting lens distortion using the photographed images and mapping each image on a surface of a Gaussian sphere using the obtained optical center; changing an angle and distance such that the Gaussian sphere and the real reference patterns correspond to each other using the relative location and the installation angle of the estimated camera and arranging the images in a three-dimensional virtual space; and obtaining a three-dimensiona
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: September 20, 2016
    Assignee: VADAS, LTD.
    Inventors: Jun-Seok Lee, Byung-Chan Jeon, Gyu-Ro Park, Sang-Jin Ryu, Byeong-Moon Song
  • Patent number: 9343157
    Abstract: An EEPROM circuit includes a data reception register and a column decoder. A buffer memory having a size corresponding to the size of a data page is included between the data reception register and the column decoder.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: May 17, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Fran├žois Tailliet
  • Patent number: 9343122
    Abstract: A circuit configuration includes a first input for inputting a first set of digital input data, an output for outputting digital output data, and a control input for receiving a control signal. At least two register units are provided and the circuit configuration is designed to write, as a function of the control signal, into a first register unit optionally at least a part of the first set of input data or of the second set of digital input data and to write into a second register unit optionally at least a part of the first set of input data or of the second set of input data.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: May 17, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Matthew Lewis, Paulius Duplys
  • Patent number: 9042168
    Abstract: A system including a state set module to arrange states of a memory cell in three sets. The memory cell stores three bits when programmed to a state. Each set includes three rows of bits. In a set, a row includes one of the three bits of the states. The first, second, and third rows of the first, second, and third sets include a first number of state transitions. The second, third, and first rows of the first, second, and third sets include a second number of state transitions. The third, first, and second rows of the first, second, and third sets include a third number of state transitions. A write module writes first, second, and third portions of data to a plurality of memory cells, each memory cell storing the three bits when programmed to a state, using states selected respectively from the first, second, and third sets.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: May 26, 2015
    Assignee: Marvell International LTD.
    Inventor: Xueshi Yang
  • Publication number: 20150109874
    Abstract: A method, system and memory controller are provided for implementing memory devices with sub-bank architecture in a computer system. An array is divided into sub-blocks having odd bit lines and even bit lines. The sub-blocks are alternated with rows of sense amplifiers; wherein a particular row of sense amplifiers connects only to odd bit lines and a next row of sense amplifiers connects only to even bit lines. More than one word line for a sub-block is allowed to be active at the same time, where a first active word line will select memory cells connected to even bit lines and a second active word line will select memory cells connected to odd bit lines.
    Type: Application
    Filed: October 23, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Hillery C. Hunter, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule
  • Publication number: 20150098282
    Abstract: Disclosed herein is a semiconductor memory device using a pre-fetch method and a semiconductor system including the same. The semiconductor memory device may include a memory bank having an odd-numbered array region suitable for inputting/outputting data through N first local lines in response to an odd-numbered column address, and an even-numbered array region suitable for inputting/outputting data through N second local lines in response to an even-numbered column address, N being a positive integer, a column address generation unit suitable for consecutively generating the odd-numbered column address and the even-numbered column address whose generation sequence is controlled depending on whether an external column address has an even-numbered value or an odd-numbered value, and N global lines coupled in common to the N first local lines and the N second local lines, suitable for inputting/outputting data.
    Type: Application
    Filed: December 15, 2013
    Publication date: April 9, 2015
    Applicant: SK hynix Inc.
    Inventor: Geun-Il LEE
  • Publication number: 20150055430
    Abstract: A nonvolatile memory device comprises multiple memory blocks each comprising multiple memory cells arranged at intersections of wordlines and bitlines, an address decoder configured to electrically connect first lines to wordlines of one of the memory blocks in response to an address, a line selection switch circuit configured to electrically connect the first lines to second lines in different configurations according to the address, a first line decoder configured to provide the second lines with wordline voltages needed for driving, and a voltage generator configured to generate the wordline voltages.
    Type: Application
    Filed: April 21, 2014
    Publication date: February 26, 2015
    Inventors: SU-YONG KIM, LEE JINYUB, LEE SEUNGJAE
  • Patent number: 8947954
    Abstract: A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second bit is able to receive a copy and hold the primary value. When the copying mechanism is over, the two memory planes may act as two completely independent structures.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: February 3, 2015
    Assignee: Mentor Graphics Corporation
    Inventor: Peer Schmitt
  • Patent number: 8891317
    Abstract: A volatile memory including volatile memory cells adapted to the performing of data write and read operations. The memory cells are arranged in rows and in columns and, further, are distributed in separate groups of memory cells for each row. The memory includes a first memory cell selection circuit configured to perform write operations and a second memory cell selection circuit, different from the first circuit, configured to perform read operations. The first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation. The second circuit is capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: November 18, 2014
    Assignee: STMicroelectronics SA
    Inventors: Anis Feki, Jean-Christophe Lafont, David Turgis
  • Patent number: 8873330
    Abstract: A plurality of address conversion circuits are provided for memory cores respectively, and convert logical address data supplied from outside to physical address data. In an interleave operation, the address conversion circuits output the logical address data as the physical address data without converting the logical address data when a first memory core is to be accessed earlier than a second memory core, whereas output address data obtained by adding a certain value to the logical address data as the physical address data when the second memory core is to be accessed earlier than the first memory core.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumihiro Kono, Kiyotaro Itagaki
  • Patent number: 8861301
    Abstract: A memory includes a memory array having a plurality of word lines, a plurality of latching predecoders, and word line driver logic. Each latching predecoder receives a clock signal and a plurality of address signals and latches a result of a logic function of the plurality of address signals in response to a first edge of a clock cycle of the clock signal and provides a predetermined value in response to a second edge of the first clock cycle of the clock signal, wherein, in response to the second edge, every latching decoder of the plurality of latching predecoders provides a same predetermined value. The word line driver logic selectively activates a selected word line of the plurality of word lines in response to the latched results.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: October 14, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hema Ramamurthy, Ravindraraj Ramaraju
  • Patent number: 8854913
    Abstract: A semiconductor memory device and method of operating the same is disclosed. The semiconductor memory device includes an address decoder including pass transistor groups, a memory block selector coupled in common to the pass transistor groups, and a block decoding section configured to deliver an enable signal through the block word line based on a block group address. The memory block selector is configured to deliver the enable signal to a first pass transistor group selected from the pass transistor groups in response to a block select signal to activate the first pass transistor group.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: October 7, 2014
    Assignee: SK Hynix Inc.
    Inventor: Chae Kyu Jang
  • Patent number: 8848424
    Abstract: A variable resistance nonvolatile memory device includes: bit lines in layers; word lines in layers formed at intervals between the layers of the bit lines; a memory cell array including basic array planes and having memory cells formed at crosspoints of the bit lines in the layers and the word lines in the layers; global bit lines provided in one-to-one correspondence with the basic array planes; and sets provided in one-to-one correspondence with the basic array planes, and each including a first selection switch element and a second selection switch element, wherein memory cells connected to the same word line are successively accessed in different basic array planes, and memory cells are selected so that voltages applied to the word line and bit lines are not changed and a direction in which current flows through the memory cells is the same.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: September 30, 2014
    Assignee: Panasonic Corporation
    Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Ryotaro Azuma
  • Patent number: 8841646
    Abstract: Disclosed are a semiconductor storage device and a manufacturing method. The storage device has: a substrate; a first word line above the substrate; a first laminated body above the first word line and having N+1 first inter-gate insulating layers and N first semiconductor layers alternately laminated; a first bit line above the laminated body and extending in a direction that intersects the first word line; a first gate insulating layer on side surfaces of the first inter-gate insulating layers and the first semiconductor layers; a first channel layer on the side surface of the first gate insulating layer; and a first variable resistance material layer on the side surface of the first channel layer. The first variable resistance material layer is in a region where the first word line and the first bit line intersect. A polysilicon diode is used as a selection element.
    Type: Grant
    Filed: October 6, 2013
    Date of Patent: September 23, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Sasago, Akio Shima, Satoru Hanzawa, Takashi Kobayashi, Masaharu Kinoshita, Norikatsu Takaura
  • Publication number: 20140241099
    Abstract: A memory system is provided which includes multiple semiconductor memories having arrays of memory cells and a memory controller configured to provide an address in common to the multiple memories. First and second addresses corresponding to first and second rows of memory cells in first and second memories are selected according to the address in common. The first row and its adjacent rows in the first memory can all be different from the second row and its adjacent rows in the second semiconductor memory. Different conversion schemes can provide scramble information used to convert the address in common into the first and second addresses.
    Type: Application
    Filed: December 9, 2013
    Publication date: August 28, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seong-Young Seo, Chul Woo Park
  • Patent number: 8819359
    Abstract: A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses to locations within memory modules and ranks so that physical addresses for a given page all map to the same memory module, and physical addresses for the given page are interleaved across the plurality of ranks which comprise the same memory module.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: August 26, 2014
    Assignee: Oracle America, Inc.
    Inventors: Sanjiv Kapil, Blake Alan Jones
  • Patent number: 8797814
    Abstract: An apparatus and method is capable of reducing instantaneously consumed current by allowing write drivers and input buffers not to be simultaneously driven in a multi-test of semiconductor chips. A multi-test apparatus includes an input unit configured to receive data for testing, wherein the data for testing is inputted from a circuit outside of the multi-test apparatus, a plurality of memory banks each including a plurality of memory cells, a plurality of write drivers, corresponding to the respective memory banks, configured to write the test data in the plurality of memory banks, and a write control unit configured to control the plurality of write drivers so that the test data is written in the memory banks in at least two time periods.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: August 5, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dae-Suk Kim
  • Patent number: 8767499
    Abstract: A semiconductor memory device includes a random address generation unit configured to receive a multi-bit source address and generate a multi-bit random address and a signal mixing unit configured to mix the multi-bit random address with a data, wherein the random address generation unit has a plurality of transmission lines configured to electrically connect the plurality of input terminals respectively corresponding to bits of the source address and the plurality of output terminals respectively corresponding to bits of the random address in one-to-one correspondence regardless of an order of the bits of the source address.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: July 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dae-Il Choi
  • Patent number: 8750026
    Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: June 10, 2014
    Assignee: Altera Corporation
    Inventors: Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin S. Lee, Jeffrey Xiaoqi Tung, Albert Ratnakumar, Qi Xiang, Irfan Rahim, Andy L. Lee, Jeffrey T. Watt, Srinivas Perisetty
  • Patent number: 8743651
    Abstract: A memory includes a plurality of latching predecoders, each including a first transistor coupled between a power supply voltage and a latch and having a control electrode coupled to a clock signal; a second transistor coupled to the first transistor and having a control electrode coupled to a first address bit signal; a third transistor coupled to the second transistor and having a control electrode coupled to a second address bit signal; a fourth transistor coupled to the third transistor and having a control electrode coupled to a delayed and inverted version of the clock signal; a fifth transistor coupled between the fourth transistor and ground and having a control electrode coupled to the clock signal; and an output which provides a predecode value during a first portion of a clock cycle of the clock signal and a predetermined logic level during a second portion of the clock cycle.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: June 3, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hema Ramamurthy, Ravindraraj Ramaraju
  • Patent number: 8737149
    Abstract: A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays. Each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at one time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent each other in the plurality of memory cell mats. The memory cell mats with the plurality of activated word lines are distributed. Therefore, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: May 27, 2014
    Inventors: Yoshiro Riho, Hiromasa Noda, Kazuki Sakuma
  • Patent number: 8699293
    Abstract: A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non-volatile storage elements, a plurality of bit lines connected to the blocks of non-volatile storage elements, multiple sets of word lines drivers such that each set of word line drivers is positioned between two adjacent blocks for driving word lines connected to the two adjacent blocks, global data lines, local data lines in selective communication with the bit lines, one or more selection circuits that selectively connect the global data lines to selected local data lines and connect unselected local data lines to one or more unselected bit line signals and control circuitry in communication with the one or more selection circuits and the global data lines.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: April 15, 2014
    Assignee: Sandisk 3D LLC
    Inventors: Tianhong Yan, Tz-yi Liu, Roy E. Scheuerlein
  • Patent number: 8699294
    Abstract: A nonvolatile memory device includes a plurality of memory blocks vertically arranged, first and second row decoder groups configured to couple first and second local global word lines and the word lines of upper memory blocks among the plurality of memory blocks, third and fourth row decoder groups configured to couple third and fourth local global word lines and the word lines of lower memory blocks among the plurality of memory blocks, a first local decoder switch configured to couple a plurality of global lines and the first or second local global word lines, a second local decoder switch configured to couple the plurality of global lines and the third or fourth local global word lines, and a high voltage generator configured to supply operating voltages to the plurality of global word lines.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: April 15, 2014
    Assignee: SK Hynix Inc.
    Inventor: Sang Hwa Chung
  • Patent number: 8699269
    Abstract: A state set module arranges states of a memory cell in a first and a second sequence in a first and a second state set, respectively. The memory cell stores first and second bits when programmed to a state. When the states in the first and second state sets are accessed respectively in the first and the second sequence, the first and second bits of the states in the first and second state sets exhibit different number of logical transitions. A write module receives first and second sets of bits to be written as the first and second bits in a plurality of memory cells, and selects states from the first and second state sets in an alternating pattern to write the first and second sets of bits as the first and second bits in the plurality of memory cells.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: April 15, 2014
    Assignee: Marvell International Ltd.
    Inventor: Xueshi Yang
  • Patent number: 8671254
    Abstract: A wireless communications device has two or more multiple port memory units operable to perform encryption/decryption shuffling and processing. Other circuits and methods of manufacture and operation are also disclosed.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: March 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Tonmoy Shingal, Chakravarthy Srinivasan, Shankaranarayana Karantha
  • Patent number: 8659955
    Abstract: According to an exemplary embodiment, a memory array arrangement includes a plurality of word lines, where at least two of the plurality of word lines are concurrently active word lines. Each of the plurality of word lines drive at least one group of columns. The memory array arrangement also includes a multiplexer for coupling one memory cell in a selected group of columns to at least one of the plurality of sense amps, thereby achieving a reduced sense amp-to-column ratio. The memory array arrangement further includes a plurality of I/O buffers each corresponding to the at least one of the plurality of sense amps. The memory array arrangement thereby results in the plurality of word lines having reduced resistive and capacitive loading.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: February 25, 2014
    Assignee: Broadcom Corporation
    Inventors: Chulmin Jung, Myron Buer
  • Publication number: 20140043929
    Abstract: A semiconductor memory device and method of operating the same is disclosed. The semiconductor memory device includes an address decoder including pass transistor groups, a memory block selector coupled in common to the pass transistor groups, and a block decoding section configured to deliver an enable signal through the block word line based on a block group address. The memory block selector is configured to deliver the enable signal to a first pass transistor group selected from the the pass transistor groups in response to a block select signal to activate the first pass transistor group.
    Type: Application
    Filed: December 17, 2012
    Publication date: February 13, 2014
    Applicant: SK Hynix Inc.
    Inventor: Chae Kyu Jang
  • Patent number: 8638620
    Abstract: A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. In another aspect, the two memory cells can be considered a dual bit cell that contains a copying mechanism. There are two interleaved memory planes, assembled from bit cells that contain two bits of information. One bit is the primary bit that corresponds to the normal RAM bit. The second bit is able to receive a copy and hold the primary value. When the copying mechanism is over, the two memory planes may act as two completely independent structures.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: January 28, 2014
    Assignee: Mentor Graphics Corporation
    Inventor: Peer Schmitt
  • Patent number: 8627022
    Abstract: A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K information elements; wherein the group of memory banks comprises N pairs of single access memory banks; each pair of memory banks comprises an even memory bank and an odd memory bank; wherein each pair of memory banks stores sub-set of K/N information elements; wherein an even memory bank of each pair of memory banks stores even address information elements of a certain sub-set of K/N information elements and an odd memory bank of each pair of memory banks stores odd address information elements of the certain sub-set of K/N information elements; wherein K/N is an even positive integer; and a non-blocking interconnect, coupled to the group of processing entities and to the group of memory banks; wherein during each fetch cycle each processing entity of the group of processing entities fetches a first information elemen
    Type: Grant
    Filed: January 21, 2008
    Date of Patent: January 7, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yuval Neeman, Ron Bercovich, Guy Drory, Dror Gilad, Aviel Livay, Yonatan Naor
  • Patent number: 8611174
    Abstract: A semiconductor memory device is configured to have a first memory cell array having a plurality of blocks (cell arrays corresponded to one I/O bit), each block having a plurality of columns and being corresponding respectively to one of data terminals, wherein the blocks being arranged side by side in the column-wise direction, and a second memory cell array configured similarly to the first memory cell array, and is also configured to assign addresses while classifying the even-number-th memory blocks in the first memory cell array and the odd-number-th memory blocks in the second memory cell array into a first set, whereas the odd-number-th memory blocks in the first memory cell array and the even-number-th memory blocks in the second memory cell array into a second set, so as to output data from every other block in each memory cell array upon being accessed with a certain address.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: December 17, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hiroyuki Imoto
  • Patent number: 8605476
    Abstract: A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: December 10, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Takenori Sato, Kazuhiko Kajigaya, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Akira Kotabe, Satoru Akiyama
  • Patent number: 8576655
    Abstract: A semiconductor memory includes a bit cell having first and inverters forming a latch. First and second transistors are respectively coupled to first and second storage nodes of the latch and to first and second write bit lines. Each of the first and second transistors has a respective gate coupled to a first node. Third and fourth transistors are coupled together in series at the first node and are disposed between a write word line and a first voltage source. Each of the first and second transistors has a respective gate coupled to a first control line. A fifth transistor has a source coupled to a second voltage source, a drain coupled to at least one of the inverters of the latch, and a gate coupled to the first node. A read port is coupled to a first read bit line and to the second storage node of the latch.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: November 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Min Chan, Yen-Huei Chen, Jihi-Yu Lin, Hsien-Yu Pan, Hung-Jen Liao
  • Patent number: 8570821
    Abstract: A semiconductor memory device includes a latch address generation unit configured to latch row addresses to generate first and second latch addresses when at least one of memory cells coupled to sub word lines is faulty, wherein the first and second latch addresses select different main word lines, and a repair unit configured to perform a repair operation on memory cells coupled to the main word lines selected by the first and second latch addresses.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: October 29, 2013
    Assignee: SK Hynix Inc.
    Inventors: Sun Young Hwang, Sang Il Park
  • Patent number: 8570827
    Abstract: Controllable arrays in a memory may be activated and deactivated independently. In one embodiment, a processor may include a memory. The memory may be a de-interleaved memory with independently selectable arrays. Based on an address bit of an address used to access data from the memory, a wordline and downstream components may be activated while another wordline and downstream components may be deactivated.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: October 29, 2013
    Assignee: Apple Inc.
    Inventors: Steven C. Sullivan, Abhijeet R. Tanpure, William V. Miller, Ben D. Jarrett
  • Patent number: 8563961
    Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: October 22, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Sasago, Akio Shima, Satoru Hanzawa, Takashi Kobayashi, Masaharu Kinoshita, Norikastsu Takaura
  • Patent number: 8520448
    Abstract: A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. First, second and third sets of non-volatile storage elements are programmed in separate sequences, one after another, so that all program-verify operations occur for the first set, then for the second set, and then for the third set. Each non-volatile storage element in a set is separated from the next closest non-volatile storage element in the set at least two other non-volatile storage elements in the set.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: August 27, 2013
    Assignee: SanDisk Technologies Inc.
    Inventors: Jeffrey W Lutze, Deepanshu Dutta
  • Patent number: 8498154
    Abstract: A memory system includes a state set module that provides a first state set having a plurality of states, each being assigned to represent a particular data sequence, and a second state set having a same number of states as the first state set, wherein an assignment of one or more particular data sequences among the states of the second state set is different relative to that set forth in the first state set. The memory system further includes a write module that writes first data to a first multi-level memory cell of the memory system based on the first state set, the first multi-level cell being located on a wordline of the memory system, and that writes second data to a second multi-level memory cell of the memory system based on the second state set, the second multi-level cell being located on the wordline of the memory system.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: July 30, 2013
    Assignee: Marvell International Ltd.
    Inventor: Xueshi Yang
  • Patent number: 8493805
    Abstract: A semiconductor apparatus includes: odd and even sub word line driving units configured to selectively drive odd sub word lines and even sub word lines among a plurality of sub word lines; a bit line sense amplifier including a plurality of sense amplifier driving lines which are electrically connected with bit lines; a first sense amplifier driving unit formed on one side of the bit line sense amplifier which extends in the same direction as the bit lines, and configured to drive odd sense amplifier driving lines among the plurality of sense amplifier driving lines; and a second sense amplifier driving unit formed on another side of the bit line sense amplifier which extends in the same direction as the bit lines, and configured to drive even sense amplifier driving lines among the plurality of sense amplifier driving lines according to driving of the even sub word lines.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: July 23, 2013
    Assignee: SK Hynix Inc.
    Inventor: Hyun Su Yoon
  • Patent number: 8488406
    Abstract: A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the internal power-supply voltage from the first power-supply circuit through a first line, a second internal circuit that receives a supply of the internal power-supply voltage from the second power-supply circuit through a second line, an inter-block line that connects the first and second lines to each other, and a control circuit that operates the first and second internal circuits in a predetermined operating cycle, and controls a length of a period during which the first and second internal circuits operate simultaneously.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: July 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Toshikatsu Jinbo