Abstract: A semiconductor apparatus includes a logic memory chip including a transmission block which outputs input signals and a strobe signal; and a plurality of memory chips stacked with the logic memory chip. At least one of the plurality of memory chips includes a plurality of reception blocks. Each of the plurality of reception blocks receives an input signal among the input signals and the strobe signal, and controls a phase of any one of the input signal and the strobe signal.

Abstract: An image sensor has a plurality of pixels arranged in an array, a selection means for selecting individual pixels in the array, and a shutter means for transmitting a shutter signal to the pixels. The pixels are constructed and arranged to sense incident light only when both selected and in receipt of a shutter signal. The pixels in said array can thus be triggered individually to capture light at different times.

Abstract: A semiconductor system includes a memory configured to output a parity bit during a read operation and receive a data mask (DM) signal during a write operation. The semiconductor system also includes a System On Chip (SOC) configured to detect errors by decoding the parity bit during the read operation, and output the DM signal to the memory during the write operation. Since the parity bit is generated in the memory based on data received from outside the memory, the semiconductor device and a corresponding semiconductor system may reduce the size of a storage space for parity bits.

Abstract: A semiconductor device may include a write control block configured to generate a plurality of write enable signals for controlling a write operation, and a write delay block configured to apply delay times to a plurality of write data which are transmitted through a write global input/output line. The semiconductor device may also include a plurality of banks configured to operate in response to the plurality of write enable signals and receive the plurality of write data, wherein the plurality of write data have different delay times according to physical positions of the plurality of banks.

Abstract: In a conventional DRAM, data read errors are more likely to occur along with miniaturization of DRAM A small change in the potential of a first bit line is inverted by a first inverter constituted by an n-channel transistor and a p-channel transistor, and is output to a second bit line through a first selection transistor, which is a first switch. Since the potential of the second bit line is the inverse of the potential of the first bit line, the potential difference between the first bit line and the second bit line is increased. The increased potential difference is amplified by a known sense amplifier, a flip-flop circuit composed of the first inverter and a second inverter (constituted by an n-channel transistor and a p-channel transistor), or the like.

Abstract: Apparatuses and methods are disclosed, including an apparatus with a string of charge storage devices coupled to a common source, a first switch coupled between the string of charge storage devices and a load current source, and a second switch coupled between the load current source and the common source. Additional apparatuses and methods are described.

Abstract: Apparatuses and methods for memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An example apparatus includes first and second memory sections, and further includes a sense amplifier region. A memory section includes a word line extending in a first direction and a digit line extending in a second direction, and the sense amplifier region is disposed between the first and second memory sections. The sense amplifier region includes a sense amplifier coupled to the digit line, a local input/output (LIO) line, a column select circuit coupled to the sense amplifier, and a column select line. The column select line extends in the first direction and is configured to provide a column select signal to the column select circuit. Capacitance of a LIO line may be reduced by coupling fewer sense amplifiers of a group to the LIO line.

Abstract: According to one embodiment, a memory device includes: a nonvolatile memory that stores data according to a write access; an address memory that stores a first address described with a gray code; a first counter that counts up the first address for each write access, generates a second address as the count-up result, and supplies the second address to the nonvolatile memory; a rounding circuit configured to calculate a third address that is equal to or larger than a final output of the first counter and larger than the first address by one or a power of two after a series of write accesses is completed; and a controller that rewrites the third address in the address memory.

Abstract: An operating access method for a DRAM is provided. A first address is obtained via an address bus and a first command is obtained via a command bus from a controller. A second address is obtained via the address bus and a second command is obtained via the command bus from the controller after the first command is obtained. The first address and the second address are combined to obtain a valid address, wherein the valid address is a row address when each of the first command and the second command is an active command. In addition, the valid address is a column address when the second command is an access command.

Abstract: Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections.

Abstract: A memory comprises a first layer comprising a first line. The memory also comprises second layer comprising a series of bit-cells, a word line driver, and a word line coupled to the word line driver. The memory further comprises a first plurality of through vias coupling the word line to the first line. The word line has a resistance value based on a geometry of the word line, and the first line is configured to reduce the resistance value of the word line by a degree associated with a geometry of the first line.

Abstract: A nonvolatile memory device includes a plurality of vertical NAND flash memory cells arranged in a three dimensional (3D) structure, a first memory block disposed in the 3D structure and having memory cells selected by a first ground selection line and a second ground selection line, wherein the first and second ground selection lines are electrically separated from each other, a second memory block disposed in the 3D structure and having memory cells selected by a third selection line and fourth selection line, wherein the third and fourth ground selection lines are electrically separated from each other, and a pass transistor that transfers a driving signal to turn on ground selection transistors respectively connected to the first and third ground selection lines in response to a block selection signal.

Abstract: A semiconductor memory device includes a first bank, a second bank disposed separately from the first bank along a first direction, a third bank disposed separately from the first bank along a second direction substantially perpendicular to the first direction, a fourth bank disposed separately from the second bank along the second direction and from the third bank along the first direction, a first row control region, which is disposed between the first bank and the second bank, suitable for controlling a row decoding operation of the first bank and the second bank, a second row control region, which is disposed between the third bank and the fourth bank, suitable for controlling a row decoding operation of the third bank and the fourth bank, and a refresh control unit suitable for controlling a refresh operation of the first to fourth banks.

Abstract: Non-volatile memory devices including on-die termination circuits connected to an input/output circuit and an on-die termination control logic detecting a preamble of a strobe signal based on a command and a control signal and activating the on-die termination within the preamble period.

Abstract: According to one embodiment, a memory device includes: a first interconnect extending in a first direction; a plurality of second interconnects extending in a second direction intersecting with the first direction, and having lower ends positioned on the first interconnect; a plurality of third interconnects extending in a third direction intersecting with the second direction; a memory layer provided between the second interconnects and the third interconnects; and selectors respectively provided between the first interconnect and the lower ends of the plurality of second interconnects.

Abstract: A non-volatile memory device incorporates a write buffer within a multi-level column decoder to enable multiple memory cells associated with a single write driver to be written in parallel. In this manner, in a non-volatile memory such as a flash memory that performs batch write operation, a group of data bits for a single I/O can be written to the memory cells at a time, thereby reducing the number of write cycles required for writing a block of program data and increasing the speed of write operation.

Abstract: A multiport memory emulator receives first and a second memory commands for concurrent processing of memory commands in one operation clock cycle. Data operands are stored in a memory array of bitcells that is arranged as rows and memory banks. An auxiliary memory bank provides a bitcell for physically storing an additional word for each row. The bank address portion of each of the first and second memory commands is respectively translated into a first and second physical bank address. The second physical bank address is assigned a bank address of a bank that is currently unused in response to a determination that the bank address portions are equal and the bank associated with the first bank address is designated as a currently unused bank for subsequently received memory commands in response to the determination that the bank address portions are equal. Simultaneous read and write operations are possible.

Abstract: Command signal management methods and circuits in memory devices are disclosed. Command signals are selectively passed and blocked to enforce safe operating characteristics within a memory device. In at least one embodiment, a command signal management circuit is configured to selectively block a command signal while a memory device operation is being performed. In at least one other embodiment, one or more command blocking circuits are configured to selectively pass and block one or more command signals generated by a memory access device coupled to the memory device while a memory device operation is being performed in the memory device.

Abstract: An access method for a DRAM is provided. A row address is partitioned into a first portion and a second portion. The first portion of the row address is provided via an address bus and a first active command is provided via a command bus the DRAM. The second portion of the row address is provided via the address bus and a second active command is provided via the command bus to the DRAM, after the first active command is provided. The address bus is formed by a plurality of address lines, and a quantity of the address lines is smaller than the number of bits of the row address.

Abstract: A die assignment scheme assigns data, in the order it is received, to multiple memory dies with some randomness. Randomization events, such as skipping dies or reversing direction, occur at intervals, with a deterministic assignment scheme used between randomization events. Intervals between randomization events may be of random length, or of fixed length.

Abstract: A storage device is provided which includes a plurality of memory chips each nonvolatile memory cells divided into a first memory region and a second memory region; and a memory controller configured to buffer data provided from the exterior and to control the plurality of memory chips to perform a buffer-program operation and a main-program operation. The buffered data is stored at the first memory region at the buffer-program operation and data stored at the first memory region is written at the second memory region at the main-program operation. During a main-program operation of a first memory chip among the plurality of memory chips, the memory controller buffers data to be written at a second memory chip.

Abstract: An embedded memory device includes a mask ROM including a plurality of mask ROM cells and an address decoder configured to decode an address of the plurality of mask ROM cells; and an e-fuse memory configured to replace a part of data stored in the mask ROM with replacement data, the e-fuse memory including, a plurality of e-fuse memory cells configured to store the replacement data, and an e-fuse address selector configured to decode an address of the plurality of e-fuse memory cells and to selectively cause data of one or more of the plurality of e-fuse memory cells to be output based on the decoding result.

Abstract: A semiconductor memory device according to the embodiment comprises memory cells each having asymmetrical voltage-current characteristics, wherein the memory cell has a first state, and a second state and a third state of higher resistances than that in the first state, wherein the memory cell, (1) in the second state, makes a transition to the first state on application of a first voltage of the first polarity, (2) in the first state, makes a transition to the second state on application of a second voltage of the second polarity, (3) in the first state, makes a transition to the third state on application of a third voltage of the second polarity (the third voltage<the second voltage), and (4) in the third state, makes a transition to the first state on application of a fourth voltage of the first polarity (the fourth voltage<the first voltage).

Abstract: A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory array based on a clock signal and an output signal from the read/write control circuit.

Abstract: Examples are disclosed for accessing a dynamic random access memory (DRAM) array. In some examples, sub-arrays of a DRAM bank may be capable of opening multiple pages responsive to a same column address strobe. In other examples, sub-arrays of a DRAM bank may be arranged such that input/output (IO) bits may be routed in a serialized manner over an IO wire. For these other examples, the IO wire may pass through a DRAM die including the DRAM bank and/or may couple to a memory channel or bus outside of the DRAM die. Other examples are described and claimed.

Abstract: A memory circuit includes a voltage boosting circuit for generating a voltage that exceeds a voltage supply of the voltage boosting circuit. The voltage boosting circuit includes a first transistor having a first polarity type and a second transistor having a second polarity type opposite the first transistor. The first transistor is a planar transistor, a source of the first transistor being connected with the voltage supply, and a gate of the first transistor receiving a control signal. The second transistor includes a gate formed in at least two planes. A source of the second transistor is connected with the voltage supply, a gate of the second transistor receives the control signal, and a drain of the second transistor is connected with a drain of the first transistor and forms an output of the voltage boosting circuit for generating a boosted supply voltage as a function of the control signal.

Abstract: Systems and methods of encoding and decoding shaped data include determining a bit representation corresponding to a bit in a representation of a codeword that is read from a non-volatile memory of a data storage device. A soft metric corresponding to the bit representation is determined at least partially based on an amount of shaping of data.

Abstract: A method and apparatus for organizing memory for a computer system including a plurality of memory devices, connected to a logic device, particularly a memory system having a plurality of stacked memory dice connected to a logic die, with the logic device having capability to analyze and compensate for differing delays to the stacked devices stacking multiple dice divided into partitions serviced by multiple buses connected to a logic die, to increase throughput between the devices and logic device allowing large scale integration of memory with self-healing capability.

Abstract: A semiconductor memory apparatus includes: a memory cell area including a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin.

Abstract: Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling.

Abstract: A memory device comprises an array of bitcells arranged as a plurality of rows of bitcells and a plurality of columns of bitcells, and has a plurality of wordlines and a plurality of readout channels. A control unit is configured to control access to the array of bitcells, wherein in response to a memory access request specifying a memory address the control unit is configured to activate a selected wordline and to activate the plurality of readout channels, and to access a row of bitcells in said array storing a data word and addressed by the memory address. The data word consists of a number of data bits given by a number of bitcells in each row of bitcells. The control unit is further configured to be responsive to a masking signal and, when the masking signal is asserted when said memory access request is received, the control unit is configured to activate only a portion of the selected wordline and a portion of the plurality of readout channels, such that only a portion of the data word is accessed.

Abstract: A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell. The bit line sense amplifier circuit may include a first inverter having an input node coupled to the first bit line and an output node coupled to the second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit may be configured to activate the first inverter without activating the second inverter during a first time period and to activate the first inverter and the second inverter at the same time during a second time period after the first time period.

Abstract: A flash memory device reducing a layout area is provided. In the flash memory device, even power transistors and odd power transistors of a plurality of power connection portions corresponding to a plurality of pairs of bit lines and even select transistors and odd select transistors of a plurality of select connection portions corresponding thereto are disposed in one common active region. In the flash memory device, since the number of insulation regions/layout areas for distinguishing active regions is reduced, a layout length in the vertical direction is reduced, ultimately reducing an entire required layout area considerably.

Abstract: Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is to be closed.

Abstract: A semiconductor apparatus includes first and second through vias, a first path setting unit, and a second path setting unit. The first and second through vias connect first and second chips. The first path setting unit connects a first chip circuit to a first input/output terminal, and the second through via to a second input/output terminal. The second path setting unit connects a second chip circuit to the first through via and the second through via, wherein the first through via is connected to the second input/output terminal.

Abstract: A system and method includes reception of a first image data value of a digital image, determination of a first index based on the first image data value, determination of a value stored in a first array of a first shared memory at the first index, and determination of whether the value stored in the first array of the first shared memory at the first index is equal to the first image data value. If the value stored in the first array of the first shared memory at the first index is equal to the first image data value, 1 is added to a count value stored in a second array of the first shared memory at the first index. If the value stored in the first array of the first shared memory at the first index is not equal to the first image data value a count value stored in a second shared memory in association with the first image data value is updated.

Abstract: An electronic device (22, 48, 50) includes an array (26) of memory cells, which are configured to store data values. One or more sense amplifiers (40) have respective inputs for receiving signals from the memory cells and are configured to output the data values corresponding to the received signals. Switching circuitry (36, 52) is coupled between the array of the memory cells and the sense amplifiers and is configured to receive an indication of a temporal pattern and to route the signals from the memory cells among the inputs of the sense amplifiers in accordance with the temporal pattern.

Abstract: A memory system (10) is disclosed, which comprises a flash-EEPROM nonvolatile memory (11) having a plurality of memory cells that have floating gates and in which data items are electrically erasable and writable, a cache memory (13) that temporarily stores data of the flash-EEPROM nonvolatile memory (11), a control circuit (12, 14) that controls the flash-EEPROM nonvolatile memory (11) and the cache memory (13), and an interface circuit (16) that communicates with a host, in which the control circuit functions to read data from a desired target area to-be-determined of the flash-EEPROM nonvolatile memory and detect an erased area to determine a written area/unwritten area by using as a determination condition whether or not a count number of data “0” of the read data has reached a preset criterion count number.

Abstract: According to one embodiment, a semiconductor memory apparatus includes a memory and a speed control unit. The speed control unit calculates a time-varying behavior of a permissible value of an accumulated amount of data written in the non-volatile semiconductor memory, where, after a start of a guaranteed period, data is written in the memory at a constant write speed so that the permissible value at an end time of the guaranteed period is equal to a sum of a first capacity and a second capacity. The first capacity is an accumulated amount of data written in the memory. The second capacity is an accumulated amount of data which is writable in the memory in a remaining time of the guaranteed period based on remaining rewritable times of existing blocks. The speed control unit controls a transmission speed of data from a host based on the permissible value.

Abstract: A nonvolatile memory device includes a memory cell array, a page buffer unit which output a verify-read result, a reference current generating unit which generates a reference current signal, a page buffer decoding unit which outputs currents according to the verify-read result. The nonvolatile memory device further includes an analog bit counting unit which counts the currents, a digital adding unit which calculates an accumulated sum of the counting result, a pass/fail checking unit which outputs a pass signal or fail signal according to the calculation result, and a control unit controlling a program operation.

Abstract: The invention relates to a method for memory management, in which memory usage data relating to the use of the memory is recorded. The memory usage data is determined in response to a number of memory write and/or read accesses.

Abstract: A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract: Provided is a semiconductor memory device including a column decoder, a plurality of sub-cell blocks, and a bit line selection circuit. The column decoder is configured to decode column addresses and drive column selection signals. Each of the sub-cell blocks includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells connected to the plurality of bit lines and the plurality of word lines. The bit line selection circuit includes a plurality of bit line connection controllers, and is configured to select one or more bit lines in response to the column selection signals. Each of the bit line connection controllers electrically couples a respective first bit line to corresponding first and second local input/output (I/O) lines in response to first and second column selection signals of the column selection signals, respectively.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell block that includes a memory cell array, the memory cell array including: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; and a memory cell that is provided at each of intersections of the plurality of first lines and the plurality of second lines and includes a variable resistance element, the memory cell array further including a protective resistance film that is provided respectively at each of the intersections of the plurality of first lines and the plurality of second lines and that is connected in series with the memory cell and ohmically contacts the memory cell, and the protective resistance film being configured from a material having a resistivity of 1˜100 ?·cm.

Abstract: According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

Abstract: A memory is provided that comprises a bank of non-volatile memory cells configured into a plurality of banklets. Each banklet in the plurality of banklets can be enabled separately and independently of the other banklets in the bank of non-volatile memory cells. The memory further comprises peripheral banklet circuitry, coupled to the bank of a non-volatile memory array, that is configured to enable selected subsets of bit lines within a selected banklet within the plurality of banklets. Moreover, the memory comprises banklet select circuitry, coupled to the peripheral banklet circuitry, that is configured to select data associated with a selected banklet for reading out from the banklet or writing to the banklet.

Abstract: A redundancy circuit includes a plurality of block address lines, a first fuse array storing a first data, a plurality of first local lines configured to supply a verification voltage to the first fuse array in response to a signal of a corresponding line among the plurality of block address lines, a second fuse array storing a second data, a plurality of second local lines configured to supply the verification voltage to the second fuse array in response to a signal of a corresponding line among the plurality of block address lines, and a plurality of verification lines configured to check the first data of the first fuse array and the second data of the second fuse array, wherein the plurality of verification lines are shared by the first fuse array and the second fuse array and are disposed between the first fuse array and the second fuse array.

Abstract: A read voltage generation circuit includes a register unit configured to store an initial read voltage code, a counter circuit configured to change a read voltage code in every read-retry operation, wherein an initial value of the read voltage code is the initial read voltage code; and a voltage generation circuit configured to generate a read voltage corresponding to a read voltage code produced by the counter circuit.

Abstract: A decoder circuit with reduced leakage configured to decode an address and drive one of a number of word lines may be implemented with two-high logic gates in a pre-decode stage, a decode stage, and a word line driver stage. Such decoder circuits may include, in the word line driver stage, a number of two-high NOR gates configured to drive one of a number of word lines. In some embodiments, the two-high logic gates that share common inputs are implemented with multi-output static logic.

Abstract: Methods and non-volatile storage systems are provided for using compensation that depends on the temperature at which the memory cells were programmed. Note that the read level compensation may have a component that is not dependent on the memory cells' Tco. That is, the component is not necessarily based on the temperature dependence of the Vth of the memory cells. The compensation may have a component that is dependent on the difference in width of individual Vth distributions of the different states across different temperatures of program verify. This compensation may be used for both verify and read, although a different amount of compensation may be used during read than during verify.