Abstract: A frequency divider divides the external clock signal by two and generates a first clock signal for an even-numbered data patch and a second clock signal for an odd-numbered data, wherein the first clock signal is opposite in phase to the second clock signal. A column selection line enable control circuit generates even-numbered column selection line enable signals in response to the first clock signal and generates odd-numbered column selection line enable signals in response to the second clock signal. A switching circuit connects a pair of bit lines to a pair of even-numbered input/output (I/O) lines in response to the even-numbered column selection line enable signals and connects the pair of bit lines to a pair of odd-numbered I/O lines in response to the odd-numbered column selection line enable signals.

Abstract: A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.

Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.

Abstract: The present invention provides circuitry for implementing a multiple data rate interface architectures for programmable logic devices. The programmable logic device of the invention includes a core and surrounding periphery. The core includes a plurality of logic elements arranged in an array. Some of the logic elements within the core include registers that are used as data registers for the multiple data rate interface.

Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

Abstract: A ferroelectric memory device comprises a plurality of subarrays having a plurality of bitlines and a plurality of wordlines crossing over the bitlines. Ferroelectric material is disposed between the wordlines and the bitlines to define a ferroelectric cell at each crossing of the wordlines and bitlines. Each subarray further comprises left and right voltage converters disposed on opposite sides thereof, to drive respective first and second sets of wordlines within the subarray. A plurality of global wordlines are couple to the left and right voltage converters of each subarray and are configured to establish the drive levels for respective wordlines of the subarrays. A bitline multiplexer selectively couples the bitlines of a select subarray to a plurality of sense amplifiers.

Abstract: A content addressable memory comprises a CAM control logic unit and plural cells connected in a chain. Each cell comprises a memory block coupled to a common address bus, a comparator coupled to a common data bus and to the data interface of the memory block. A switch couples the data interface of the memory block with the data bus, and a logic block including a Match flip-flop. The memory is operable in a Search phase and an Access phase. In the Search phase, a sequence of words on the common data bus is serially matched with the contents of a sequence of addresses in the memory blocks. In the Access phase, the cells matched in the Search phase are made serially available for access via common address and data buses.

Abstract: A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.

Abstract: A method for masking a ringing in a DDR SDRAM comprises in a write mode, generating first and second synchronizing signals by means of a DQS signal inputted from an exterior circuit, in order to synchronize input data, latching data in odd sequences from among the inputted data, which are sequentially inputted, at a rising edge of the first synchronizing signal, and latching data in even sequences from among the data, which are sequentially inputted, at a rising edge of the second synchronizing signal, aligning the data in odd sequences and the data in even sequences at a falling edge of the DQS signal so that the odd and even sequenced data has the same synchronized timing, and blocking activation of the second synchronizing signal by means of a first control signal, the a first control signal being synchronized with the falling edge of the last valid DQS signal that is normally inputted, so as to enable the blocking step and thereby masking the ringing phenomenon.

Abstract: A memory array having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store “1” and “0” bits. For such a memory array both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each “1” or “0” bit is stored as an electric charge in at least two memory cells.

Abstract: A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full density mode. In the full density mode, the refresh controller increments a counter at a rate that is half the rate the counter is incremented in the full density mode. A refresh trigger pulse, which initiates the refresh of the memory cells, is generated when the counter has incremented to one of a first counter stage in the full density mode and a counter stage two stages beyond the first counter stage in the half density mode. Circuitry is also provided for ignoring some auto-refresh commands applied to the SDRAM in the half density mode so that the memory cells are also refreshed less frequently in the auto-refresh mode.

Abstract: A method of narrowing the threshold voltage distribution in a memory. The method includes separating the erase and erase identification of odd memory cells from the erase and erase identification of even memory cells in an advanced non-volatile memory so that the distribution of the threshold voltage is narrowed.

Abstract: Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory system comprising a memory module and a memory controller. The memory module comprises a memory component having a memory core for storing data therein, a first set of interface connections for providing access to the memory core, and a second set of interface connections for providing access to the memory core. The memory module also comprises access circuitry for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections.

Abstract: A non-volatile semiconductor memory device includes a plurality of page buffers, each corresponding to a sense node. Voltages of a first set of sense nodes are varied according to states of corresponding memory cells during a first sense period, while voltages of a second set of sense nodes are fixed at a predetermined voltage. During the second sense period, voltages of the second set of sense nodes are varied according to states of corresponding memory cells, while voltages of the first set of sense nodes are fixed at a predetermined voltage. Using this sensing scheme, even though a sense node corresponding to an OFF cell is floated, a voltage of the floated sense node is not coupled down when a voltage of a neighboring sense node corresponding to an ON cell is lowered.

Abstract: The present invention relates to a synchronization circuit and method for allowing two or more successive read processes of a memory to be activated simultaneously without destroying the paths or the data. Two independent read processes are mutually independent while active, and are synchronized with respect to each other. The connection between a plurality of sense amplifiers and an output buffer is also synchronized by protocol conditions. The synchronization circuit further synchronizes the read streams so that an evaluation step is perfomed exclusively on one of the plurality of banks of memory while having a plurality of simultaneous read streams.

Abstract: Bit lines formed from a first metal wiring layer and bit lines formed from a second metal wiring layer are provided as bit lines that intersect with word lines. The bit lines are formed from metal wiring layers and are divided into two layers so that the pitch of the bit lines can be widened. Thereby, a non-volatile semiconductor memory device having an increased access speed while maintaining production yield can be implemented.

Abstract: A flash memory device that has a global and local bit line design that enables an alternate bit line stress mode as well as a way to detect short circuits in local and global bit lines with a single alternate bit line program. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a control gate and is coupled between one of the local bit lines in each set of local bit lines and one of the global bit lines. Thus, each local bit line in each set of local bit lines is coupled to a different global bit line. Multiple select lines are used to activate the control gates on the select transistors. Each select line is coupled to the control gates on associated select transistors. The associated select transistors are select transistors that are coupled to the local bit lines in an associated set of local bit lines.

Abstract: A semiconductor memory device includes an advanced prefetching block for prefetching more bit data at once and effectively arranging the prefetched data so as to reduce an address access time of the semiconductor memory device. The semiconductor memory device having four pipelining latches for prefetching 4-bit data outputted from at least one bank in response to a start address of the 4-bit data and control signals includes a first data multiplexing unit, a second data multiplexing unit, a third order multiplexing unit and a forth order multiplexing unit.

Abstract: The invention provides method and apparatus to reduce access time in synchronous FIFOs with zero latency overheads. The FIFO buffer includes a FIFO circuit capable of storing ‘n’ data words, each ‘m’ bits wide, having an ‘m’ bit wide data input terminal. Furthermore, the FIFO buffer includes a read data set selection circuit connected to the data output terminals of the FIFO circuit and having two data output terminals providing simultaneous access to a selected storage location at an odd address and an even address. An odd read pointer generating circuit provides the selection input to the data selection circuit for selecting data at an odd read address of the read data selection circuit, while an even read pointer generating circuit provides the input for selecting data at an even read address. A multiplexer coupled to each of the two data output terminals of the read data set selection circuit selects one of its outputs as the final output of the FIFO.

Abstract: A DDR and QDR converter and an interface, a motherboard and a memory module interface using the same. The DDR and QDR converter has a QDR interface, a DDR interface and a conversion core. The QDR interface is used to exchange a signal with QDR devices. The DDR interface is used to exchange a signal with DDR devices. The conversion core is used to convert QDR command and data formats into DDR command and data formats, and to convert DDR command and data formats into QDR command and data formats.

Abstract: An apparatus for outputting burst read data is disclosed which divides input data into an odd number data group and an even number data group, selects a data group including a bit to be first outputted and synchronizes the data group including the bit at rising edges of a clock signal and a data group not including the bit at falling edges of a clock signal, thereby continuously outputting burst read data at a high speed according to output mode set in mode register set using sequential or interleave modes.

Abstract: The present relief module equipped random access memory avoids the need for enforced idle cycles for the processors, thereby enabling the State Machine to operate at its maximum speed. This relief module equipped random access memory also enables the Central Processing Unit to access the data in the single-port Random Access Memory as required to read and write the data contained therein. This is accomplished by the addition of a single-port Random Access Memory module to the plurality of Random Access Memory modules that are typically specified for a particular application. The extra Random Access Memory module alternates its output with each of the others of the plurality of Random Access Memory modules, on a sequential basis, thereby providing effectively extra clock cycles for each Random Access Memory module.

Abstract: A semiconductor memory device has a memory cell array which includes memory cells arranged in a matrix form, word lines, bit lines, a decoding circuit and sense unit. The decoding circuit is supplied with an address signal and a first control signal and drives a selected word line which is the word line specified by the address signal or an adjacent word line which is the word line adjacent to the selected word line on the basis of the first control signal. The sense unit is connected to the bit line and reads data stored in the memory cell which is connected to the word line driven by the decoding circuit.

Abstract: A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

Abstract: In a packetized memory device, row and column address paths receive row and column addresses from an address capture circuit. Each of the row and column address paths includes a respective address latch that latches the row or column address from the address capture circuitry, thereby freeing the address capture circuitry to capture a subsequent address. The latched row and column addresses are then provided to a combining circuit. Additionally, redundant row and column circuits receive these latched addresses and indicate to the combining circuit whether or not to substitute a redundant row. The combining circuit, responsive to a strobe then transfers the redundant row address or latched row address to a decoder to activate the array.

Abstract: The period of time required for a parallel test can be shortened by widening the application range of the parallel test. In the semiconductor memory device having memory cell portions, there are provided a column controller that simultaneously activates a plurality of columns which are subject to degenerate substitution in a column redundant substitution; and a data read-out circuit that simultaneously reads out the data from a plurality of memory cells as selected by the above plurality of columns.

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks each including a plurality of partial blocks, a plurality of global word lines, and odd-numbered and even-numbered sub word lines corresponding to each of the plurality of the global word lines, the odd-numbered sub word lines of each of odd-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the odd-numbered sub word lines of each of the previous neighboring partial blocks, the even-numbered sub word lines of each of the odd-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the even-numbered sub word lines of each of the next neighboring partial blocks, the odd-numbered sub word lines of each of even-numbered partial blocks among the plurality of the partial blocks, respectively, connected to the odd-numbered sub word lines of each of the next neighboring partial blocks, the even-numbered sub word lines of each of the even-numbered partial blocks

Abstract: A network processing device intelligently interleaves packets for read and write access requests in a multibank memory. The system intelligently writes packets into the different memory banks so that the same memory bank is not used for back-to-back packet reads. The last memory bank write is determined for each output queue. This write information is used in combination with look ahead packet read information for a group of packets from the next output queue scheduled to read packets from memory. The scheduler uses all this information to avoid any back-to-back packet read, write, or read/write accesses to the same memory bank. This intelligent packet interleaving scheme preserves memory bus bandwidth normally wasted accessing the same memory banks.

Abstract: A semiconductor memory device capable of preventing coupling noise being generated between adjacent bit lines in different columns. The device comprises first and second columns, wherein each column comprises a pair of bit lines, and wherein the first and second columns are adjacent, first and second sense amplifiers, each being connected to the bit lines of the first or second column, for sensing and amplifying a voltage difference between the bit lines of the first or second column, and a control circuit for controlling the first and second sense amplifiers. When the voltages of adjacent bit lines of the first and second columns transition in an opposite direction during a read operation, the control circuit controls the first and second sense amplifiers to concurrently amplify the voltages of the adjacent bit lines.

Abstract: A semiconductor memory device is organized in such a way that undesirable interference and cross-coupling between various signals generated during operation of the device is minimized. The semiconductor memory device comprises an array of rows and columns of memory cells organized logically and physically into a plurality of sub-arrays. Within each sub-array, the memory cells are organized logically and physically into a plurality of dependent, interleaved banks of memory cells. The banks of memory cells, in turn, each comprise a plurality of memory cores comprising a plurality of memory cells. The memory cores are arranged in such a way as to define a plurality of substantially elongate, orthogonal “stripes” therebetween. Row decoder circuitry for selecting a specified row of memory cells is disposed along the stripes extending in a first direction.

Abstract: An apparatus and method are provided for transmitting data using synchronous dynamic random access memory (SDRAM). In example, the method includes writes data using a first set of SDRAM banks. Data is written using a second set of SDRAM banks, wherein the first set of SDRAM banks and the second set of SDRAM banks write interleaved, Data is read using a third set of SDRAM banks. Data is read using a fourth set of SDRAM banks, wherein the fourth set of SDRAM banks and the third set of SDRAM banks read interleaved.

Abstract: A system and method is provided for bit line sharing in a memory device. Adjacent memory cells are configured to share a bit line and are accessed with separate word lines as an odd and even plane. Bit line sharing reduces the number of Y-multiplexors and I/O circuitry required by about two-fold, and provides power savings by reducing the number of bit lines pre-charged.

Abstract: A memory and method for accessing data in a memory which uses non redundant-form address decoders is disclosed. Lines in subarrays of the memory are selected using the redundant-form addresses. The least significant bit of the non redundant-form address is used to select between these lines. The compare function of the cache memory is then done with a non redundant-form address.

Abstract: A synchronous memory device includes a prefetch address counter. The address counter is composed of an n number of one-bit counter circuits, an n number of adders to which the output signals of these counters are supplied respectively, and an adder control circuit for controlling each adder. A start address is externally supplied to each of the one-bit counter circuits, which in turn count up. When the addressing mode is the sequential mode and the start address is an odd address, each adder performs addition according to the state of the even control signal outputted from the adder control circuit. With the addition, the address outputted from each one-bit counter circuit is inverted, but otherwise the same signal as the address outputted from each one-bit counter circuit is outputted.

Abstract: First and second pre-processing flip-flops latch a command/address signal inputted to a register by a clock having a frequency of ½ of an external clock signal and an inverse clock thereof. Thus, the command/address signal is decomprossed to a set of signals which temporarily has two times. For example, one of the set of signals has only data contents of an odd-th command/address signal, and the other has only data contents of an even-th command/address signal. Since the set of signals has twice periods of the command/address signal, first and second post-processing flip-flop can latch signals in accordance with an internal clock signal generated by a delay locked loop circuit in a state in which a set-up time and a hold time are sufficiently assured.

Abstract: A content addressable memory (CAM) device according to the present invention is configured with binary CAM cells capable of holding binary data “0” and “1”, and is capable of being used either as a binary CAM device with the binary CAM cells being used as binary CAM cells or as a ternary CAM device with the binary CAM cells being used as ternary CAM cells capable of holding ternary data in a way in which, in each pair of two bits of the binary CAM cells, three states, “0,” “1,” and “X (don't care)” are assigned to four states, “00,” “01,” “10,” and “11,” expressed by two-bit data stored in the pair.

Abstract: A virtual ground array includes memory elements, select transistors, select lines connected with the select transistors, word lines, global bit lines and local bit lines connecting the select transistors with the memory elements, wherein each of the memory elements has a source and a drain, the virtual ground array is operative to select a set of memory elements and to fix the drains of the set of memory elements to a predetermined potential, the word lines and at least two of the select transistors select the set of memory elements and the global bit lines connect the select transistors to source and drain power supplies.

Abstract: A non-volatile semiconductor memory device includes a plurality of page buffers, each corresponding to a sense node. Voltages of a first set of sense nodes are varied according to states of corresponding memory cells during a first sense period, while voltages of a second set of sense nodes are fixed at a predetermined voltage. During the second sense period, voltages of the second set of sense nodes are varied according to states of corresponding memory cells, while voltages of the first set of sense nodes are fixed at a predetermined voltage. Using this sensing scheme, even though a sense node corresponding to an OFF cell is floated, a voltage of the floated sense node is not coupled down when a voltage of a neighboring sense node corresponding to an ON cell is lowered.

Abstract: A reset circuit in a memory device applies a reset to the global X-address latch and the local X-address latch. This resets those latches and effectively de-addresses all word lines prior to application of the next address. This eliminates any overlap of main word line signals between successive addresses thereby eliminating a possible glitch that would cause simultaneous word line addressing and potentially a memory read or write error. By terminating the addressing, the address cycle time may be reduced.

Abstract: An ultrasonic inspection apparatus obtains information on the interface of a sample as digital waveform data for any “unit measurement range” and is provided with at least two data memories and controlled by a scan state monitoring signal showing the scan state of a unit measurement range belonging to a first group or a unit measurement range belonging to a second group. A comparator-register/memory-control-circuit outputs the scan state monitoring signal to the two data memories. The operating states of the two data memories being controlled by the scan state monitoring signal to alternate between writing of digital waveform data and readout of digital waveform data.

Abstract: A decoding system which is arranged to perform a plural-stage process in determining which of the driver lines to stimulate in response to each electrode address value supplied to the decoder. This enables the network configuration of the impedances to be machine generated, and also enables the decoder to calculate on the fly which driver lines to stimulate in response to each address value. Furthermore, different resolutions may be provided to enable groups of the electrodes to be addressed simultaneously. Such a decoder arrangement may also be used with an electrode arrangement in which each electrode is connected to only two of the driver lines, in order to achieve addressing schemes in which up to t consecutive electrodes can be driven simultaneously. The invention is applicable, for example, to liquid crystal displays, arrays of memory elements and arrays of sensors such as light-sensors.

Abstract: A semiconductor memory device includes: a memory cell region having main virtual ground lines; and a reference cell region having reference virtual ground lines, and the reference cell region having substantially the same interconnection routine as said memory cell region, wherein, in said reference cell region, adjacent reference cells to a selected reference cell to be referred are off-bit cells.

Abstract: Two types of command interval specifications are defined as first and second command interval specifications. The first command interval specifications is defined as the relationship between a preceding command and a following command that are issued for the same bank, while the second command interval specifications is defined as the relationship between a preceding command and a following command that are issued for different banks, respectively. As for the second command interval specification, since target banks are different between a preceding command and a following command, the following command is executed during the column circuits precharge after the preceding command. Therefore, in the case of the second command interval specification, a command interval is substantially shortened. In addition, pairs of banks are defined as bank pairs, and are applied the first and second command interval specifications, so that the DRAM device is small-sized.

Abstract: A chip-multiprocessing system with scalable architecture, including on a single chip: a plurality of processor cores; a two-level cache hierarchy; an intra-chip switch; one or more memory controllers; a cache coherence protocol; one or more coherence protocol engines; and an interconnect subsystem. The two-level cache hierarchy includes first level and second level caches. In particular, the first level caches include a pair of instruction and data caches for, and private to, each processor core. The second level cache has a relaxed inclusion property, the second-level cache being logically shared by the plurality of processor cores. Each of the plurality of processor cores is capable of executing an instruction set of the ALPHA™ processing core. The scalable architecture of the chip-multiprocessing system is targeted at parallel commercial workloads.

Abstract: An apparatus and method for accessing data in a processing system are described. The system includes multiple processing elements for executing program instructions. The processing system can be a single instruction stream, multiple data stream (SIMD) system, and the processing elements can be the multiple data paths of the SIMD system. Each processing element or data path is associated with an identifying value which distinguishes it from the other elements. A memory, which can be configured as an interleaved memory including multiple memory banks, stores data accessed by the processing elements. The data can be a table used for table look-ups for such functions as mathematical operations. Also, multiple copies of the table can be stored in multiple respective banks of the memory. An instruction calling for a memory access such as a table look-up is received. The instruction contains address information which can be a starting address of a table in memory.

Abstract: A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells, a decode circuit configured to decode address data as input thereto to select a memory cell from the memory cell array, and a data sense circuit configured to detect and amplify the data of the selected memory cell of the memory cell array. The memory cell array includes an initial setup data region with initial setup data and status data being programmed thereinto. The initial setup data is used for determination of memory operating conditions, and the status data indicates whether the initial setup data region is presently normal or not in functionality.

Abstract: In a semiconductor memory, memory banks each having memory cells are arranged in X and Y directions. Each of the memory banks include a Y decoder for selecting Y-direction addresses of the memory cells and an X decoder for selecting X-direction addresses of the memory cells, predicated on a memory having memory banks operable independent from one another. Items of data specified by a specified number of continuous X addresses and having the same Y addresses are successively written into or read from the memory cells arranged in the X direction, which are specified by X addresses corresponding to 1+knth (where k=0, 1, 2 . . . ) in one of the banks. After all the data have been written into or read from the specified memory cells, the corresponding data are successively written into or read from the memory cells specified by X addresses corresponding to 2+knth in another one of the banks.

Abstract: The present invention is a decoder for control gate lines of a twin MONOS flash memory array. Decoder units connected to each control gate line of the memory are controlled to provide select, override and unselect voltages to perform read, program and erase operations. The decoder units are divided into odd and even addressing where separate voltages can be applied control gates of to adjacent memory cells. Override voltages, which prevent operations of a selected cell from affecting adjacent memory cell storage sites, can be applied to the control gates of immediate neighboring cells of the selected sell. Unselected voltages can be applied to beyond the immediate neighboring cells to further prevent disturb conditions in remote cells.

Abstract: A semiconductor memory device (10) having a normal mode of operation and a test mode of operation is provided. The semiconductor memory device (10) can include a plurality of banks (100A to 100D). A bank (100A) may have a plurality of plates (PLT). In the normal mode of operation a row of plates (11020, 11021, . . . 11027) may be activated. In the test mode of operation, half of the row of plates (11020, 11021, . . . 11027) may be activated.

Abstract: A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.