Abstract: In the present invention a bit line decoder circuit a method of selecting bit lines for read and program operations is described for a twin MONOS memory cell array. A block of twin MONOS memory cells is partitioned into sub-blocks wherein decode signals select bit lines to be read and programmed, and select adjacent bit lines to provide bias for the read and program operations. The bit lines are partitioned into even and odd addresses within each sub-block, and an even and odd address sub-block selector connects the selected bit line along with adjacent bit lines to sense amplifiers and memory chip I/O.

Abstract: In the present invention a twin MONOS metal bit line array is read and programmed using a three dimensional programming method with X, Y and Z dimensions. The word line address is the X address. The control gate line address is a function of the X and Z addresses, and the bit line address is a function of the Y and Z addresses. Because the bit lines and the control gate lines of the memory array are orthogonal a single cell can be erased with an adjacent memory, having the same selected bit and control gate lines, being inhibited from erase by application of the proper voltages to unselected word, control gate and bit lines.

Abstract: A read data synchronization circuit for use in a Double Data Rate (DDR) memory system is provided. The read data synchronization circuit provides programmable timing signals for use in synchronizing read data.

Abstract: An improved memory device employs a DRAM array for data storage. In the device, a special row address decoder simultaneously asserts a corresponding unique pair of the wordlines in response to each received valid row address, so that a single valid row address simultaneously accesses two rows of memory cells in the array. The device differentially writes and reads each bit of data across a pair of memory cells; each one of the pair of memory cells being within a different respective row of the array, and the two different rows together corresponding to one of the unique pairs of wordlines asserted by the row address decoder responsive to a valid row address. This arrangement obviates the need for high voltage boosting circuits and thereby reduces power consumption.

Abstract: A semiconductor memory architecture having two memory banks each containing respective memory locations, and for each memory bank, respective circuits for selecting the locations of the bank and respective circuits for reading the data contained in the selected locations of the bank, a structure for the transfer of the data read by the reading circuits associated with the memory banks to data output terminals of the memory, there being a single data-transfer structure assigned selectively to one memory bank at a time and which includes storage for storing the most recent datum read by the reading circuits, and output driver circuits activated selectively in order to transfer the contents of the registers to the data output terminals of the memory, an addressing structure having, for each memory bank, and a respective circuit for the sequential scanning of the memory locations of the bank, operatively connected to the respective circuits for selecting the locations of the memory bank.

Abstract: A memory interface (15) and method of use implements a cache (14) bursting addressing technique which begins a read of main memory (16) in a wrap around mode before automatically switching into a linear addressing mode. The use of two modes which automatically change eliminates an access delay to the main memory when switching modes and optimizes system performance by providing a most critical word first in a first cache line fill and advancing to a sequential address following the first cache line. The sequential address has a higher probability of next use by the processor than any other address. The automatic mode change may be overridden by the memory interface.

Abstract: A double pitched array includes isolation devices to divide the array into subarrays, using the same space which is used for bit line twists. This addition allows the one-fourth of the bit line pair which will not be used to propagate signals to not be charged during a memory operation.

Abstract: An apparatus for selecting banks in a semiconductor memory device provides a half-chip by adjusting all bits including the most significant bit (MSB) of bank addresses to select normal banks even if degraded banks are included in both upper and lower bank blocks. In a memory including an upper bank block and a lower bank block which are constructed with a plurality of banks selectable by a plurality of bank addresses, an apparatus for selecting the banks includes a plurality of bank address control parts each corresponding to one address bit of the bank addresses, each of the bank address control part applying a fixed logic value to the upper and lower bank blocks according to a selective cutting of at least one of the fuses, and each of the bank address control parts applying either a corresponding bank address bit input thereto or a bank address bit just below the corresponding bank address bit to the upper and lower bank blocks.

Abstract: A method and apparatus for performing a block-write to a memory device comprising at least one register, a data input port, at least one memory bank, and a hardware device to block-write data from the register to the memory device, including receiving a first portion of block-write data from a data bus during a first half of a clock cycle; then, producing a second portion of the block-write data, and block-writing the first and second portions of the block-write data from a write logic unit to the memory bank at a double data rate as determined by the clock cycle.

Abstract: A timing and control structure for a memory, including the timing and control structure includes a first circuit that can recognize, on the basis of control signals supplied to the memory from the exterior, whether a random-access reading is to be executed, the control signals including a first control signal indicative of the presence of an address supplied to the memory from the exterior, and a second control signal that, upon switching edges of a first type, supplies to the control and timing structure a time base for the execution of the random-access readings and, upon switching edges of a second type, supplies a time base for the execution of the sequential readings, a second circuit controlled by the first circuit and upon a random-access reading, generates a first synchronism signal in response to a transition of the first type in the second control signal, a third circuit sensitive to transitions of the second type in the second control signal and which can generate a second synchronism signal upon t

Abstract: A memory array having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store “1” and “0” bits. For such a memory array both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory-cells are accessed for each row address so that each “1” or “0” bit is stored as an electric charge in at least two memory cells. By grouping enough memory cells together in this manner to store each “1” and “0” bit, the grouped memory cells are able to retain a sufficient total electric charge as a group to properly store each bit even when individual memory cells in the group are unable to do so.

Abstract: A method and apparatus for testing memory devices. One embodiment provides a method including receiving a first input data bit having a first polarity, and receiving a second input data bit having a second polarity, wherein the second polarity is the complement of the first polarity. The method also includes writing the first input data bit to a first portion of a plurality of memory cells, writing the second input data bit to a second portion of a plurality of memory cells, and reading data bits from the first and second portions of the plurality of memory cells. An active signal is generated if the data bits read from the first portion of the plurality of memory cells and complements of the data bits read from the second portion of the plurality of memory cells each have the same polarity.

Abstract: An internal addressing structure for a semiconductor memory with at least two memory banks, includes a counter associated for operation with each memory bank and capable of generating sequences of digital codes for addressing locations in the corresponding bank, a first circuit for causing a selective updating of the counters, a second circuit for loading into the counters a common initial digital code, forming part of an initial address supplied to the memory from the outside through an addressing line bus, corresponding to an initial memory location, and a third circuit capable of detecting a first signal, supplied to the memory from the outside and indicating the presence of a digital code on the bus, to cause the common initial digital code to be loaded into the counters.

Abstract: A memory array includes a first plurality of metal bit lines, a second plurality of diffusion bit lines and a third plurality of select transistors. There are more than two diffusion bit lines per metal bit line.

Abstract: A semiconductor memory device includes control circuits for respectively controlling operation timings of respective sense amplifiers related to an odd-numbered bit line pair and related to an even-numbered bit line pair. The control circuits thus allow respective sense amplifiers provided for bit line pairs adjacent to each other to operate at different timings respectively.

Abstract: Integrated circuit memory devices include first and second memory banks, first and second local data lines electrically coupled to the first and second memory banks, respectively, and a multiplexer having first and second inputs electrically coupled to first and second data bus lines, respectively. A data selection circuit is also provided which routes data from the first and second local data lines to the first and second data bus lines, respectively, when a selection control signal is in a first logic state and routes data from the second and first local data lines to the first and second data bus lines, respectively, when a selection control signal is in a second logic state opposite the first logic state. A control signal generator is also provided. This control signal generator generates the selection control signal in the first and second logic states when a first address in a string of burst addresses is even and odd, respectively.

Abstract: A redundancy architecture for a memory includes an array of memory cells divided into at least a pair of semi-arrays that are singularly addressable. Each semi-array is organized into rows and columns. The redundancy architecture includes a number of packets each including redundancy columns. The packets are divided into two subsets of packets. Each packet is addressable independently from the other by respective address circuits. Each packet also provides redundancy columns exclusively for a respective semi-array.

Abstract: A semiconductor memory device has a column address decoder which includes first and second pre-decoders corresponding to high-order and low-order addresses, respectively, a shift register for using the output signal of the second pre-decoder as an initial value, and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal through the output circuit. The shift register includes a first shift register for an even address and a second shift register for an odd address and forms two sets of continuous select signals of the bit lines, as composed of a sequential action and an interleave action, on the basis of the initial value by combining its up and down shifting actions.

Abstract: An interleaved memory having an interleaved data path includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells, first and second arrays of sense amplifiers respectively coupled to the first and second bank of memory cells, and first and second read registers respectively coupled to the first and second arrays of sense amplifiers. A control and timing circuit is connected to the first and second arrays of sense amplifiers and has inputs for receiving externally generated command signals, and outputs for providing path selection signals and a control signal. A third register is connected to the first and second read registers and has inputs for receiving read data therein as a function of the path selection signals. An array of pass-gates are connected to the third register and are controlled in common by the control signal for enabling a transfer of the read data stored in the third register to an array of output buffers.

Abstract: An improved memory card and its use in a computer system is provided. The computer system has a system bus which provides requests from a CPU to a memory controller, which then provides signals to the memory card or module or a memory bus. The memory card is provided with first and second banks of DRAMs, a memory card bus and a DSP. Logic circuitry including a memory card data bus controller provides communication of the DSP with the banks of DRAM chips. Logic circuitry is also provided which can selectively connect the DSP to either the first or second bank of DRAMs and selectively connect the memory bus with the other bank of DRAMs or with both banks of DRAMs. Hence when the CPU is accessing one bank of DRAMS the DSP can access the other bank of DRAMs thus allowing the DSP to function utilizing the bank of DRAMs not being accessed by the memory bus to service the CPU or some I/O device.

Abstract: The present invention relates to a semiconductor memory having a pre-fetch structure. In such memory, an odd address cell array is provided with an odd address redundant cell array, and an even address cell array is provided with an even address redundant cell array, firstly, the present invention comprises a redundant memory, which stores an odd redundant address and an even redundant address, together with odd and even selection data. Since redundant memory is used flexibly on the odd side and even side, it is possible to maintain a high relief probability even when redundant memory capacity is reduced.

Abstract: A dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM), having a full-page increment/decrement burst mode. In one embodiment, the DDR SDRAM/SGRAM includes a memory array and a logic circuitry coupled thereto. The memory array is addressable by even and odd word addresses. The logic circuitry has a burst increment mode to access the array starting at an even word address and a burst decrement mode to access the array starting at an odd word address.

Abstract: An interleaved memory includes an array of memory cells divided into a first bank of memory cells and a second bank of memory cells. The interleaved memory operates in a burst access mode. A first address counter is coupled to the first bank of memory cells, and an address register is coupled to the first address counter and to the second bank of memory cells. A timing circuit generates increment pulses to the first address counter so that a first random access asynchronous read cycle starts with the first bank of memory cells. A function of an address counter for the second bank of memory cells is being performed by coping contents of the first address counter to the address register.

Abstract: In this invention a double data rate (DDR) DRAM is read and written with data coherence. The data is in the form of a data burst either interleaved or sequential and of any length. The data is read from the DDR DRAM depending on whether the starting address is even or odd and taking into consideration CAS latency. Both edges of the clock are used to transfer data in and out of the DDR DRAM. To write data only the starting address of the data burst is used to maintain data coherence. Data coherence is assured by a write followed by a read of the same data to and from the same memory cell.

Abstract: The inventive mechanism determines whether memory source and destination addresses map to the same or nearly the same cache address. If they map to different addresses, then loads and stores are ordered so that loads to one cache bank are performed on the same clock cycles as the stores to another cache bank. After a group of loads and stores are completed, then load and store operations for each bank are switched. If the source and destination addresses map to nearly the same cache address and if the source address is prior to the destination address, then a group of cache lines is loaded into registers and stored to memory without any interleaving of other loads and stores. If the source and destination addresses map to the same cache location, then an initial load of data into registers is performed. After that, additional loads are interleaved with non-cache conflicting stores to move new values into memory. Thus, loads and stores to matching cache addresses are separated by time.

Abstract: A computer memory system provides a double data rate (DDR) memory output while requiring memory chips with only half the frequency limit of the prior art DDR memory chips. The system contains a first memory bank having data lines and a second memory bank having data lines. The first and second memory banks are associated with first and second clock signals, respectively, where the second clock signal is delayed from the first clock signal such that the data lines of the first memory bank are connected to a data bus in synchronism with the first clock signal while the data lines of the second memory bank are connected with the data bus in synchronism with the second clock signal. In one embodiment, a first FET switch connects the data lines of the first memory bank with the data bus and a second FET switch connects the data lines of the second memory bank with the data bus.

Abstract: A DRAM array is repairable when the array includes memory cells that are defective because their storage capacitors are unable to retain a sufficient electric charge to properly store “1” and “0” bits. To repair the array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each “1” or “0” bit is stored as an electric charge in at least two memory cells. By grouping enough memory cells together in this manner to store each “1” and “0” bit, the grouped memory cells are able to retain a sufficient total electric charge as a group to properly store each bit even when individual memory cells in the group are unable to do so.

Abstract: The integrated memory has a first address path, via which the address terminals are connected to first selection lines of a first group and which has corresponding first lines and a first decoder circuit. In addition, the integrated memory has a second address path, via which the address terminals are connected to first selection lines of a second group and which has corresponding second lines and a second decoder circuit. The first decoder circuit is faster than the second decoder circuit. The first lines have a longer signal propagation time than the second lines.

Abstract: A memory control apparatus according to the invention is interposed between a central processing unit and a memory device to store data and has: a channel control unit to control a data transfer to/from the central processing unit; a drive control unit to control a data transfer to/from the memory device; a plurality of cache memories to temporarily store the data which is transferred between the central processing unit and the memory device; and a cache memory control unit having selecting means for selecting the cache memory to store the data which is transferred from the memory device. The memory control apparatus selects the cache memory to store the data so as to almost equalize use amounts in the plurality of cache memories, thereby controlling the allocation of the cache memories and enabling a cache memory space to be effectively used.

Abstract: A flat memory cell read only memory is disclosed. A flat cell ROM array is formed on a substrate. This array is formed by a plurality of sub-arrays. In each sub-array, a plurality of first buried diffusion regions are planted into the substrate. A insulating layer covers on the substrate. A plurality of wordlines and metal bitlines are formed on the insulating layer. The wordlines are vertically buried to the diffusion region. A flat FET array is installed in a section between the lower sides of two adjacent buried diffusion regions and word lines. Four block selecting lines are used to control the selection of the memory cell selecting transistors for reading a selecting memory cell. Commonly used metal bitlines and transistors of a minimum number are used to read data. Therefore, it has the advantages of rapidly reading, small size, high density and lower power consumption.

Abstract: An integrated device includes an external memory interface that includes address decoding logic configured for identifying a destination device register based on register address information retrieved from an external memory. The external memory interface, upon identifying the destination device register, loads the destination device register with register data read from the external memory, for example contiguously following the corresponding register address information. Hence, the integrated device can be programmed on a per register basis, without the necessity of an EEPROM map.

Abstract: A memory array includes a memory unit and a dual access controller. The memory unit stores a multiplicity of words and has a plurality of word lines each of which accesses a row of words. The memory unit is divided into a left memory unit and a right memory unit, each having generally half of the storage space of the memory unit, the left memory unit having left half word lines and the right memory unit having right half word lines. The dual access controller receives a word address N and a word separation amount S and activates the columns and half rows of the memory unit in which a main word and a second word S words from the main word are found. In one embodiment useful for neighboring words, the left memory unit holds the words with even addresses and the right memory unit holds the words with odd addresses. In another embodiment, the left memory unit holds the first four words of an eight word set and the right memory unit holds the second four words.

Abstract: 1. An apparatus for outputting data included in a synchronous memory device includes: first storage unit for storing in sequence even data provided by a first sense amplifier coupled to a selected even bank; second storage unit for storing odd data in sequence provided by a second sense amplifier coupled to a selected odd bank; selection unit coupled to the first storage unit and the second storage unit, for receiving at the same time both the even data and the odd data; third storage unit for storing and providing one of both the even data and the odd data in synchronization with a rising edge of a clock signal; fourth storage unit for storing and providing one of both the even data and the odd data in synchronization with a falling edge of a clock signal; data output unit for driving data from third storage unit and data from the fourth storage unit.

Abstract: An apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output signals are generally each at either (i) the same logic state or (ii), a don't care state.

Abstract: A semiconductor memory device comprising a test structure is disclosed. The semiconductor device includes a plurality of memory cells, word lines, bit lines, and test pads; the word lines including a first set and a second set of word lines, connected to a first and second word line test pad, respectively; the bit lines including a first set and a second set of bit lines, connected to a first and second bit line test pad, respectively. The first set of word lines and the first set of bit lines access a first set of memory cells, the first set of word lines and the second set of bit lines access a second set of memory cells, the second set of word lines and the first set of bit lines access a third set of memory cells, and the second set of word lines and the second set of bit lines access a fourth set of memory cells.

Abstract: A DDR-SDRAM has a plurality of banks of memory cells, one of which is selectively activated at a time. Each bank includes two memory cell plates, each of which is juxtaposed with a corresponding memory cell plate in another of the bank to form a memory cell plate pair for sharing an I/O amplifiers and a branch line of power source line. The number of I/O amplifiers and the width of the branch line can be reduced because the both of the memory cell plate pair are not activated at a time.

Abstract: A method is described for interleaving bank and page access to a multibank memory device, such as an SDRAM or SLDRAM. An address detector detects a pending page access, and the associated data transfer request is then stored in a page hit register. A control timing chain includes a rank register queue with a bank access input, a page write input, and a page read input. Comparator circuitry provides bank address comparisons to avoid bank conflicts and to control the timing of insertion of the page hit register contents into the appropriate page write or page read input. While a pending page access request is stored in the page hit register, other pending bank access operations can be initiated. Consequently, bank and page accesses can be interleaved in substantially contiguous command cycles, and data transfer bandwidth is correspondingly improved.

Abstract: A semiconductor memory device has a column address decoder which includes first and second pre-decoders corresponding to high-order and low-order addresses, respectively, a shift register for using the output signal of the second pre-decoder as an initial value, and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal through the output circuit. The shift register includes a first shift register for an even address and a second shift register for an odd address and forms two sets of continuous select signals of the bit lines, as composed of a sequential action and an interleave action, on the basis of the initial value by combining its up and down shifting actions.

Abstract: A quad data rate RAM (100) in accordance with the invention is a burst synchronous RAM with separate data buses (Data-In, Data-Out) for read and write data. Data can be transferred on both buses and on both the rising and the falling edge of the clock (CLK). Operating at the maximum throughput, four data items are transferred per clock cycle. In one embodiment, data is written to or read from the RAM in bursts of four data items. The RAM includes four independent internal RAM blocks (44-47). in a write burst, (i) a write address, (ii) control signal(s), and (iii) four write data items are sequentially presented to the respective four internal RAM blocks at the respective four clock edges of two consecutive clock cycles. A read burst is carried out similar to a write burst except that there is a one clock cycle latency between the four read data items and the burst address.

Abstract: A circuit transfers data in an array of memory cells arranged in rows and columns. The circuit includes a plurality of row lines, a plurality of pairs of complementary digit lines, and an array of memory cells, each memory cell having a control terminal coupled to one of the row lines and a data terminal coupled to one of the complementary digit lines of one of the pairs of complementary digit lines responsive to a row enable signal on the row line of the row corresponding to the memory cell. A plurality of sense amplifiers are included in the circuit, each sense amplifier coupled to an associated pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and, in response to the sensed voltage differential, drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states.

Abstract: In a burst operation, a counter receives one or more bits of a starting column address. The count signal generated by the counter is provided to column decoders. The column decoders select two columns in response to a single value of the count signal. The two columns can be at non-consecutive column addresses. Alternatively, the two columns can be at consecutive column addresses starting at an odd column address boundary. Data are transferred between the two columns and a buffer in parallel. Data are transferred between the buffer and a data terminal serially. Some embodiments are suitable for burst operations defined by standards for synchronous dynamic random access memories.

Abstract: A graphics subsystem having a dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM), which has a full-page increment/decrement burst mode. In one embodiment, the DDR SDRAM/SGRAM includes a memory array and a logic circuitry coupled thereto. The graphics subsystem may be formed on a single semiconductor chip. The memory array is addressable by even and odd word addresses. The logic circuitry has a burst increment mode to access the array starting at an even word address and a burst decrement mode to access the array starting at an odd word address.

Abstract: In the present invention a bit line precharge circuit is used to prevent errors from a write operation in memory cells adjacent to the column being written. The precharge circuits are enabled by write enable and selected by the Y decoder in such a way that only precharge circuits on bit lines adjacent to the active bit lines in a write operation are activated. All other precharge circuits on bit lines more remote than immediately adjacent bit lines are not activated and thus saving power during a write operation.

Abstract: An interleaved memory is readable in a sequential access synchronous mode and in a random access asynchronous mode based upon externally generated command signals including an address latch enabling signal and a chip enable signal. The memory includes a circuit for regenerating the externally generated address latch enabling signal. A first and a second internal replica signal are generated by the circuit. The second internal replica signal has a leading edge that is delayed with respect to a leading edge of the first internal replica signal. A duration of the second internal replica signal is conditionally incremented to prevent non-synchronization between the externally generated address latch enabling signal and the externally generated chip enable signal when the interleaved memory is operating in the sequential access synchronous mode or in the random access asynchronous mode.

Abstract: An integrated circuit memory device including at least one memory bank with the memory bank being logically partitioned into even and odd portions thereof. Even and odd data buses are provided which are selectively couplable to the even and odd portions of the memory banks respectively for placing read data thereon by means of corresponding first multiplexers in response to a first control signal. A read pipeline sorting block is coupled to the even and odd data buses for selectively applying the read data on the even data bus to either of a rising or falling edge data output bus and the read data on the odd data bus to an opposite one of the rising or falling edge data output buses.

Abstract: A symmetric memory array includes a multiplicity of repeating segments formed into rows and columns. Each segment includes a cell area formed of four segmented cell bit lines an even select area and an odd select area. The even select area is located at one end of the cell area and includes a segmented even contact bit line and two select transistors connecting the even contact bit line with the even cell bit lines of the segment. The odd select area is located at the opposite end of the cell area and includes a segmented odd contact bit line and two select transistors connecting the odd contact bit line with the odd cell bit lines of the segment. The array additionally includes one even contact connected to the even contact bit lines of two neighboring even select areas, one odd contact connected to the odd contact bit lines of two neighboring odd select areas and alternating even and odd metal lines connecting to the even and odd contacts, respectively.

Abstract: A semiconductor memory device is disclosed that is capable of outputting in the fastest possible time the first of serial data that are read in bursts, despite the increase in capacity of a memory cell array. In this semiconductor memory device, for a single address access, a plurality of bits of serial data are read in a burst from a memory sub-array that is made up by memory cell arrays 11Uo and 11Ue or memory cell arrays 11Le and 11Lo. In order that the serial data that are read first are the data of bit 0 regardless of the operation mode of the semiconductor memory device, each individual memory sub-array is divided between portions for even data and portions for odd data and the even memory cell arrays 11Ue and 11Le in which the data of bit 0 are stored are arranged closer to the data amplifier than the odd memory cell arrays 11Uo and 11Lo. The maximum length of I/O lines that are used in reading even data is therefore about half that of the maximum length of I/O lines that are used in reading odd data.

Abstract: Decoding of addresses in a register file is simplified by reducing the number of bits used for addressing by one. Bits are read from even/odd cell combinations simultaneously, and a reserved address line is driven high. The reserved address line is coupled to each driver corresponding to a storage cell. Individual even cells may also be read. Writing to even/odd cell combinations may be performed in a similar manner. However, when writing, an even write enable line and an odd write enable line are provided to indicate whether an even cell, an odd cell, or an even/odd cell combination should be written to simultaneously. By simplifying the decoding stage, performance of reading and writing tasks may be performed much faster and use less resources.

Abstract: The present invention relates to a semiconductor memory having a pre-fetch structure. In such memory, an odd address cell array is provided with an odd address redundant cell array, and an even address cell array is provided with an even address redundant cell array, firstly, the present invention comprises a redundant memory, which stores an odd redundant address and an even redundant address, together with odd and even selection data. Since redundant memory is used flexibly on the odd side and even side, it is possible to maintain a high relief probability even when redundant memory capacity is reduced.

Abstract: A memory control circuit for writing or reading digital data at a high speed without increasing access speed to the memory circuit. The memory control circuit includes a control signal generation circuit for generating a first write enable signal and a first read enable signal of a first memory circuit, an address generation circuit for generating an address signal designating a data write address of the first memory circuit and a second memory circuit, and a write data supply circuit for supplying write data to the first and second memory circuits. A shift circuit is connected between the control signal generation circuit and the second memory circuit to generate a second write enable signal and a second read enable signal by shifting the first write enable signal and the first read enable signal by one cycle of a data write cycle or read cycle. The write data is written alternately to the first and second memory circuits in response to the first and second write enable signals.