Plural Clock Signals Patents (Class 365/233.11)
  • Patent number: 10395702
    Abstract: A memory device includes a first data driver configured to send a first data according to a first clock signal; a first data port electrically coupled to the first data driver, the first data port configured to receive the first data; a second data driver configured to send a second data according to a second clock signal, wherein the second clock signal does not match the first clock signal; and a second data port electrically coupled to the second data driver, the second data port configured to receive the second data.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jason M. Brown, Vijayakrishna J. Vankayala, Todd A. Dauenbaugh
  • Patent number: 10223303
    Abstract: A computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other, wherein the memory subsystem comprises a memory controller connected to the system bus, the computer system includes an up/down counter for counting a number of access requests and a number of requests other than access requests, a comparator for comparing the count of the up/down counter with a predetermined threshold value stored in a register, and a clock gate circuit for generating clock gate signals to decimate an operating clock of the memory controller in response to the comparison result of the comparator.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Norio Fujita, Masahiro Hori, Masahiro Murakami, Junka Okazawa
  • Patent number: 10169263
    Abstract: A method including estimating an access request frequency from a CPU to a memory subsystem by counting a number of CPU access requests and a number of requests other than CPU access requests, wherein the CPU is connected to the memory subsystem via a system bus, and the memory subsystem includes a memory controller connected to the system bus, and a DDR memory, including the estimated access request frequency with a predetermined threshold value stored in a register, generating a clock gate signal to decimate an operating clock of the memory controller in response to a result of comparing the estimated access request frequency with the predetermined threshold value, generating a dummy cycle signal to delay the timing of signal data output from the memory controller to the system bus, and generating a clock enable signal to decimate an operating clock of the DDR memory.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Norio Fujita, Masahiro Hori, Masahiro Murakami, Junka Okazawa
  • Patent number: 9761282
    Abstract: There are provided a memory system and an operating method thereof. A memory system includes a memory device suitable for storing data therein; and a memory controller suitable for initializing the memory device, or maintaining or changing a mode of the memory device according to power of the memory device during a wake-up operation.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: September 12, 2017
    Assignee: SK Hynix Inc.
    Inventor: Dong Yeob Chun
  • Patent number: 9673798
    Abstract: Systems and methods for generating periodic signals with reduced duty cycle variation are described. In some cases, a calibration procedure may be performed prior to a memory operation (e.g., prior to a read operation or a programming operation) in which a duty cycle correction circuit receives an input signal (e.g., an input clock signal), steps through various delay settings to determine a first delay setting corresponding with a signal high time for the input signal and a second delay setting corresponding with a signal low time for the input signal, generates a delayed version of the input signal corresponding with a mid-point delay setting between the first delay setting and the second delay setting, and generates a corrected signal using the delayed version of the input signal and the input signal.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: June 6, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Tianyu Tang, Venkatesh Ramachandra, Srinivas Rajendra
  • Patent number: 9613687
    Abstract: In one embodiment, the method includes performing a read operation on a memory, and determining, by a memory controller, whether to perform a reliability verification read operation based on a count value and a reference value. The count value is based on a number of read commands issued by the memory controller to the memory, and the reliability verification read operation is for reading data from at least one memory cell associated with at least one unselected word line in the memory. An unselected word line is a word line not selected during the read operation. The method further includes performing the reliability verification read operation for the at least one unselected word line based on the determining.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: April 4, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyungryun Kim, Sangyong Yoon
  • Patent number: 9531364
    Abstract: Apparatuses and methods are directed to preventing duty cycle distortion in an electronic apparatus. The apparatus generally includes a first phase mixer stage configured to interpolate a first and a second input signal to provide a first intermediate signal and further configured to interpolate the second input signal and a third input signal to provide a second intermediate signal, the first phase mixer stage distorting duty cycle in providing the first intermediate signal. The apparatus further includes a second phase mixer stage configured to interpolate the first intermediate signal and the second intermediate signal to provide an output signal and further configured to compensate for duty cycle distortion of the first phase mixer stage.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: December 27, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Yantao Ma, Tyler Gomm
  • Patent number: 9496878
    Abstract: A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: November 15, 2016
    Assignee: SK Hynix Inc.
    Inventors: Hae-Rang Choi, Joo-Hwan Cho, Kwang-Jin Na, Kwan-Dong Kim
  • Patent number: 9479183
    Abstract: A memory storage device having a clock and data recovery circuit module are provided. The module includes sampling circuits, a first logic circuit module, a delay circuit module, a second logic circuit module, a frequency adjustment circuit and a clock control circuit. The sampling circuits sample a data signal according to reference clocks. The first logic circuit module performs a first logic operation according to a sampling result. The delay circuit module delays a result of the first logic operation. The second logic circuit module performs a second logic operation according to said result and the delayed first logic result. The frequency adjustment circuit outputs a frequency adjustment signal according to a result of the second logic operation, and the clock control circuit performs a phase locking accordingly. Therefore, a circuit complexity of the clock and data recovery circuit module may be reduced.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: October 25, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei-Yung Chen, Yu-Chiang Liao
  • Patent number: 9436630
    Abstract: Systems described herein enable PCIe device components to be used with multiple PCIe topologies and with host systems of varying configurations. In some cases, a number of varying PHYs and PCIe cores are utilized to increase the number of applications and/or specifications that may be satisfied with a host interface design. Further, some systems described herein may include a number of synchronizers, clock multiplier units, and selectors to create a host interface that can be configured for a number of applications. Despite increasing the flexibility of the usage of systems disclosed herein, costs can be reduced by using the systems of the present disclosure for PCIe based devices.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: September 6, 2016
    Assignee: Western Digital Technologies, Inc.
    Inventor: Farooq Yousuf
  • Patent number: 9418762
    Abstract: A semiconductor memory device may include: a first fuse set unit suitable for storing a first repair address during a first mode; a second fuse set unit suitable for storing an input address during a second mode; and a comparison unit suitable for comparing the input address with the first repair address, wherein the first fuse set unit is reset when the first repair address is the same as the input address.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: August 16, 2016
    Assignee: SK Hynix Inc.
    Inventor: Jung-Taek You
  • Patent number: 9412428
    Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: August 9, 2016
    Assignee: Rambus Inc.
    Inventors: Thomas Giovannini, Scott Best, Lei Luo, Ian Shaeffer
  • Patent number: 9298666
    Abstract: The invention concerns a circuit comprising: a first circuit block (302) adapted to receive a first clock signal (CLK1) and to provide a first output data signal at a time determined by said first clock signal; a second circuit block (304) adapted to receive a second clock signal (CLK2) and to provide a second output data signal at a time determined by said second clock signal; a clock bus (314) coupled to corresponding outputs of said first and second circuit blocks for receiving a third clock signal (BCLK) based on said first and second clock signals; and a synchronization unit (312) coupled to said clock bus and adapted to sample said first and second output data signals based on said third clock signal.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: March 29, 2016
    Assignee: STMicroelectronics SA
    Inventors: St├ęphane Le Tual, Pratap Singh
  • Patent number: 9263107
    Abstract: A driver circuit includes an output driver including a plurality of output driver legs. The driver circuit further includes a duty cycle adjuster configured to adjust a duty cycle of a signal provided to the output driver. The driver circuit further includes an isolation module configured to isolate at least one output driver leg of the output driver legs from remaining output driver legs of the output driver legs. The driver circuit further includes a duty cycle monitor configured to monitor an output of the at least one output driver leg when the at least one output driver leg is isolated from the remaining output driver legs, and to provide the monitored output to the duty cycle adjuster.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: February 16, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Mark Charles Wayland, Thomas Clark Bryan, Yu Huang, Michael Joseph Brunolli
  • Patent number: 9222976
    Abstract: Various example implementations are directed to circuits and methods for debugging multiple integrated circuit (IC) packages. According to an example implementation, a first logic analyzer in a first IC package determines a latency of a data link. In response to test input data, the first logic analyzer communicates the test input data to a second IC package, via the data link, and captures a first set of data signals from a logic circuit in the first IC package. In response to test input data, a second logic analyzer in the second IC package captures a second set of data signals from a second logic circuit and communicates the second set of data signals to the first logic analyzer circuit via the data link. The first logic analyzer aligns the first and second sets of data signals, based on the determined latency, and outputs the aligned sets of data signals.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: December 29, 2015
    Assignee: XILINX, INC.
    Inventor: Kapil Usgaonkar
  • Patent number: 9172362
    Abstract: A circuit includes a load; a first differential pair coupled to the load and responsive to input data; a second differential pair coupled to the load and responsive to the input data; a third differential pair coupled to the first differential pair and the second differential pair and responsive to a first control signal and a second control signal; a bias circuit configured to pull a node coupled to both the first differential pair and the second differential pair to a predetermined state; and a current source coupled to the third differential pair and the bias circuit.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: October 27, 2015
    Assignee: TEKTRONIX, INC.
    Inventors: John F. Stoops, Daniel G. Knierim
  • Patent number: 9142276
    Abstract: For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: September 22, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Hiroki Fujisawa
  • Patent number: 9104571
    Abstract: A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: August 11, 2015
    Assignee: SK Hynix Inc.
    Inventor: Kie-Bong Ku
  • Patent number: 9047927
    Abstract: Disclosed herein is a device including a timing control circuit that receives a strobe signal supplied from outside to generate an internal strobe signal that is used as a timing signal to latch a data signal. An operation state of the timing control circuit is changed according to temperature change so as to keep an output timing of the internal strobe signal with respect to an input timing of the strobe signal.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: June 2, 2015
    Assignee: PS4 LUXCO S.A.R.L.
    Inventor: Yasuhiro Takai
  • Publication number: 20150146495
    Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 28, 2015
    Inventor: TSUNEO ABE
  • Patent number: 9042189
    Abstract: A semiconductor memory device includes: a burst start signal generation unit configured to generate a first burst start signal by delaying a write pulse by a first period, generate a second burst start signal by delaying the write pulse by a second period, and selectively transmit the first or second burst start signal as a select burst start signal in response to a test signal; an input control signal generation unit configured to generate an input control signal in response to the first burst start signal; and a write command generation unit configured to generate a write driver enable signal in response to the select burst start signal.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: May 26, 2015
    Assignee: SK Hynix Inc.
    Inventor: Yin Jae Lee
  • Patent number: 9036448
    Abstract: A device includes a first clock generation circuit that receives an external clock signal supplied to the device, delays the external clock signal to output a first clock signal synchronized with the external clock signal, and a circuit that generates a control signal to control output of data, based on second clock signals obtained by dividing an internal clock signal generated from the external clock signal, and third clock signals obtained by dividing the first clock signal.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: May 19, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Kyoichi Nagata
  • Publication number: 20150131365
    Abstract: Among other things, one or more techniques or systems for facilitating access operations to a single port memory device are provided. Multiple access operations to a single port memory device, such as a 6 transistor bitcell array of an SPSRAM, are performed during a single clock period of a system clock. In an embodiment, a wrapper controller initiates a first access operation during a first clock period of the system clock based upon a rising edge of the system clock. Responsive to receiving an operation complete signal during the first clock operation, the wrapper controller initiates a second access operation to the single port memory device during the first clock period. In this way, multi-port access functionality is implemented, such as in a serial manner to mitigate operation disturbs, for a single port memory device that occupies a relatively smaller area than a multi-port memory device for improved storage density.
    Type: Application
    Filed: November 13, 2013
    Publication date: May 14, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-jer Hsieh, Chiting Cheng, Chien-Kuo Su, Cheng Hung Lee, Tsung-Yung Jonathan Chang
  • Patent number: 9025411
    Abstract: A semiconductor memory apparatus includes an enable signal generation unit configured to be inputted with a plurality of clocks which have different phases, and generate a plurality of enable signals; and a plurality of sampling units configured to output input data as sampling data in response to respective pairs of clocks of the plurality of clocks and respective ones of the plurality of enable signals.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventors: Ji Seop Song, Chang Kyu Choi
  • Patent number: 9001613
    Abstract: A tracking circuit in a memory macro includes a data line, a first tracking cell, and a plurality of transistors. The first tracking cell is electrically coupled to the data line. The plurality of transistors is electrically coupled to the data line. The plurality of transistors is configured to cause a delay on a transition of a signal of the data line based on a delay current. The signal of the data line is configured for use in generating a signal of a control line of a memory cell of the memory macro.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bing Wang, Kuoyuan (Peter) Hsu
  • Patent number: 8995207
    Abstract: According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: March 31, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Christopher Edward Koob, Jen Tsung Lin, Manojkumar Pyla, Martin Saint-Laurent
  • Patent number: 8988966
    Abstract: A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: March 24, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Jongtae Kwak
  • Publication number: 20150071022
    Abstract: Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active clock signal to a command path for a first portion of a command cycle for a command of back-to-back commands. The command path decodes the command and provides an output command signal responsive to the clock signal. The method further includes providing an inactive clock signal to the command path for a second portion of the command cycle for the command of the back-to-back commands.
    Type: Application
    Filed: September 9, 2013
    Publication date: March 12, 2015
    Applicant: Micron Technology, Inc.
    Inventor: Kallol Mazumder
  • Patent number: 8976619
    Abstract: A semiconductor apparatus includes a phase detecting unit that continuously detects a first delay amount during a read operation, based on a phase difference between an external clock signal and an internal clock signal; a generating unit that generates a second control signal by delaying a first control signal by a second delay amount that when added to the first delay amount, the sum is a specific time period, a valid time period of the first control signal starts when the read operation starts and is at least to equal a read time for one data signal and less than the specific time period that is from the start of the read operation until output of a received data signal; and a delay control unit that delays the data signal by the first delay amount detected at a start of a valid time period of the generated second control signal.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: March 10, 2015
    Assignee: Fujitsu Limited
    Inventor: Noriyuki Tokuhiro
  • Patent number: 8971143
    Abstract: Such a device is disclosed that includes a control circuit outputting a first clock signal having a first clock cycle in response to a first command signal and outputting a second clock signal having a second clock cycle in response to a second command signal, a first circuit controlled based on the first clock signal, and a second circuit controlled based on the second clock signal.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: March 3, 2015
    Assignee: PS4 Luxco S.a.r.l
    Inventors: Takuyo Kodama, Kosuke Goto
  • Patent number: 8971085
    Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: March 3, 2015
    Assignee: III Holdings 2, LLC
    Inventor: Michael C. Stephens, Jr.
  • Patent number: 8958254
    Abstract: An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.
    Type: Grant
    Filed: February 22, 2012
    Date of Patent: February 17, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Manish Chandra Joshi, Parvinder Kumar Rana, Lakshmikantha Vakwadi Holla
  • Patent number: 8958252
    Abstract: To provide a signal processing circuit including a nonvolatile memory circuit with a novel structure, the signal processing circuit includes an arithmetic portion, a memory, and a control portion for controlling the arithmetic portion and the memory. The control portion includes a set of a volatile memory circuit and a first nonvolatile memory circuit for storing data held in the volatile memory circuit, the memory includes a plurality of second nonvolatile memory circuits, and the first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor having a channel in an oxide semiconductor layer and a capacitor in which one of a pair of electrodes is electrically connected to a node which is set in a floating state when the transistor is turned off.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidetomo Kobayashi, Yukio Maehashi
  • Patent number: 8953409
    Abstract: A device includes a control circuit that triggers a first operation every time a specific signal is supplied thereto, and that triggers a second operation in place of the first operation in response to the first specific signal supplied after the number of the first operation performed has reached a predetermined number.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: February 10, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Toru Ishikawa
  • Patent number: 8947971
    Abstract: Such a device is disclosed that includes a clock generation circuit generating a first clock signal and having an output node, and a drive circuit coupled to the output node of the clock generation circuit. The clock generation circuit outputs the first clock signal from the output node to the drive circuit in a clock output mode, fixes a potential of the output node to a first level in a first clock stop mode, and fixes the potential of the output node to a second level that is different from the first level in a second clock stop mode.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: February 3, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Takuyo Kodama
  • Patent number: 8942047
    Abstract: Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: January 27, 2015
    Assignee: Sandisk Technologies Inc.
    Inventors: Man L. Mui, Teruhiko Kamei, Yingda Dong, Ken Oowada, Yosuke Kato, Fumitoshi Ito, Seungpil Lee
  • Patent number: 8937839
    Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: January 20, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Eric Lee
  • Patent number: 8937846
    Abstract: A write leveling calibration system and method for double data-rate dynamic random access memory includes performing write leveling at two different frequencies to determine to which of two successive rising clock cycle edges each data strobe signal would be aligned as a result of applying the write leveling delay determined by the write-leveling procedure. The determination can then be used to ensure that the data strobe signals of all source synchronous groups are aligned with the same edge of the clock signal.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: January 20, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Barbara Jean Duffner, David Linam
  • Patent number: 8934316
    Abstract: A parallel-serial conversion circuit includes an adjustment circuit that receives a parallel input signal having a plurality of bits and generates and outputs a parallel output signal having a plurality of bits. A conversion circuit coupled to the adjustment circuit generates a plurality of clock signals having mutually different phases with respect to a reference clock signal on the basis of the reference clock signal and serially selects the plurality of bits of the parallel output signal in accordance with the generated plurality of clock signals to convert the parallel output signal to serial 1-bit output signals. The adjustment circuit adjusts the output timing of each of the plurality of bits of the parallel output signal in time unit of half of one cycle of the reference clock signal.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: January 13, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichiro Ikeda, Kazumi Kojima, Hiroyuki Sano
  • Patent number: 8929156
    Abstract: A semiconductor memory device includes an internal clock generation unit configured to generate an internal clock including periodic pulses during a period of a test mode; a DQ information signal generation block configured to generate DQ information signals which are sequentially enabled, in response to the internal clock; and a data output block configured to output the DQ information signals to DQ pads during a period of the test mode.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: January 6, 2015
    Assignee: SK Hynix Inc.
    Inventor: Bok Rim Ko
  • Patent number: 8917566
    Abstract: Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Aaron J. Cummings, Michael T. Fragano, Kevin W. Gorman, Kelly A. Ockunzzi, Michael R. Ouellette
  • Patent number: 8913440
    Abstract: A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: December 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Derek C. Tao, Annie-Li-Keow Lum, Yukit Tang, Kuoyuan (Peter) Hsu
  • Patent number: 8913457
    Abstract: Memory circuitry includes memory components operable in response to first edges of an internal clock. The memory circuitry also includes internal clock generating circuitry to generate the internal clock in response to a system clock. The first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: December 16, 2014
    Assignees: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Nishu Kohli, Robin M. Wilson
  • Patent number: 8913459
    Abstract: A method for reading data from a plurality of DRAM devices connected to common command, address, and data busses. A clock signal is provided to the plurality of DRAM devices. A read command and address to the plurality of DRAM devices on the command and address busses in synchronization with the clock signal. A read clock signal is provided to the plurality of DRAM devices to initiate a read operation in one of the plurality of DRAM devices that is selected by the address. The one DRAM device delays the read clock signal by an amount based on a speed of the one of the plurality of DRAM devices to generate. First delayed read clock and second delayed read clock signals are provided. The read data is received on the data bus in synchronization with the second delayed read clock signal.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: December 16, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Chikara Kondo
  • Patent number: 8897047
    Abstract: An analog associative memory, which includes an array of coupled voltage or current controlled oscillators, matches patterns based on shifting frequencies away from a center frequency of the oscillators. Test and memorized patterns are programmed into the oscillators by varying the voltage or current that controls the oscillators. Matching patterns result in smaller shifts of frequencies and enable synchronization of oscillators. Non-matching patterns result in larger shifts and preclude synchronization of oscillators. The patterns may each include binary data and the pattern matching may be based on discrete shifts. The patterns may each include grayscale data and the pattern matching may be based on continuously-varied shifts. Other embodiments are described herein.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: November 25, 2014
    Assignee: Intel Corporation
    Inventors: George I. Bourianoff, Dmitri E. Nikonov
  • Patent number: 8897093
    Abstract: A controlling method of a connector, the connector, and a memory storage device are provided. The controlling method includes following steps. A first clock signal generated by a first oscillator in the connector is obtained. A second clock signal generated by a second oscillator in the connector is obtained. A frequency shift of the first oscillator is smaller than a frequency shift of the second oscillator. A detection window information corresponding to the second clock signal is corrected according to the first clock signal and the second clock signal. The first oscillator is turned off. A signal stream including a first signal is received. A detection window is generated according to the corrected detection window information and the second clock signal, and whether the first signal is a burst signal is determined according to the detection window. Thereby, the power consumption of the connector is reduced.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: November 25, 2014
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Ming Chen, Ming-Hui Tseng
  • Patent number: 8897084
    Abstract: Techniques are disclosed relating to determining when a data strobe signal is valid for capturing data. In one embodiment, an apparatus is disclosed that includes a memory interface circuit configured to determine an initial time value for capturing data from a memory based on a data strobe signal. In some embodiments, the memory interface circuit may determine this initial time value by reading a known value from memory. In one embodiment, the memory interface circuit further configured to determine an adjusted time value for capturing the data, where the memory interface circuit is configured to determine the adjusted time value by using the initial time value to sample the data strobe signal.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: November 25, 2014
    Assignee: Apple Inc.
    Inventors: Hao Chen, Rakesh L. Notani, Sukalpa Biswas
  • Patent number: 8890584
    Abstract: Disclosed herein is a device that includes: a frequency division circuit that divides a frequency of a first clock signal to generate a second clock signal; a first logic circuit that receives a first chip select signal and the second clock signal to generate a second chip select signal; and a command generation circuit that is activated based on the second chip select signal, and generates a second command signal based on a first command signal.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: November 18, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Chikara Kondo
  • Patent number: RE45366
    Abstract: The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kye-Hyun Kyung
  • Patent number: RE45378
    Abstract: The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: February 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kye-Hyun Kyung