Abstract: A method includes receiving at a management component of an FPGA a persona change request and issuing a request by the management component to a reconfigurable PR slot of the FPGA to change a first persona of a first circuit device of the FPGA to a second persona of a second circuit device of the FPGA. The management component, the reconfigurable PR slot, and the first and second circuit devices are configured in the FPGA core. The method includes switching by the reconfigurable PR slot the first persona to the second persona. The method includes issuing a request by the management component, a host re-enumeration of the reconfigurable PR slot, triggering by the host a re-enumeration component a re-enumeration of the reconfigurable PR slot, and exposing by the reconfigurable PR slot the second persona such that the host is reconfigured to recognize the second circuit device.

Abstract: Devices, systems and methods for maintaining consistent write latencies in non-volatile memory devices are described. An example method includes receiving, from a host device, a write command, computing an actual latency of the write command based on an arrival of the write command and a completion of the write command, incrementing, based on the actual latency, one or more of a plurality of counters, updating, based on the plurality of counters subsequent to the incrementing, a value of a minimum duration, and transmitting, at a time instance determined based on an updated value of the minimum duration, an indication of the completion of the write command to the host device, wherein the minimum duration represents a minimum latency between the arrival and the transmitting, and wherein transmitting at the time instance enables an observed latency to remain within a predetermined tolerance of an average value of the actual latency.

Abstract: A memory device includes a first data driver configured to send a first data according to a first clock signal; a first data port electrically coupled to the first data driver, the first data port configured to receive the first data; a second data driver configured to send a second data according to a second clock signal, wherein the second clock signal does not match the first clock signal; and a second data port electrically coupled to the second data driver, the second data port configured to receive the second data.

Abstract: A semiconductor device includes a substrate, a die and multiple conductive traces. The die is mounted on the substrate. The conductive traces are routed on the substrate and connected to the die. The conductive traces at least include a plurality of first conductive traces and a plurality of second conductive traces. The second conductive traces are coupled to a predetermined voltage for providing a shielding pattern. The first conductive traces and the second conductive traces are disposed on the substrate in a substantially interlaced pattern.

Abstract: A semiconductor device includes an address latch circuit and a column address generation circuit. The address latch circuit latches an address based on an input control signal generated according to a column control pulse and outputs the latched address as a pre-column address based on an output control signal generated according to an internal column control pulse. The column address generation circuit generates a column address from the pre-column address based on a delayed column control pulse and a delayed internal column control pulse.

Abstract: A storage controller communicates with an external device including a submission queue and a completion queue. An operation method of the storage controller includes receiving a notification associated with a command from the external device, based on a first clock, fetching the command from the submission queue, based on a second clock, performing an operation corresponding to the fetched command, based on a third clock, writing completion information to the completion queue, based on a fourth clock, and transmitting an interrupt signal to the external device, based on a fifth clock. Each of the first clock to the fifth clock is selectively activated depending on each operation phase.

Abstract: A semiconductor memory device includes first, second, third, and fourth planes, a first address bus connected to the first and third planes, a second address bus connected to the second and fourth planes, and a control circuit configured to execute a synchronous process on at least two planes in response to a first command set including a first address and a second address. The control circuit is configured to transfer the first address to the first and third planes through the first address bus, and the second address to the second and fourth planes through the second address bus, and during the synchronous process, select a first block in one of the first and third planes, based on the transferred first address and select a second block in one of the second and fourth planes, based on the transferred second address.

Abstract: The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information signal: a control circuit that provides a plurality of control signals; and a signal receiver replica circuit that receives a first reference signal. The signal receiver replica circuit includes a plurality of receivers. Each receiver of the plurality of receivers receives the first reference signal and a corresponding control signal of the plurality of control signals, and further provides an output signal.

Abstract: An apparatus includes a plurality of coarse delay circuits and a phase blender circuit. The coarse delay circuits may be configured to (i) receive an input clock signal, (ii) receive a plurality of control signals and (iii) generate a first phase signal and a second phase signal. The phase blender circuit may be configured to (i) receive the first phase signal and the second phase signal, (ii) receive a phase control signal, (iii) step between stages implemented by the coarse delay circuits and (iv) present an output clock signal. The phase blender circuit may mitigate a mismatch between the stages of the coarse delay circuits by interpolating an amount of coarse delay provided by the coarse delay circuits.

Abstract: In certain aspects of the disclosure, a frequency monitor includes a counter configured to receive a monitored clock signal, to count a number of periods of the monitored clock signal over a predetermined time duration, and to output a count value corresponding to the number of periods of the monitored clock signal. The frequency monitor also includes a comparator configured to receive the count value from the counter, to receive an expected count value, to compare the count value from the counter with the expected count value, and to output a pass status signal or a fail status signal based on the comparison.

Abstract: A memory device includes a first data driver configured to send a first data according to a first clock signal; a first data port electrically coupled to the first data driver, the first data port configured to receive the first data; a second data driver configured to send a second data according to a second clock signal, wherein the second clock signal does not match the first clock signal; and a second data port electrically coupled to the second data driver, the second data port configured to receive the second data.

Abstract: A computer system including a CPU and a memory subsystem connected via a system bus to communicate with each other, wherein the memory subsystem comprises a memory controller connected to the system bus, the computer system includes an up/down counter for counting a number of access requests and a number of requests other than access requests, a comparator for comparing the count of the up/down counter with a predetermined threshold value stored in a register, and a clock gate circuit for generating clock gate signals to decimate an operating clock of the memory controller in response to the comparison result of the comparator.

Abstract: A method including estimating an access request frequency from a CPU to a memory subsystem by counting a number of CPU access requests and a number of requests other than CPU access requests, wherein the CPU is connected to the memory subsystem via a system bus, and the memory subsystem includes a memory controller connected to the system bus, and a DDR memory, including the estimated access request frequency with a predetermined threshold value stored in a register, generating a clock gate signal to decimate an operating clock of the memory controller in response to a result of comparing the estimated access request frequency with the predetermined threshold value, generating a dummy cycle signal to delay the timing of signal data output from the memory controller to the system bus, and generating a clock enable signal to decimate an operating clock of the DDR memory.

Abstract: There are provided a memory system and an operating method thereof. A memory system includes a memory device suitable for storing data therein; and a memory controller suitable for initializing the memory device, or maintaining or changing a mode of the memory device according to power of the memory device during a wake-up operation.

Abstract: Systems and methods for generating periodic signals with reduced duty cycle variation are described. In some cases, a calibration procedure may be performed prior to a memory operation (e.g., prior to a read operation or a programming operation) in which a duty cycle correction circuit receives an input signal (e.g., an input clock signal), steps through various delay settings to determine a first delay setting corresponding with a signal high time for the input signal and a second delay setting corresponding with a signal low time for the input signal, generates a delayed version of the input signal corresponding with a mid-point delay setting between the first delay setting and the second delay setting, and generates a corrected signal using the delayed version of the input signal and the input signal.

Abstract: In one embodiment, the method includes performing a read operation on a memory, and determining, by a memory controller, whether to perform a reliability verification read operation based on a count value and a reference value. The count value is based on a number of read commands issued by the memory controller to the memory, and the reliability verification read operation is for reading data from at least one memory cell associated with at least one unselected word line in the memory. An unselected word line is a word line not selected during the read operation. The method further includes performing the reliability verification read operation for the at least one unselected word line based on the determining.

Abstract: Apparatuses and methods are directed to preventing duty cycle distortion in an electronic apparatus. The apparatus generally includes a first phase mixer stage configured to interpolate a first and a second input signal to provide a first intermediate signal and further configured to interpolate the second input signal and a third input signal to provide a second intermediate signal, the first phase mixer stage distorting duty cycle in providing the first intermediate signal. The apparatus further includes a second phase mixer stage configured to interpolate the first intermediate signal and the second intermediate signal to provide an output signal and further configured to compensate for duty cycle distortion of the first phase mixer stage.

Abstract: A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock.

Abstract: A memory storage device having a clock and data recovery circuit module are provided. The module includes sampling circuits, a first logic circuit module, a delay circuit module, a second logic circuit module, a frequency adjustment circuit and a clock control circuit. The sampling circuits sample a data signal according to reference clocks. The first logic circuit module performs a first logic operation according to a sampling result. The delay circuit module delays a result of the first logic operation. The second logic circuit module performs a second logic operation according to said result and the delayed first logic result. The frequency adjustment circuit outputs a frequency adjustment signal according to a result of the second logic operation, and the clock control circuit performs a phase locking accordingly. Therefore, a circuit complexity of the clock and data recovery circuit module may be reduced.

Abstract: Systems described herein enable PCIe device components to be used with multiple PCIe topologies and with host systems of varying configurations. In some cases, a number of varying PHYs and PCIe cores are utilized to increase the number of applications and/or specifications that may be satisfied with a host interface design. Further, some systems described herein may include a number of synchronizers, clock multiplier units, and selectors to create a host interface that can be configured for a number of applications. Despite increasing the flexibility of the usage of systems disclosed herein, costs can be reduced by using the systems of the present disclosure for PCIe based devices.

Abstract: A semiconductor memory device may include: a first fuse set unit suitable for storing a first repair address during a first mode; a second fuse set unit suitable for storing an input address during a second mode; and a comparison unit suitable for comparing the input address with the first repair address, wherein the first fuse set unit is reset when the first repair address is the same as the input address.

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

Abstract: The invention concerns a circuit comprising: a first circuit block (302) adapted to receive a first clock signal (CLK1) and to provide a first output data signal at a time determined by said first clock signal; a second circuit block (304) adapted to receive a second clock signal (CLK2) and to provide a second output data signal at a time determined by said second clock signal; a clock bus (314) coupled to corresponding outputs of said first and second circuit blocks for receiving a third clock signal (BCLK) based on said first and second clock signals; and a synchronization unit (312) coupled to said clock bus and adapted to sample said first and second output data signals based on said third clock signal.

Abstract: A driver circuit includes an output driver including a plurality of output driver legs. The driver circuit further includes a duty cycle adjuster configured to adjust a duty cycle of a signal provided to the output driver. The driver circuit further includes an isolation module configured to isolate at least one output driver leg of the output driver legs from remaining output driver legs of the output driver legs. The driver circuit further includes a duty cycle monitor configured to monitor an output of the at least one output driver leg when the at least one output driver leg is isolated from the remaining output driver legs, and to provide the monitored output to the duty cycle adjuster.

Abstract: Various example implementations are directed to circuits and methods for debugging multiple integrated circuit (IC) packages. According to an example implementation, a first logic analyzer in a first IC package determines a latency of a data link. In response to test input data, the first logic analyzer communicates the test input data to a second IC package, via the data link, and captures a first set of data signals from a logic circuit in the first IC package. In response to test input data, a second logic analyzer in the second IC package captures a second set of data signals from a second logic circuit and communicates the second set of data signals to the first logic analyzer circuit via the data link. The first logic analyzer aligns the first and second sets of data signals, based on the determined latency, and outputs the aligned sets of data signals.

Abstract: A circuit includes a load; a first differential pair coupled to the load and responsive to input data; a second differential pair coupled to the load and responsive to the input data; a third differential pair coupled to the first differential pair and the second differential pair and responsive to a first control signal and a second control signal; a bias circuit configured to pull a node coupled to both the first differential pair and the second differential pair to a predetermined state; and a current source coupled to the third differential pair and the bias circuit.

Abstract: For example, a semiconductor device includes a first latency counter, which selects whether to give an odd-cycle latency to an internal command signal; and a second latency counter, which gives a latency to an internal command signal at intervals of two cycles. The latency counters are connected in series. Since the number of bits in control information, which is used to set a latency, is smaller than the types of settable latency as a result, it is possible to reduce wiring density.

Abstract: A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.

Abstract: Disclosed herein is a device including a timing control circuit that receives a strobe signal supplied from outside to generate an internal strobe signal that is used as a timing signal to latch a data signal. An operation state of the timing control circuit is changed according to temperature change so as to keep an output timing of the internal strobe signal with respect to an input timing of the strobe signal.

Abstract: Disclosed herein is an apparatus that includes a clock circuit configured to receive first and second clock signals and perform a phase control operation in which a phase relationship between the first and second clock signals is controlled, the clock circuit configured to initiate the phase control operation each time a first control signal is asserted, the clock circuit including a comparator circuit that is configured to produce a second control signal indicative of a phase difference between the first and second clock signals, and a timing generator configured to assert the first control signal cyclically, the timing generator configured to respond to the second control signal to control a cycle of producing the first control signal.

Abstract: A semiconductor memory device includes: a burst start signal generation unit configured to generate a first burst start signal by delaying a write pulse by a first period, generate a second burst start signal by delaying the write pulse by a second period, and selectively transmit the first or second burst start signal as a select burst start signal in response to a test signal; an input control signal generation unit configured to generate an input control signal in response to the first burst start signal; and a write command generation unit configured to generate a write driver enable signal in response to the select burst start signal.

Abstract: A device includes a first clock generation circuit that receives an external clock signal supplied to the device, delays the external clock signal to output a first clock signal synchronized with the external clock signal, and a circuit that generates a control signal to control output of data, based on second clock signals obtained by dividing an internal clock signal generated from the external clock signal, and third clock signals obtained by dividing the first clock signal.

Abstract: Among other things, one or more techniques or systems for facilitating access operations to a single port memory device are provided. Multiple access operations to a single port memory device, such as a 6 transistor bitcell array of an SPSRAM, are performed during a single clock period of a system clock. In an embodiment, a wrapper controller initiates a first access operation during a first clock period of the system clock based upon a rising edge of the system clock. Responsive to receiving an operation complete signal during the first clock operation, the wrapper controller initiates a second access operation to the single port memory device during the first clock period. In this way, multi-port access functionality is implemented, such as in a serial manner to mitigate operation disturbs, for a single port memory device that occupies a relatively smaller area than a multi-port memory device for improved storage density.

Abstract: A semiconductor memory apparatus includes an enable signal generation unit configured to be inputted with a plurality of clocks which have different phases, and generate a plurality of enable signals; and a plurality of sampling units configured to output input data as sampling data in response to respective pairs of clocks of the plurality of clocks and respective ones of the plurality of enable signals.

Abstract: A tracking circuit in a memory macro includes a data line, a first tracking cell, and a plurality of transistors. The first tracking cell is electrically coupled to the data line. The plurality of transistors is electrically coupled to the data line. The plurality of transistors is configured to cause a delay on a transition of a signal of the data line based on a delay current. The signal of the data line is configured for use in generating a signal of a control line of a memory cell of the memory macro.

Abstract: According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.

Abstract: A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.

Abstract: Apparatuses and methods for providing active and inactive clock signals to a command path circuit are described. An example method includes providing an active clock signal to a command path for a first portion of a command cycle for a command of back-to-back commands. The command path decodes the command and provides an output command signal responsive to the clock signal. The method further includes providing an inactive clock signal to the command path for a second portion of the command cycle for the command of the back-to-back commands.

Abstract: A semiconductor apparatus includes a phase detecting unit that continuously detects a first delay amount during a read operation, based on a phase difference between an external clock signal and an internal clock signal; a generating unit that generates a second control signal by delaying a first control signal by a second delay amount that when added to the first delay amount, the sum is a specific time period, a valid time period of the first control signal starts when the read operation starts and is at least to equal a read time for one data signal and less than the specific time period that is from the start of the read operation until output of a received data signal; and a delay control unit that delays the data signal by the first delay amount detected at a start of a valid time period of the generated second control signal.

Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: Such a device is disclosed that includes a control circuit outputting a first clock signal having a first clock cycle in response to a first command signal and outputting a second clock signal having a second clock cycle in response to a second command signal, a first circuit controlled based on the first clock signal, and a second circuit controlled based on the second clock signal.

Abstract: An 8T memory bit cell receives a clock signal and read and write address signals. A read address latch/clock circuit receives the clock signal and the read address signals and initiates a read operation during a first clock cycle state. A write address flip-flop/clock circuit receives the clock signal and the write address signals and initiates a write operation during a second clock cycle state. An inverter receives and inverts the clock signal and applies the inverted clock signal to the write address flip-flop/clock circuit. The read address latch/clock circuit initiates a read word line precharge operation during the second clock cycle state and a write word line precharge operation during the first clock cycle state. The write address flip-flop/clock circuit may also include a loose self-timer to end a write cycle is a clock signal continues beyond a predetermined time.

Abstract: To provide a signal processing circuit including a nonvolatile memory circuit with a novel structure, the signal processing circuit includes an arithmetic portion, a memory, and a control portion for controlling the arithmetic portion and the memory. The control portion includes a set of a volatile memory circuit and a first nonvolatile memory circuit for storing data held in the volatile memory circuit, the memory includes a plurality of second nonvolatile memory circuits, and the first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor having a channel in an oxide semiconductor layer and a capacitor in which one of a pair of electrodes is electrically connected to a node which is set in a floating state when the transistor is turned off.

Abstract: A device includes a control circuit that triggers a first operation every time a specific signal is supplied thereto, and that triggers a second operation in place of the first operation in response to the first specific signal supplied after the number of the first operation performed has reached a predetermined number.

Abstract: Such a device is disclosed that includes a clock generation circuit generating a first clock signal and having an output node, and a drive circuit coupled to the output node of the clock generation circuit. The clock generation circuit outputs the first clock signal from the output node to the drive circuit in a clock output mode, fixes a potential of the output node to a first level in a first clock stop mode, and fixes the potential of the output node to a second level that is different from the first level in a second clock stop mode.

Abstract: Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.

Abstract: A write leveling calibration system and method for double data-rate dynamic random access memory includes performing write leveling at two different frequencies to determine to which of two successive rising clock cycle edges each data strobe signal would be aligned as a result of applying the write leveling delay determined by the write-leveling procedure. The determination can then be used to ensure that the data strobe signals of all source synchronous groups are aligned with the same edge of the clock signal.

Abstract: The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.

Abstract: The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.