Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.

Abstract: A parallel-serial conversion circuit includes an adjustment circuit that receives a parallel input signal having a plurality of bits and generates and outputs a parallel output signal having a plurality of bits. A conversion circuit coupled to the adjustment circuit generates a plurality of clock signals having mutually different phases with respect to a reference clock signal on the basis of the reference clock signal and serially selects the plurality of bits of the parallel output signal in accordance with the generated plurality of clock signals to convert the parallel output signal to serial 1-bit output signals. The adjustment circuit adjusts the output timing of each of the plurality of bits of the parallel output signal in time unit of half of one cycle of the reference clock signal.

Abstract: A semiconductor memory device includes an internal clock generation unit configured to generate an internal clock including periodic pulses during a period of a test mode; a DQ information signal generation block configured to generate DQ information signals which are sequentially enabled, in response to the internal clock; and a data output block configured to output the DQ information signals to DQ pads during a period of the test mode.

Abstract: Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.

Abstract: A method for reading data from a plurality of DRAM devices connected to common command, address, and data busses. A clock signal is provided to the plurality of DRAM devices. A read command and address to the plurality of DRAM devices on the command and address busses in synchronization with the clock signal. A read clock signal is provided to the plurality of DRAM devices to initiate a read operation in one of the plurality of DRAM devices that is selected by the address. The one DRAM device delays the read clock signal by an amount based on a speed of the one of the plurality of DRAM devices to generate. First delayed read clock and second delayed read clock signals are provided. The read data is received on the data bus in synchronization with the second delayed read clock signal.

Abstract: Memory circuitry includes memory components operable in response to first edges of an internal clock. The memory circuitry also includes internal clock generating circuitry to generate the internal clock in response to a system clock. The first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

Abstract: A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro.

Abstract: Techniques are disclosed relating to determining when a data strobe signal is valid for capturing data. In one embodiment, an apparatus is disclosed that includes a memory interface circuit configured to determine an initial time value for capturing data from a memory based on a data strobe signal. In some embodiments, the memory interface circuit may determine this initial time value by reading a known value from memory. In one embodiment, the memory interface circuit further configured to determine an adjusted time value for capturing the data, where the memory interface circuit is configured to determine the adjusted time value by using the initial time value to sample the data strobe signal.

Abstract: A controlling method of a connector, the connector, and a memory storage device are provided. The controlling method includes following steps. A first clock signal generated by a first oscillator in the connector is obtained. A second clock signal generated by a second oscillator in the connector is obtained. A frequency shift of the first oscillator is smaller than a frequency shift of the second oscillator. A detection window information corresponding to the second clock signal is corrected according to the first clock signal and the second clock signal. The first oscillator is turned off. A signal stream including a first signal is received. A detection window is generated according to the corrected detection window information and the second clock signal, and whether the first signal is a burst signal is determined according to the detection window. Thereby, the power consumption of the connector is reduced.

Abstract: An analog associative memory, which includes an array of coupled voltage or current controlled oscillators, matches patterns based on shifting frequencies away from a center frequency of the oscillators. Test and memorized patterns are programmed into the oscillators by varying the voltage or current that controls the oscillators. Matching patterns result in smaller shifts of frequencies and enable synchronization of oscillators. Non-matching patterns result in larger shifts and preclude synchronization of oscillators. The patterns may each include binary data and the pattern matching may be based on discrete shifts. The patterns may each include grayscale data and the pattern matching may be based on continuously-varied shifts. Other embodiments are described herein.

Abstract: A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.

Abstract: Disclosed herein is a device that includes: a frequency division circuit that divides a frequency of a first clock signal to generate a second clock signal; a first logic circuit that receives a first chip select signal and the second clock signal to generate a second chip select signal; and a command generation circuit that is activated based on the second chip select signal, and generates a second command signal based on a first command signal.

Abstract: Disclosed herein is a device comprising a first terminal for a first clock signal, a second terminal for a second clock signal substantially complementary to the first clock signal, a third terminal for a third clock signal, a fourth terminal for a fourth clock signal substantially complementary to the third clock signal, a first logic gate to produce a first intermediate signal, a second logic gate to produce a second intermediate signal, a first delay circuit to produce a third intermediate signal, and a second delay circuit to produce a fourth intermediate signal, and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.

Abstract: Systems and methods are disclosed relating to semiconductor memory devices. According to some exemplary implementations, there are provided innovations associated with power and ground pads in devices such as static random access memory (“SRAM”) devices and dynamic random access memory (“DRAM”) devices. Moreover, the systems and/or methods may include features such as minimization of simultaneous switching outputs (SSO) effects relating to echo clock circuitry.

Abstract: A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by using substantially the same latency delayed received command indications. A downstream clock generation circuit generates a clock signal from a received command indication delayed by both a delay locked loop and latency delays stored in latency control circuits. An upstream clock generation circuit generates a clock signal from the received command indication delayed by the delay locked loop and capture indications from the latency control circuits.

Abstract: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.

Abstract: A data write circuit of a semiconductor apparatus includes a plurality of latches configured to latch a plurality of data in response to activation of a plurality of control signals and output the latched data to data lines; and a control unit configured to generate the plurality of control signals to be activated at different timings, such that partial data input at relatively earlier timing among the plurality of data is latched at earlier timing than the other data by a portion of the plurality of latches.

Abstract: An integrated circuit with memory elements is provided. The memory elements may be single-port memory cells that are used to provide multiport memory functionality. The integrated circuit may include an arbitration circuit operable to receive memory access requests from at least first and second request generators. The arbitration circuit may be configured to operate in a synchronous mode and an asynchronous mode. The arbitration circuit operating in the synchronous mode may perform port selection based on a predetermined logic table. The arbitration circuit operating in the asynchronous mode may execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed.

Abstract: Disclosed herein is a device that includes a command decoder and a latency counter. The command decoder generates a first internal command in response to a first internal clock signal. The latency counter includes: a gate control signal generation unit generating output gate signals in response to a second internal clock signal; delay circuits each receiving an associated one of the output gate signals and generating an associated one of input gate signals; and a command signal latch unit fetching the first internal command in response to one of the input gate signals and outputting the first internal command in response to one of the output gate signals. Each of the delay circuit includes a first delay element that operates on a first power supply voltage and a second delay element that operates on a second power supply voltage different from the first power supply voltage.

Abstract: A memory includes a memory array having a plurality of word lines, a plurality of latching predecoders, and word line driver logic. Each latching predecoder receives a clock signal and a plurality of address signals and latches a result of a logic function of the plurality of address signals in response to a first edge of a clock cycle of the clock signal and provides a predetermined value in response to a second edge of the first clock cycle of the clock signal, wherein, in response to the second edge, every latching decoder of the plurality of latching predecoders provides a same predetermined value. The word line driver logic selectively activates a selected word line of the plurality of word lines in response to the latched results.

Abstract: A semiconductor device includes: a DLL circuit that generates an internal clock signal based on an external clock signal; a clock dividing circuit that generates two complementary internal clock signals having different phases based on the internal clock signal; and a multiplexer that outputs two internal data signals in synchronization with the two clock signals based on internal data signals, respectively. An internal power supply voltage supplied to the clock dividing circuit and an internal power supply voltage supplied to the multiplexer are generated by respective different power supply circuits and are separated from each other in the semiconductor device. This prevents interaction among noises.

Abstract: The present disclosure includes apparatuses and methods for power consumption control. A number of embodiments include determining power consumption information for each phase in a combination of phases of a command, and authorizing execution of at least one of the phases in the combination based, at least partially, on the power consumption information determined for the at least one of the phases.

Abstract: A method of operating a multiport memory, which has first and second sets of word lines and bit lines for accessing a memory array, uses a first port and a second port for accesses during a first phase of a master clock and a third port and a fourth port during a second phase of the master clock. Each port has its own port clock, which clocks their own row and column addresses, that is no faster than the master clock. Assuming there is demand for it, four accesses occur for each cycle of the master clock. This has the effect of being able to be sure that a given access is complete within two cycles of the port clocks and can be operated at the rate of one access per cycle of the port clock.

Abstract: Multiple timing reference signals (e.g., clock signals) each cycling at the same frequency are distributed in a fly-by topology to a plurality of memory devices in various embodiments are presented. These multiple clock signals each have a different phase relationship to each other (e.g., quadrature). A first circuit receives a first of these clocks as a first timing reference signal. A second circuit receives a second of these clocks as a second timing reference signal. A plurality of receiver circuits receive signals synchronously with respect to the first timing reference signal and the second timing reference signal, such that a first signal value is resolved using the first timing reference signal and a second signal value is resolved using the second timing reference signal.

Abstract: A semiconductor memory device includes an internal signal generation unit configured to output a column select signal and a write enable signal in response to an external address, a write circuit unit configured to output internal data corresponding to external data in response to the write enable signal, a core unit configured to store the internal data in response to the column select signal, and an output timing control unit configured to control output timings of the internal signal generation unit and the write circuit unit in response to an external command, an internal synchronization signal, and preamble related information.

Abstract: A memory device comprising: at least one bank of memory cells that receives a first clock for clocking commands and a second clock for clocking data, wherein the second clock is activated based on a first command and deactivated based on a second command. The memory device further including a clock activation circuit configured to generate an enable signal based on the first command and a disable signal based on the second command, and a clock generator configured to generate the second clock based on a reference clock upon receipt of the enable signal.

Abstract: Disclosed herein is a semiconductor device having first and second operation modes. In the first operation mode, the semiconductor device deactivates a DLL circuit during a self-refresh mode. In the second operation mode, the semiconductor device intermittently activates the DLL circuit to generate an internal clock signal.

Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputing an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

Abstract: A semiconductor memory device includes a pipe latch circuit configured to receive parallel input data and output serial data or set an output terminal of the pipe latch circuit at a predetermined voltage level in response to an enable signal, and a synchronization circuit configured to output an output data of the pipe latch circuit in synchronization with an internal clock.

Abstract: In a method, a first edge of a first tracking signal in a first direction of a memory array is generated. A first edge of a second tracking signal in a second direction of the memory array is generated. A first edge of a write-timing control signal is generated based on a slower edge of the first edge the first tracking signal and of the first edge of the second tracking signal. The first edge of the write-timing control signal is used to generate a second edge of the second tracking signal.

Abstract: Disclosed herein is a device comprising a first terminal for a first clock signal, a second terminal for a second clock signal substantially complementary to the first clock signal, a third terminal for a third clock signal, a fourth terminal for a fourth clock signal substantially complementary to the third clock signal, a first logic gate to produce a first intermediate signal, a second logic gate to produce a second intermediate signal, a first delay circuit to produce a third intermediate signal, and a second delay circuit to produce a fourth intermediate signal, and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.

Abstract: A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line.

Abstract: Examples of command latency systems and methods are described. In some examples, phase information associated with a received command signal is stored, a received command signal is propagated through a reduced clock flip-flop pipeline and the delayed command signal is combined with the stored phase information. The reduced clock flip-flop pipeline may use a clock having a lower frequency than that used to issue the command signal. Accordingly, fewer flip-flops may be required.

Abstract: A clock transfer circuit includes a clock transfer unit configured to receive an external clock and transfer the received external clock as one or more internal clocks and a clock control unit configured to control the clock transfer unit to transfer the external clock as a column clock among the internal clocks in response to an active command and block a transfer of the external clock as the column clock in response to a precharge command.

Abstract: A method includes generating a first and a second internal clock signal from a clock signal, wherein a first internal clock signal edge of the first internal clock signal and a second internal clock signal edge of the second internal clock signal are generated from a same edge of the clock signal. A first one of the first and the second internal clock edges is used to trigger a first operation on a six-transistor (6T) Static Random Access Memory (SRAM) cell of a SRAM array. A second one of the first and the second internal clock edges is used to trigger a second operation on the 6T SRAM cell. The first and the second operations are performed on different ports of the 6T SRAM. The first and the second operations are performed within a same clock cycle of the clock signal.

Abstract: A circuit can include address evaluation circuitry coupled to an address bus of a memory and configured to generate a first control signal responsive to determining that an address on the address bus has not changed for a current clock cycle from a previous clock cycle. The circuit can include write enable evaluation circuitry coupled to the memory and configured to generate a second control signal responsive to determining that a write enable signal of the memory is de-asserted for the current clock cycle and for the previous clock cycle. The circuit can include clock enable circuitry coupled to a clock enable port of the memory and configured to generate a clock enable signal to the clock enable port of the memory responsive to the first control signal and the second control signal.

Abstract: Data serializers, output buffers, memory devices and methods for serializing are provided, including a data serializer that may convert digits of parallel data to a stream of corresponding digits of serial data digits. One such data serializer may include a logic system receiving the parallel data digits and clock signals having phases that are equally phased apart from each other. Such a data serializer may use the clock signals to generate data sample signals having a value corresponding to the value of a respective one of the parallel data digits and a timing corresponding to a respective one of the clock signals. The data sample signals may be applied to a switching circuit that includes a plurality of switches, such as respective transistors, coupled to each other in parallel between an output node and a first voltage.

Abstract: In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

Abstract: A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.

Abstract: A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit is provided. The semiconductor memory device includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obtaining a locked state. A control unit controls the DLL circuit to constantly maintain the locked state during an updating period of an auto-refresh period of an auto-refresh operation for refreshing memory banks.

Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.

Abstract: Interconnections between signal lines help to reduce signal skew between signals carried on the signal lines. The interconnections may be resistive interconnections, and the signal lines may be clock lines. In a memory controller, for example, resistive traces may connect adjacent clock lines. The resistive traces reduce the clock signal skew between the adjacent clock lines, and throughout the memory controller as a whole.

Abstract: Disclosed herein is a semiconductor device having self-refresh modes in which a refresh operation of storage data is periodically performed asynchronously with an external clock signal. The semiconductor device performs the refresh operation on n memory cells in response to an auto-refresh command. The semiconductor device periodically performs the refresh operation on m memory cells included in the memory cell array during the self-refresh mode, where m is smaller than n.

Abstract: To provide a signal processing circuit including a nonvolatile memory circuit with a novel structure, the signal processing circuit includes an arithmetic portion, a memory, and a control portion for controlling the arithmetic portion and the memory. The control portion includes a set of a volatile memory circuit and a first nonvolatile memory circuit for storing data held in the volatile memory circuit, the memory includes a plurality of second nonvolatile memory circuits, and the first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor having a channel in an oxide semiconductor layer and a capacitor in which one of a pair of electrodes is electrically connected to a node which is set in a floating state when the transistor is turned off.

Abstract: A system includes a shared memory and a plurality of processor cores communicatively coupled to the shared memory. The system includes a processor core memory and a clock subsystem for providing a clock signal to the shared memory and the plurality of processor cores. Each of the plurality of processor cores executes instructions stored in the processor core memory for synchronously changing the clock rate provided by the clock subsystem to the plurality of processor cores.

Abstract: Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register. The data path has a data propagation delay and is configured to receive data and propagate the data therethrough. The delay path is configured to receive a clock signal and provide a delayed clock signal having a delay relative to the clock signal that models the data propagation delay. The clocked data register is configured to clock in data responsive at least in part to the delayed clock signal. The clocked data register is further configured to clock out data responsive at least in part to the clock signal.

Abstract: A method can include storing bank addresses, if received, on at least rising and falling edges of a same clock cycle; and if addresses stored on the rising and falling edges of the same clock cycle correspond to different banks of a memory device, starting accesses to both banks after the falling edge of the clock cycle; wherein any of the banks can be accessed in response to an address stored on a rising edge of a next clock cycle. Devices and additional methods are also disclosed.

Abstract: Circuits and techniques for operating a memory circuit are disclosed. A disclosed circuit includes a memory circuit and a sleep circuit with an output terminal coupled to the memory circuit. The sleep circuit is operable to receive a control signal and further operable to place the memory circuit in different modes of operation. The memory circuit may be placed in either a first mode of operation, a second mode of operation or a third mode of operation based at least partly on the control signal. An input terminal of the sleep circuit is coupled to an output terminal of the control circuit. The control circuit is operable to receive an enable signal and is operable to supply the control signal to the sleep circuit at first, second and third voltage levels during the first, second and third modes of operation, respectively, based on the enable signal and a clock signal.

Abstract: A dynamic phase shifter and staticizer circuit and method includes a clock domino configured to receive a phase memory signal from a memory array and a clock signal and output the intermediate signal, and a staticizer configured to receive the intermediate signal from the clock domino and the clock signal and output a static memory signal. The static memory signal is shifted by one clock cycle from the phase memory signal. Setup and holding is done with respect to the clock edge, shifting the output of the clock domino, and the received phase memory signal can borrow into the next cycle when being sampled. The phase memory signal is converted from a half-cycle in length to the static memory signal that is a full-cycle in length.

Abstract: Apparatus, systems, and methods are disclosed that operate to generate a clock signal in a die in a stack and to receive the clock signal in another die in the stack. Additional apparatus, systems, and methods are disclosed.