Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: A nonvolatile memory device is provided. A counter counts an amount of data to be program-inhibited among data to be written to memory cells to provide a first count value. The counter also counts an amount of program-inhibited data among data written to the memory cells to provide a second count value. Control logic controls a program operation by comparing the first count value with the second count value.

Abstract: A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Programming can be stopped when all non-volatile storage elements have reached their target level or when the number of non-volatile storage elements that have not reached their target level is less than a number or memory cells that can be corrected using an error correction process during a read operation (or other operation). The number of non-volatile storage elements that have not reached their target level can be estimated by counting the number of non-volatile storage elements that have not reached a condition that is different (e.g., lower) than the target level.

Abstract: A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal.

Abstract: To provide a counter circuit capable of accurately counting a high-frequency signal in which hazard or the like is easily generated. There are provided: a frequency dividing circuit that generates first and second frequency dividing clocks, which differ in phase to each other, based on a clock signal; a first counter that counts the first frequency dividing clock; a second counter that synchronizes with the second frequency dividing clock to fetch a count value of the first counter; and a selection circuit that exclusively selects count values of the first and second counters. According to the present invention, a relation of the count values between the first and second counters is kept always constant, and thus, even when hazard occurs, the count values are only made to jump and the count values do not fluctuate.

Abstract: A memory cell array has a plurality of memory cells arrayed in row and column directions. A plurality of sense amplifier units includes a plurality of sense amplifiers detecting write completion of each of the memory cells selected for each row. A plurality of detection units is arranged correspondingly to the sense amplifier units, and forms a transfer path for transferring potential in accordance with a detection output signal of each sense amplifier unit. The detection units detect a sense amplifier unit corresponding to a portion where the transfer path breaks off, as a sense amplifier unit including write incompletion bit.

Abstract: In an SDRAM of reduced current consumption, a signal RAS for performing refresh while temporally splitting refresh becomes active N times (where N is an integer and N?2 holds) in a single refresh time period (indicated by a signal REF) to thereby refresh an internal memory array successively. The SDRAM includes a DLL circuit for aligning phase of an internal clock signal with that of an external clock signal that is externally supplied, and a DLL control circuit for exercising control so as to halt operation of the DLL circuit in an interval in which the address signal becomes active one or more times and N?1 times or fewer, this interval being included in an interval in which the signal RAS becomes active N times. The DLL control circuit counts the signal RAS and decodes the value of the count. Operation of the DLL circuit is halted while a prescribed range of count values is being decoded.

Abstract: A semiconductor memory apparatus includes a counting control circuit and an address counting circuit. The counting control circuit is configured to generate a first counting start signal, a second counting start signal and a counting count signal in response to an auto-refresh signal, a voltage stabilization signal and a fuse control signal. The address counting circuit is configured to count a plurality of count addresses in response to the first counting start signal, and to count one or more specified count addresses from among the plurality of count addresses in response to the second counting start signal and the counting control signal.

Abstract: A memory system comprises charge storage cells and a refresh control module. The charge storage cells have a charge level decay that is based on lifetime erase operations performed on the charge storage cells. The refresh control module increases charge levels of the charge storage cells to offset the charge level decay without first erasing the charge storage cells. A method of controlling a memory system comprises determining charge level decay of charge storage cells having charge level decay characteristics that are based on lifetime erase operations performed on the charge storage cells; and increasing charge levels of the charge storage cells to offset the charge level decay without first erasing the charge storage cells.

Abstract: A table-based driving circuit for displays that switches between a normal operational mode and a read table block mode. The driving circuit comprises an address sequencer and a memory. The memory comprises the full table of individual sequences, such as interlacing or color-sequential sequence. In the read table mode, the next upcoming addresses are read, i.e. are downloaded, from the memory into an address table register in the address sequencer. In the normal operational mode, the address sequencer generates the addresses for the video data to be stored in the memory or to be displayed.

Abstract: A memory may includes: word lines; bit lines; memory array blocks including memory cells, each memory array block being a unit of a data read operation or a data write operation; a row decoder configured to selectively drive the word lines; sense amplifiers configured to detect data; and an access counter provided for each memory cell block, the access counter counting the number of times of accessing the memory array blocks in order to read data or write data, and activating a refresh request signal when the number of times of access reaches a predetermined number of times, wherein during an activation period of the refresh request signal of the access counter, the row decoder periodically and sequentially activates the word lines of the memory array blocks corresponding to the access counter, and the sense amplifier performs a refresh operation of the memory cells connected to the activated word lines.

Abstract: Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. One such method includes generating and latching an internal write command. The latched internal write command is released after a latency delay responsive to the memory clock signal. The internal write command is propagated over an internal write command path. Write data is captured and internal write command latched in response to a write clock signal. The captured write data is released to be written to memory.

Abstract: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.

Abstract: A memory access strobe configuration system and process operable to generate a strobe signal having a selected phase. Based on the strobe signal, a write/read cycle using a first logic value at a memory location of a memory device generates a result logic value. The result logic value provided by the write/read cycle is compared to the first logic value. Where there is a mismatch between the result logic value and the first logic value, the phase of the strobe signal is updated. The process is then repeated using a strobe signal having the updated phase.

Abstract: A semiconductor memory that assigns M data groups, each data group including N data, to a first address, where M and N are integers equal to or larger than 2; and wherein L data among N data is designated by a second address indicating a position of the data groups and the L data is read from the designated position, where L is an integer and L<N.

Abstract: A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate.

Abstract: The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includes adjusting at least one program voltage, from an initial program voltage to an adjusted voltage, in response to the counted number of process cycles.

Abstract: A sensing enable signal control circuit determines a driving timing of an I/O sense amplifier based on a read-out result of data, which is stored in a dummy cell of a semiconductor memory apparatus. The sensing enable signal control circuit in a semiconductor memory apparatus includes a detection code generating unit configured to output a detection code according to a voltage level of dummy cell data, which are read out from a dummy cell through at least one read operation, in response to a column select enable signal, and a multiplexer configured to receive the detection code and a default code and output a delay code to delay a sensing enable signal.

Abstract: A semiconductor memory device includes a bank having a plurality of mats, an address counting unit configured to receive an auto-refresh command consecutively applied at predetermined intervals corresponding to a number of the mats, and sequentially count an internal address in response to the auto-refresh command, and an address transferring unit configured to enable the plurality of mats in response to the auto-refresh command, and transfer the internal address to the plurality of mats at predetermined time intervals.

Abstract: Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. One such method includes generating and latching an internal write command. The latched internal write command is released after a latency delay responsive to the memory clock signal. The internal write command is propagated over an internal write command path. Write data is captured and internal write command latched in response to a write clock signal. The captured write data is released to be written to memory.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Abstract: A semiconductor memory device executes a refresh operation on memory banks, and includes: a command decoder that decodes a command from outside the semiconductor memory device, and outputs a refresh instruction when the command is an auto-refresh command; a refresh command generating unit that outputs a refresh command signal by a predetermined number of times corresponding to the number of word lines to be refreshed in response to the refresh instruction; a bank address counter that holds a bank address for selecting a memory bank to be refreshed, counts up the bank address every time the refresh command signal is output, and performs a carry-over action when count-up operations equivalent to the number of the memory banks are performed; and a row address counter that holds a row address for selecting a word line to be refreshed, and counts up the row address in response to the carry-over action.

Abstract: An apparatus and method for reducing power consumption within dynamic memory devices having internal self-refresh circuitry. The circuits for generating isolator control (ISO), pre-decoded row address (PXID) and/or word enable (WE) signals are configured in response to receipt of self-refresh and refresh counter signals to output different timing and sequencing when in self-refresh mode than when in normal mode of the memory device. Conventionally, ISO signals are controlled from a block selection circuit which also controls bit line equalization (BLEQ) and sense amplifier enable (SAPN). While in conventional circuits the PXID and WE signals are generated in response to the output of the address decoder and thus have a fixed timing in relation to the output of the address decoder. The use of different timing and sequencing can lower power consumption, such as by outputting fewer signal transitions per block during self-refresh.

Abstract: Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of a plurality of memory circuits in a system. The memory circuits may be stacked and may also be ranked memory circuits. The global memory select signal may be sent to a counter. Such a counter could count the length of time that the global memory select signal is active, and based on the counting, sends a count signal to a comparator. The comparator may compare the count signal with a programmed value to determine if a specific memory chip and/or port is to be accessed. This configuration may be duplicated over multiple ports on the same memory device, as well as across multiple memory ranks.

Abstract: This document discusses among other things, a system comprising a host controller, an Input/Output buffer, and a memory device. The memory device is coupled to the host controller and is configured to receive a read command from the host controller. The non-volatile includes an interface control logic, which is in communication with a non-volatile memory. The interface control logic includes a latency programming circuit coupled to the non-volatile memory and the Input/Output buffer. The latency programming circuit stores at least one value corresponding to dummy byte delays to be provided at the non-volatile memory prior to transferring data from the non-volatile memory during a read operation.

Abstract: A decoder, a memory system, and a physical position converting method thereof may detect whether an address count of an input address is equal to or greater than a predetermined value. A physical position of a semiconductor memory device corresponding to the input address may be converted if the address count is equal to or greater than the predetermined value.

Abstract: A method and system to lower the minimum operating voltage of a memory array during read and/or write operations of the memory array. In one embodiment of the invention, the voltage of the read and/or write word line of the memory array is boosted or increased during read and/or write operations of the memory array. By doing so, the NMOS devices in the memory array are strengthened and the contention between the NMOS and PMOS devices are reduced during read and/or write operations of the memory array. This helps to lower or reduce the required VCCmin of the memory array during read and/or write operations of the memory array.

Abstract: A semiconductor memory device includes a memory core circuit having memory cells for storing data, a circuit configured to refresh the memory core circuit at a refresh interval, a temperature detecting unit configured to detect temperature, and a control circuit configured to shorten the refresh interval immediately in response to detection of a predetermined temperature rise by the temperature detecting unit and to elongate the refresh interval after refreshing every one of the memory cells at least once in response to detection of a temperature drop by the temperature detecting unit.

Abstract: A semiconductor memory device includes a plurality of memory chips each including a chip identification (ID) generation circuit.

Abstract: A semiconductor memory device is provided that can support a per-bank refresh as well as an all-bank refresh and a self refresh. The semiconductor memory device includes an address counting unit for counting a bank address signal of a specific bank and row address signals of the specific bank in response to a control signal including refresh mode information when a per-bank refresh command is received, and for counting row address signals in response to the control signal when an all-bank refresh command or a self refresh command is received.

Abstract: An address counting circuit includes a counter configured to sequentially count from an initial address in response to a clock signal in order to output counted addresses. The address counting circuit also includes a code conversion unit that is configured to output converted addresses such that only one address bit of the converted addresses with respect to the previous converted addresses are toggled to output the converted addresses. The converted addresses output form the code conversion unit do not overlap with one another.

Abstract: An input/output interface reads data from and writes data to a DDR memory. The interface includes data and strobe circuits. The strobe circuit includes preamble logic, a first counter operating with a strobe clock, a second counter operating with an ASIC-generated clock, a strobe park circuit and a first synchronizer. The preamble logic receives strobe signals from the DDR memory and generates a preamble signal. The first counter generates a first input of the strobe park circuit. The second counter generates a second input of the strobe park circuit. The strobe park circuit controllably replaces the strobe signals from the DDR memory with respective non-transitioning signals when data is not being read. The data circuit includes a FIFO buffer and a second synchronizer. The FIFO buffer receives data with the strobe clock. The second synchronizer generates a representation of the data in response to the ASIC-generated clock.

Abstract: A semiconductor integrated circuit (100) fetches read data from DDR-SDRAMs (110, 120) each operating in synchronization with a clock, and transfers the read data. The semiconductor integrated circuit (100) includes read buffers (104, 105) for fetching the read data from the DDR-SDRAMs (110, 120), and transferring the read data, latch timing control circuits (102, 103) for controlling respective latch timings with which the read buffers (104, 105) fetch the read data from the DDR-SDRAMs (110, 120) based on respective data strobe signals from the DDR-SDRAMs (110, 120), and a read timing control circuit (106) for controlling respective read timings with which the read buffers (104, 105) transfer the read data based on the latch timings of the latch timing control circuits (102, 103).

Abstract: A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and an output selecting circuit that causes the internal command taken in the latch circuit to be output. The input selection circuit includes a timing control circuit allocated to each of the signal paths. The timing control circuit includes an SR latch circuit that is set by the internal command and is reset in response to deactivation of a corresponding count value. Therefore, it becomes possible to suppress shortening of an active period of the internal command that is output from the input selecting circuit.

Abstract: A latency counter includes a counter circuit and a point-shift FIFO circuit. Latch circuits included in the point-shift FIFO circuit are divided into n groups having wired-OR outputs, and an output of a latch circuit that belongs to a group different from a current group is selected each time a count value is updated. Therefore, an output load is reduced compared to a case where outputs of all the latch circuits are bundled in a wired-OR connection. Further, because there is no need to provide a reset circuit corresponding to each wired-OR wire, it is possible to achieve a reduction in the circuit scale. Furthermore, because a waveform of a signal flowing in the wired-OR wire does not change in a state where internal commands are continuously created in n clock cycles, it is possible to achieve a reduction in the power consumption.

Abstract: A latency counter includes an input selecting circuit that selects one of a plurality of signal paths and supplies an internal command to the selected signal path, a shift circuit that switches a correspondence relation between the signal paths and a latch circuit, and an output selecting circuit that causes the internal command taken in the latch circuit to be output. The input selection circuit includes a timing control circuit allocated to each of the signal paths. The timing control circuit includes an SR latch circuit that is set by the internal command and is reset in response to deactivation of a corresponding count value. Therefore, it becomes possible to suppress shortening of an active period of the internal command that is output from the input selecting circuit.

Abstract: To include an AL counter that outputs a second ODT signal after counting a clock signal by an additive latency after receiving a first ODT signal, and a counter control circuit that controls the AL counter such that the second ODT signal having the same logic value as a logic value of the first ODT signal at a time of shifting from an asynchronous mode to a synchronous mode is output during a period until when at least the clock signal is input by an additive latency after the shifting. With this configuration, an interruption of an CDT operation can be prevented without separately providing a CKE counter. Therefore, the circuit scale can be reduced and the power consumption can be also reduced.

Abstract: A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal.

Abstract: The semiconductor memory device executes, in address units, operation for inverting data stored in a memory cell designated by an internal address and writing the data in the memory cell and increments the internal address every time inversion writing operation for the memory cell is executed.

Abstract: A method of reading a nonvolatile memory device may include, after an nth erase operation is performed, reading dummy cells on which a program operation has been performed based on a first read voltage, where n is an integer greater than zero, counting a number of dummy cells that are read as having a threshold voltage lower than the first read voltage, when the number is a critical value or more, resetting a read voltage, and performing, based on the reset read voltage, a read operation on memory cells that belong to the same memory cell block as the dummy cells and on which a program operation has been performed on the memory cells after the nth erase operation has been performed.

Abstract: A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row address. A refresh counter in the DRAM generates refresh row addresses that are used to refresh rows of memory cells. The refresh row addresses are compared to the subsets of row addresses that are stored in the register. In the event of a match, the row of memory cells corresponding to the matching subset of bits is refreshed. The number of refreshes occurring each refresh cycle will depend upon the number of bits in the subset that are omitted from the row address. The memory cells that are unable to retain data bits are identified by a modified sense amplifier.

Abstract: An oscillating device including: an oscillator generating an oscillation signal according to an enable signal; a counter counting an oscillation number of the oscillation signal and being able to reset at the oscillation number indicated by a first signal; and a comparator comparing the counted oscillation number and a reference number, is provided.

Abstract: To provide a latency counter capable of increasing the signal quality of outputted internal commands. There is provided a point-shift FIFO circuit controlled by count values of a counter circuit. The point-shift FIFO circuit includes: a first wired-OR circuit that combines outputs of first latch circuits; a second wired-OR circuit that combines outputs of second latch circuits; a gate circuit that combines outputs of the first and second wired-OR circuits; and reset circuits that reset the first and second wired-OR circuits, respectively, based on the count value of the counter circuit. According to the present invention, as compared to a case that outputs of all the latch circuits are wired-OR connected, output loads are more reduced. Thus, a high signal quality can be obtained.

Abstract: Provided are memory devices and read level controlling methods. A memory device may include: a memory cell array that includes a plurality of memory cells; a counter that counts a number of memory cells with a threshold voltage included in a reference threshold voltage interval among the plurality of memory cells; a first decision unit that compares the counted number of memory cells with a threshold value to thereby decide whether to set a read level based on the reference threshold voltage interval; and a second decision unit that generates a new reference threshold voltage interval based on the comparison result between the counted number of memory cells and the threshold value.

Abstract: A semiconductor memory device includes a mask information storage circuit that stores therein mask information indicating an area for which the self refresh operation is not performed among a plurality of areas in a memory cell array, a mask determining circuit that is activated by a self refresh command and generates a match signal in response to a detection of a match between a refresh address and the mask information, and a refresh operation control circuit that disables the self refresh operation in response to an activation of the match signal. When a test mode signal is activated, the mask determining circuit is also activated by the auto refresh command. With this configuration, it is possible to perform a test of a partial array self refresh function without actually entering a self refresh mode.

Abstract: A semiconductor memory device includes a thermosensor that senses present temperatures of the device and confirms whether the temperature values are valid. The thermosensor includes a temperature sensing unit, a storage unit and an initializing unit. The temperature sensing unit senses temperatures in response to a driving signal. The storage unit stores output signals of the temperature sensing unit and outputs temperature values. The initializing unit initializes the storage unit after a predetermined time from an activation of the driving signal. A driving method includes driving the thermosensor in response to the driving signal, requesting a re-driving after a predetermined time from the activation of the driving signal, and re-driving the thermosensor in response to the driving signal input again.

Abstract: According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.

Abstract: A counter circuit is configured to simultaneously maintain individual character match count values for a plurality of overlapping substrings of an input string of characters that match a portion of a regular expression stored in a plurality of rows of content addressable memory (CAM) cells of a ternary CAM device. The counter circuit is selectable between a normal operational mode in which all matching portions of the input string are identified, and a minimum match length operational mode in which only matching portions of the input string that have at least a specified minimum number of characters are identified.

Abstract: A counter control signal generator comprises a first pulse signal generator configured to generate a first pulse signal including a pulse generated when a self-refresh period is terminated, a second pulse signal generator configured to generate a second pulse signal including a pulse generated in sync with a cyclic signal generated during a refresh period, and a signal generator configured to generate a counter control signal counting an address of a memory cell, corresponding to a memory cell on which a refresh operation is conducted, in response to the first and second pulse signals.