Hardware For Storage Elements Patents (Class 365/52)
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Patent number: 8144538Abstract: A semiconductor device to improve layout uniformity may include an active region formed in a substrate, a dummy active region formed in the substrate and separated from the active region, a word line crossing over the active region, and a dummy word line. The dummy word line is formed over the dummy active region to overlap at least part of the dummy active region and may have an end positioned within the dummy active region.Type: GrantFiled: January 15, 2009Date of Patent: March 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Sung Hoon Kim
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Patent number: 8144497Abstract: A semiconductor die having a functional circuit (e.g., a memory array) and a decode circuit suitable for use in a stacked die semiconductor component (e.g., a random access memory component) is described. The decode circuit permits individual die in a stacked die structure to automatically determine their location or position in the stack and, in response to this determination, selectively pass one or more external control signals (e.g., chip select and clock enable signals) to the decode circuit's associated functional circuit based on inter-die connection patterns. This “self-configuring” capability permits all die designated for a specified functionality (e.g., a memory module including four vertically aligned die) to be uniformly or consistently manufactured. This, in turn, can reduce the cost to manufacture stacked die components.Type: GrantFiled: August 4, 2009Date of Patent: March 27, 2012Assignee: Micron Technology, Inc.Inventor: Paul Silvestri
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Patent number: 8139386Abstract: Embodiments of the present invention provide local checkpoint memories that are closely coupled to the processor of a computing system used during normal operation. The checkpoint memory may be coupled to the processor through a peripheral bus or a memory bus. The checkpoint memory may be located on a same semiconductor substrate or circuit board as the processor. The checkpoint memory may be located on a same semiconductor substrate as a main memory used by the processor during normal operation. The checkpoint memory may be included in a memory hub configuration, with a checkpoint memory hub provided for access to the checkpoint memory.Type: GrantFiled: April 21, 2008Date of Patent: March 20, 2012Assignee: Micron Technology, Inc.Inventor: Dean A. Klein
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Patent number: 8130527Abstract: Some embodiments include apparatus and methods having dice arranged in a stack. The dice include at least a first die and a second die, and a connection coupled to the dice. The connection may be configured to transfer control information to the first die during an assignment of a first identification to the first die and to transfer the control information from the first die to the second die during an assignment of a second identification to the second die.Type: GrantFiled: September 11, 2008Date of Patent: March 6, 2012Assignee: Micron Technology, Inc.Inventor: Brent Keeth
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Patent number: 8125810Abstract: An integrated circuit (200) includes a semiconductor memory device (202) operative for determining match between received search data and stored data in a plurality of ternary content addressable memory (TCAM) bitcells (100). The plurality of TCAM bitcells (100) each include bit storage including a pair of memory cells (102-0, 102-1) for holding stored data. The TCAM bitcells (100) also include bit comparison circuitry (104) operative for comparing between the stored data and search data on a search line coupled to the TCAM bitcell, wherein the bit comparison circuitry includes a static logic gate operable to provide a match output signal exclusive of a pulsed input. Match circuitry (205) is coupled to receive the match output signal (108) from the plurality of TCAM bitcells (100) for determining whether a match is present for a given search word.Type: GrantFiled: April 29, 2008Date of Patent: February 28, 2012Assignee: Texas Instruments IncorporatedInventor: Patrick W. Bosshart
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Patent number: 8111534Abstract: Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of a plurality of memory circuits in a system. The memory circuits may be stacked and may also be ranked memory circuits. The global memory select signal may be sent to a counter. Such a counter could count the length of time that the global memory select signal is active, and based on the counting, sends a count signal to a comparator. The comparator may compare the count signal with a programmed value to determine if a specific memory chip and/or port is to be accessed. This configuration may be duplicated over multiple ports on the same memory device, as well as across multiple memory ranks.Type: GrantFiled: May 17, 2011Date of Patent: February 7, 2012Assignee: Micron Technology, Inc.Inventor: Robert Walker
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Patent number: 8108591Abstract: A semiconductor device includes first and second interfaces, and a control unit. The first interface is capable of being connected to a memory card and communicating with the memory card. The memory card has a nonvolatile semiconductor memory and has an unlock state and a lock state. The memory card in the unlock state permits an access to the nonvolatile semiconductor memory. The memory card in the lock state prohibits the access. The second interface is capable of being connected to a host device and communicating with the host device. The host device generates an access command to access the memory card. The control unit operates based on the access command sent from the host device through the second interface so as to release the lock state of the memory card, when the memory card is connected to the first interface.Type: GrantFiled: August 14, 2008Date of Patent: January 31, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Takafumi Ito
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Patent number: 8102690Abstract: A chip system that has reduced power consumption under specific operational modes includes: a DDR3 chip that includes: a plurality of pads, disposed at the center of the DDR3 chip; and an array of banks, each bank having a specific logical address, surrounding the pads. The chip system further includes: a clock, coupled to the DDR3 chip, for controlling a rate of data transmission; and a memory controller, coupled to the clock, for coordinating transmitted data with relevant processes, and for selectively reassigning the bank logical addresses according to a specific operational mode.Type: GrantFiled: October 12, 2009Date of Patent: January 24, 2012Assignee: Nanya Technology Corp.Inventors: Richard Michael Parent, Ryan Andrew Jurasek, Dave Eugene Chapmen
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Patent number: 8102699Abstract: A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set at a resistance value. While a selected bit line is set at a certain potential, word lines coupled to different memory cells, which are coupled in common to the selected bit line, are sequentially driven, so that different memory cells are accessed in a time-divisional mode.Type: GrantFiled: December 13, 2010Date of Patent: January 24, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Haruki Toda
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Patent number: 8085544Abstract: A data card includes a casing, a circuit board in the casing, a plug electrically connected with the circuit board and a cap part capable of covering the plug; wherein one end of the casing is provided with the plug; a card slot is defined in the casing at a joint of the casing and the plug, and the cap part covers a notch of the card slot when the plug is inserted into the cap part. The invention is mainly used in wireless data signal receiving or transmitting device.Type: GrantFiled: April 20, 2011Date of Patent: December 27, 2011Assignee: Huawei Device Co., Ltd.Inventor: Shuai Zhao
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Patent number: 8085569Abstract: Multi-chip package devices and related data programming methods are disclosed. A multi-chip package device includes one or more memory chips and a controller. The one or more memory chips include a single level cell section and a multi level cell section. The controller is configured to control a first data storing operation for storing an input data to the single level cell section and control a second data storing operation for storing the input data stored in the single level section to the multi level cell section during an idle time.Type: GrantFiled: December 14, 2010Date of Patent: December 27, 2011Assignee: Hynix Semiconductor Inc.Inventor: You Sung Kim
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Patent number: 8064236Abstract: In a multi-rank memory module having a terminal resistance of a data input/output pad 13 and a terminal resistance control pad 14 that inputs a signal that controls on/off of the terminal resistance, a high-speed operation is enabled with the aid of an enclosed terminal resistance, even in cases where the number of ranks is greater than that of terminal resistance control terminals (ODT terminals) provided on the memory module. To this end, a terminal resistance control pad 14 of a memory chip 12, having a longer length of an interconnect between a data bus 19 on a module substrate 8 and a data input/output pad 13, is connected to a terminal resistance control interconnect 18 or 21 to control the on/off of the terminal resistance from the ODT terminal. A terminal resistance control pad on a memory chip 11, having a shorter length of an interconnect between the data bus 19 on the module substrate and the data input/output pad 13, is connected to a fixed potential 20 to turn on the terminal resistance.Type: GrantFiled: June 3, 2009Date of Patent: November 22, 2011Assignee: Elpida Memory, Inc.Inventors: Yoji Nishio, Atsushi Hiraishi
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Patent number: 8064237Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.Type: GrantFiled: December 21, 2010Date of Patent: November 22, 2011Assignee: Intel CorporationInventors: Peter MacWilliams, James Akiyama, Kuljit S. Bains, Douglas Gabel
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Patent number: 8054663Abstract: A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection path, wherein each one of the stacked plurality of memory chips is characterized by a process variation and actively compensates for said process variation in relation to the reference signal.Type: GrantFiled: November 4, 2008Date of Patent: November 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Hoe-ju Chung
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Patent number: 8036012Abstract: A memory device includes an array of memory modules, a global controller, and a local controller for each memory module in the array of memory modules being configured to deliver to the global controller an activity signal reflecting an activity of the respective memory module. The memory device includes a circuit configured to implement a NAND logic function based upon the activity signals and to output a control signal to the global controller based upon the NAND logic function.Type: GrantFiled: November 16, 2009Date of Patent: October 11, 2011Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Rousset) SASInventors: Claire-Marie Lachaud, Christophe Goncalves
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Publication number: 20110216570Abstract: Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of a plurality of memory circuits in a system. The memory circuits may be stacked and may also be ranked memory circuits. The global memory select signal may be sent to a counter. Such a counter could count the length of time that the global memory select signal is active, and based on the counting, sends a count signal to a comparator. The comparator may compare the count signal with a programmed value to determine if a specific memory chip and/or port is to be accessed. This configuration may be duplicated over multiple ports on the same memory device, as well as across multiple memory ranks.Type: ApplicationFiled: May 17, 2011Publication date: September 8, 2011Applicant: MICRON TECHNOLOGY, INC.Inventor: Robert Walker
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Patent number: 7995365Abstract: Described herein are a method and apparatuses for providing DDR memory access. In one embodiment, an apparatus includes a data storage unit to store and synchronize a plurality of data line signals with a clock signal. The apparatus includes a selector unit that receives the plurality of data line signals and selects two data line signals. The apparatus also includes a double data rate (DDR) output unit that receives the two data line signals from the selector unit and generates a DDR data line signal having a time period substantially one half of a clock time period of the clock signal. The apparatus also includes an input/output (I/O) pad coupled to and locally positioned with respect to the DDR output unit. The data storage unit, the selector unit, and the DDR output unit in combination form an I/O buffer which is locally coupled to the I/O pad.Type: GrantFiled: May 1, 2009Date of Patent: August 9, 2011Assignee: Micron Technology, Inc.Inventors: Elio D'Ambrosio, Ciro Chiacchio, Dionisio Minopoli
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Patent number: 7990746Abstract: A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die.Type: GrantFiled: July 27, 2009Date of Patent: August 2, 2011Assignee: Google Inc.Inventor: Suresh N. Rajan
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Patent number: 7965530Abstract: A memory module includes a plurality of data ports configured to receive/transmit associated data and a plurality of memory devices. The plurality of memory devices include a first set of the memory devices in at least one rank, each memory device of the first set being coupled to each of the associated data ports, and a second set of the memory devices in at least one other rank, each memory device of the second set being configured to receive/transmit the associated data for the memory device through at least each associated memory device of the first set.Type: GrantFiled: December 8, 2008Date of Patent: June 21, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: You-Keun Han, Seung-Jin Seo, Kwan-Yong Jin, Jung-Hwan Choi, Jong-Hoon Kim, Seok-Il Kim, Joo-Sun Choi
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Publication number: 20110128765Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.Type: ApplicationFiled: December 21, 2010Publication date: June 2, 2011Inventors: Peter MacWilliams, James Akiyama, Kuljit S. Bains, Douglas Gabel
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Patent number: 7948786Abstract: Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system, a single external pin receives a global memory select signal which transmits an access signal for one of a plurality of memory circuits in a system. The memory circuits may be stacked and may also be ranked memory circuits. The global memory select signal may be sent to a counter. Such a counter could count the length of time that the global memory select signal is active, and based on the counting, sends a count signal to a comparator. The comparator may compare the count signal with a programmed value to determine if a specific memory chip and/or port is to be accessed. This configuration may be duplicated over multiple ports on the same memory device, as well as across multiple memory ranks.Type: GrantFiled: February 6, 2008Date of Patent: May 24, 2011Assignee: Micron Technology, Inc.Inventor: Robert Walker
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Patent number: 7940543Abstract: A method for dynamically enabling address receivers in a synchronous memory array includes: controlling all address receivers to initially be in an off state; generating a command signal and generating an address signal; delaying the address signal so there is a latency between the command signal and the address signal; and selectively turning on an address receiver corresponding to the address signal when the command signal is received by the synchronous memory array.Type: GrantFiled: March 19, 2008Date of Patent: May 10, 2011Assignee: Nanya Technology Corp.Inventors: Chia-Jen Chang, Phat Truong
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Patent number: 7924592Abstract: Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip.Type: GrantFiled: January 6, 2010Date of Patent: April 12, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Won Kang, Seung-Duk Baek
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Patent number: 7898834Abstract: A semiconductor chip with a chip selection structure suitable for a stacked semiconductor chip includes a semiconductor chip body and a chip selection structure. The chip selection structure includes a chip selection pad disposed over the semiconductor chip body, a main through electrode electrically connected to the chip selection pad, and a sub through electrode interposed between the main through electrode and the chip selection pad. A plurality of the semiconductor chips, each having the same chip selection structure, can be stacked by offsetting the stacked semiconductor chips.Type: GrantFiled: March 31, 2008Date of Patent: March 1, 2011Assignee: Hynix Semiconductor Inc.Inventors: Sung Min Kim, Chang Jun Park, Kwon Whan Han, Seong Cheol Kim, Ha Na Lee
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Patent number: 7898862Abstract: A semiconductor device includes a transfer section which receives, from an external source, a second program for modifying a function of a first program stored in a read-only memory (ROM) and information required in activation of the second program, and which writes the program and the information to a nonvolatile semiconductor memory, and a load section which activates the second program on the basis of the information written to the nonvolatile semiconductor memory to modify the function of the first program.Type: GrantFiled: November 27, 2009Date of Patent: March 1, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Murakami, Takashi Oshima
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Patent number: 7894232Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.Type: GrantFiled: April 21, 2009Date of Patent: February 22, 2011Assignee: Hitachi, Ltd.Inventors: Satoru Hanzawa, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Saen
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Patent number: 7872892Abstract: In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The memory array in the memory integrated circuit stores data. The register includes one or more bit storage circuits to store one or more identity bits of an identity value. The control logic provides independent sub-channel memory access into the memory integrated circuit in response to the one or more identity bits stored in the register.Type: GrantFiled: July 5, 2005Date of Patent: January 18, 2011Assignee: Intel CorporationInventors: Peter MacWilliams, James Akiyama, Kuljit S. Bains, Douglas Gabel
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Patent number: 7859885Abstract: A phase change memory device includes a substrate, a plurality of cell arrays stacked above the substrate and each including a matrix layout of a plurality of memory cells, each the memory cell storing therein as data a resistance value determinable by a phase change, a write circuit configured to write a pair cell constituted by two neighboring memory cells within the plurality of cell arrays in such a manner as to write one of the pair cell into a high resistance value state and write the other into a low resistance value state, and a read circuit configured to read complementary resistance value states of the pair cell as a one bit of data.Type: GrantFiled: January 7, 2008Date of Patent: December 28, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Haruki Toda
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Patent number: 7855925Abstract: A multi memory chip stacked on a multi core CPU includes a plurality of memories, each memory corresponding to a CPU core from among the CPU cores and being configured to directly transmit data between the other memories of the multi memory chip.Type: GrantFiled: February 26, 2008Date of Patent: December 21, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Uk-song Kang, Jung-bae Lee
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Patent number: 7852654Abstract: The present invention relates to a semiconductor device including a MLC capable of storing plural bits of data, wherein some of the MLC are set and operated as a buffer section in response to a control signal.Type: GrantFiled: December 17, 2007Date of Patent: December 14, 2010Assignee: Hynix Semiconductor Inc.Inventor: You Sung Kim
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Patent number: 7843758Abstract: A method for reading status data from a multi-chip memory device including pluralities of memory chips is comprised of: providing a command to request an output of the status data to the plurality of memory chips; and accepting the status data of the plurality of memory chips through multiple channels of the multi-chip memory device. The reading method of the status data is helpful to shortening a standby time for accepting the status data of the multi-chip memory device, enhancing an operation rate.Type: GrantFiled: November 20, 2007Date of Patent: November 30, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Dae-Seok Byeon
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Patent number: 7821803Abstract: A memory module having a start-type topology and a method of fabricating the same are provided. The memory module includes a substrate. Memory devices are mounted on the substrate in at least two rows and at least two columns. A star-type topology is disposed to be electrically connected to the memory devices. One or more pairs of adjacent ones of the memory devices have a point-symmetric structure.Type: GrantFiled: August 6, 2008Date of Patent: October 26, 2010Assignee: Samsung Electronics, Co., Ltd.Inventors: Do-Hyung Kim, Byoung-Ha Oh, Young-Jun Park, Yong-Ho Ko
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Patent number: 7813175Abstract: A smart card is formed of a memory having light-sensing cells to sense externally supplied light and generate a detection signal in response to the externally supplied light being sensed by the light-sensing cells, and a reset control circuit generating a reset signal in response to the detection signal, the reset signal operating to reset the smart card.Type: GrantFiled: November 27, 2007Date of Patent: October 12, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Min-Kyu Kim
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Patent number: 7808805Abstract: A column address control circuit comprises a control unit for outputting a control signal in response to a DDR mode signal and a first signal, and an address counting unit configured to receive a start column address and output a start column address in response to the control signal. The first signal is a burst read single write mode signal. The control signal is activated when the first signal is activated in a DDR mode. The control unit includes a first logic unit for performing an AND operation of the DDR mode signal and the first signal, and a second logic unit for performing an OR operation of an output signal of the first logic unit and a SDR mode signal.Type: GrantFiled: December 27, 2007Date of Patent: October 5, 2010Assignee: Hynix Semiconductor Inc.Inventor: Bok Rim Ko
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Patent number: 7796414Abstract: A memory module, system and method of making the same includes a memory module including a plurality of memory devices having a first portion of memory devices cooperatively forming a first rank of memory devices and a second portion of memory devices cooperatively forming a second rank of memory devices. The first and second portions of memory devices are grouped into a plurality of memory device stacks, wherein each of the plurality of memory device stacks includes at least one of the plurality of memory devices coupled to a first portion of a plurality of DQ signals and at least another one of the plurality of memory devices coupled to a different second portion of the plurality of DQ signals.Type: GrantFiled: December 30, 2008Date of Patent: September 14, 2010Assignee: Micron Technology, Inc.Inventor: Joseph Hofstra
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Patent number: 7796457Abstract: An exemplary motherboard includes a first slot arranged for mounting a first type of memory, a second slot arranged for mounting a second type of memory, a voltage regulator electronically connected to the first slot and the second slot, and a serial presence detect (SPD) unit connected to the voltage regulator. The first memory and the second memory alternatively mounted on the motherboard, the SPD detects which type of memory is mounted on the motherboard, and the voltage regulator outputs voltages suitable for the type of the memory mounted on the motherboard according to a detection result of the SPD.Type: GrantFiled: June 21, 2007Date of Patent: September 14, 2010Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Shou-Kuo Hsu, Duen-Yi Ho, Cheng-Shien Li
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Patent number: 7791918Abstract: A method for use with devices in a stacked package is discussed. By preprogramming a unique identifier into a device during manufacture, the device can determine its position in the stack and perform a task based on its position in the stack. In one embodiment, the task is power-up.Type: GrantFiled: September 27, 2007Date of Patent: September 7, 2010Assignee: Intel CorporationInventor: Paul Ruby
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Patent number: 7786513Abstract: In a semiconductor integrated circuit device, from a first power source strap supplying a potential to a first standard cell receiving a supply of the potential, the potential is supplied via a first cell power source line having a constant width. The width of the first cell power source line is determined in accordance with power consumed by the first standard cell and with the number of standard cells that can be placed between the first power source strap and a third power source strap.Type: GrantFiled: March 2, 2007Date of Patent: August 31, 2010Assignee: Panasonic CorporationInventor: Masanori Tsutsumi
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Patent number: 7787276Abstract: A method for controlling a memory array using a mechanical switch according to the present invention, in which the memory array comprises; a plurality of word lines; a plurality of bit lines intersecting each other with the plurality of word lines; a gate electrode connected to each of the word lines; a drain electrode spaced apart from the gate electrode and connected to a capacitor; and a source electrode comprises: an anchor part spaced apart from the gate electrode and connected to each of the bit lines; a mobile part where a dimple is formed, comprises the steps of: applying a first voltage V1 to the bit line selected from the plurality of bit lines; applying a second voltage V2 greater than a sum of the first voltage V1 and a pull-in voltage Vpi to the word lines selected from the plurality of word lines; and applying a voltage smaller than a sum of a erase voltage Verase and the pull-in voltage Vpi and a voltage greater than a difference between a write voltage Vwrite and the pull-in voltage Vpi to theType: GrantFiled: May 16, 2008Date of Patent: August 31, 2010Assignee: Korea Advanced Institute of Science and TechnologyInventors: Jun-Bo Yoon, Weon-Wi Jang, Jeong-Oen Lee
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Patent number: 7773402Abstract: A first signal input circuit outputs a first control signal in response to self-refresh and active signals. A second signal input circuit outputs a second control signal in response to the self-refresh and active signals. The power supply circuit applies a first supply voltage to an output terminal in response to the first control signal. An elevated voltage generator generates a elevated voltage by pumping a second supply voltage, and applies the elevated voltage to the output terminal, in response to the first and second control signals.Type: GrantFiled: June 12, 2009Date of Patent: August 10, 2010Assignee: Hynix Semiconductor Inc.Inventors: Sang Park, Shin Ho Chu
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Patent number: 7773420Abstract: An integrated circuit memory system includes a random access memory device, a flash memory device and a memory controller, which may be embodied on a single integrated circuit substrate. The memory controller is configured to respond to at least one command to write data into the flash memory device by first writing the data into the random access memory device and then transferring the data from the random access memory device to the flash memory device. The random access memory device may be a NOR-type flash memory device and the flash memory device may be a NAND-type flash memory device.Type: GrantFiled: April 5, 2007Date of Patent: August 10, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Gwang-Myung Kim
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Patent number: 7768111Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.Type: GrantFiled: January 4, 2008Date of Patent: August 3, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Hiroshi Iwasaki
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Patent number: 7746719Abstract: Disclosed is a multi-chip package having a plurality of memory chips. Each memory chip includes a memory cell array storing e-fuse data, a read-out control circuit reading e-fuse data in response to a read signal, a first internal pad receiving a first control signal, a read-out controller generating the read signal to define a read period, and to generate a second control signal following the read period, and a second internal pad receiving the second control signal, wherein the plurality of memory chips is connected series and each respective read-out control circuit and read-out controller in each one of the plurality of memory chips cooperate to implement a sequential read of e-fuse data across the plurality of memory chips.Type: GrantFiled: July 22, 2008Date of Patent: June 29, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Sang-Gu Kang
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Patent number: 7738276Abstract: A first region having a first pattern which includes a first minimum dimension, a second region having a second pattern which includes a second minimum dimension larger the first minimum dimension, the second region being arranged adjacent to the first region, wherein a boundary between the first region and the second region is sectioned by a width which is twice of more of a minimum dimension which exists in an adjacent region.Type: GrantFiled: July 8, 2008Date of Patent: June 15, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Kosuke Yanagidaira, Takuya Futatsuyama, Toshiya Kotani
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Patent number: 7733680Abstract: A non-volatile memory module for preventing system failure and a system including the same, in which the non-volatile memory system includes a first socket and a second socket each having a notch coupler, a first memory module, a memory controller configured to control the first memory module, and a printed circuit board on which the memory controller and the first and second sockets are installed and electrical signal lines are formed between the memory controller and the first and second sockets. The first memory includes a plurality of non-volatile memory devices and stores system software. The first memory module has a structure such that it can be installed at the first socket but cannot be installed at the second socket. The non-volatile memory system may further include a second memory module for an extension of the memory capacity. The second memory module has a structure such that it can be installed at the second socket but cannot be installed at the first socket.Type: GrantFiled: December 21, 2007Date of Patent: June 8, 2010Assignee: Samsung Electronics Co., Ltd.Inventor: Jeon-Taek Im
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Patent number: 7729153Abstract: A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.Type: GrantFiled: April 2, 2008Date of Patent: June 1, 2010Assignee: International Business Machines CorporationInventors: Daniel M. Dreps, Frank D. Ferraiolo, Kevin C. Gower, Mark W. Kellogg, Roger A. Rippens
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Publication number: 20100085791Abstract: A driving apparatus (100c) is provided with: a base portion (110); a stage portion (130) on which a driven object (12) is mounted and which can be displaced; an elastic portion (120) which connects the base portion and the stage portion and which has elasticity to displace the stage portion in one direction (Y axis); and a first applying device (161, 162, 22) for applying, to the base portion, an excitation force for displacing the stage portion such that the stage portion is resonated in the one direction at a resonance frequency determined by the stage portion and the elastic portion.Type: ApplicationFiled: March 30, 2007Publication date: April 8, 2010Applicant: Pioneer CorporationInventor: Jun Suzuki
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Patent number: 7692944Abstract: An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.Type: GrantFiled: May 27, 2008Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Paul W. Coteus, Philip G. Emma
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Patent number: 7684224Abstract: An integrated circuit design, structure and method for fabrication thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.Type: GrantFiled: June 26, 2007Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Kerry Bernstein, Paul William Coteus, Philip George Emma
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Patent number: 7663903Abstract: Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip.Type: GrantFiled: September 28, 2007Date of Patent: February 16, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sun-Won Kang, Seung-Duk Baek