Abstract: A printed circuit assembly for use in an implantable medical device comprises a plurality of panels having active and passive circuit components on one major surface thereof, the plurality of panels being interconnected with flexible flat cable segments allowing the assembly to be folded so as to place the individual panels carrying the circuit components in a stacked relationship. By providing conductive layers on predetermined surfaces of the panels, shielding is provided to inhibit noise generating circuitry from contaminating wanted signals passing between the components and the plural panels.

Abstract: A memory module is described which can be programmed with module information, identifying the type and size of the memory module, after completed assembly of the memory module. The memory module includes a plurality of edge connectors for electrically connecting the memory module circuitry external to the memory module, and a plurality of DRAM memory devices electrically connected to corresponding edge connectors for receiving and providing data from and to the external circuitry. The memory module also includes a Serial EEPROM for storing the module information. The Serial EEPROM has a Serial Data pin connected to a first of the edge connectors for providing the module information to the external circuitry. The Serial EEPROM has a Write Control pin for receiving an enabling signal which selectively enables the operation of the Serial EEPROM in Write or Read-Only mode. The memory module further includes interface circuitry which couples the Write Control pin with a second and a third of the edge connectors.

Abstract: A communications method is described in which two memory modules receive data and commands from a controller module via a common data and command bus. The memory modules contain active line terminations. By a second chip select input, one of the memory modules can monitor the write commands that pass from the controller module to the other memory module, and thus activate the line terminal in the monitoring memory module.

Abstract: In some embodiments, the invention includes a system having first and second modules and a circuit board including first and second module connectors to receive the first and second modules, respectively. The system includes a first path of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector, to the second module, and to on module terminations of the second module; and a second path of conductors extending from the circuit board to the second module connector, to the second module, back to the second module connector, to the circuit board, to the first module connector, to the first module, and to on module terminations of the first module.

Abstract: In some embodiments, the invention includes a system having first and second modules; and a circuit board including first and second module connectors to receive the first and second modules, respectively. A first path of conductors extending from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector and to the second module, and wherein the first path in the first module couples to stubs for first and second chips of the first module and the first path in the second module couples to stubs for first and second chips of the first module; and each of the first and second chips include selectable on die terminations.

Abstract: Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

Abstract: A high-density low-cost read-only memory circuit is disclosed. Within the memory circuit, a passive device chip, including only passive devices is configured to form a read-only memory array; and an active device chip, having supporting circuitry electrically coupled to the memory array. The passive chip may include amorphous or poly-Silicon diodes; the supporting circuitry may include bit-line, word-line, address decoder; sense amplifier, and output driver circuitry. The memory array may further include a first memory array; and a second memory array, deposited upon the first memory array layer, together forming a three-dimensional multi-layer compact memory circuit. The passive and active chips may be coupled together and encapsulated within a multi-chip module (MCM) package. The MCM package may further include any number of additional passive memory arrays connected to the active chip.

Abstract: A data writing system capable of writing data in at least one electrically rewritable ROM mounted on target board, comprising: a transportation unit for transporting the target board to a predetermined writing position at which data is to be written, a data writing unit for writing data in the ROM mounted on the target board, and a connection unit for electrically connecting the ROM mounted on the target board at the predetermined writing position with the data writing unit through at least one transmission line extending from the ROM.

Abstract: Methods and apparatus for a memory system using a branching point-to-point memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains a point-to-point bus connection with one memory module and that memory module maintains a separate point-to-point bus connection with a second module. Data passing between the memory controller and the second memory module passes through a buffer circuit on the first memory module. For data received from the memory controller, the buffer circuit also passes that data up a module bus segment to a first bank of memory devices. That bank of memory devices maintains a second module bus segment with a second bank of memory devices. Data passing between the buffer circuit and the second bank of memory devices passes through a pass-through circuit on the first bank of memory devices. In this manner, a point-to-point memory bus architecture can be maintained even when a memory module contains more than one bank of memory devices.

Abstract: There is provided a semiconductor integrated circuit having a multi level interconnect structure comprising: a first wiring connected to a transistor region formed in a semiconductor substrate; an interlayer dielectric formed on this topography; first and second contacts formed in the interlayer dielectric; and a second wiring connected electrically to the first wiring via the first and second contacts, this circuit further including switching means, connected to said first and second wirings respectively, for feeding a high potential and a low potential alternately.

Abstract: The present invention utilizes a buffer to isolate a stack of memory devices, thereby taking advantage of the increased memory density available from stacked memory devices while reducing capacitive loading. A memory module in accordance with the present invention may include a stack of memory devices and a buffer coupled to the first and second memory devices and arranged to capacitively isolate the first and second memory devices from a bus. In a memory system in accordance with the present invention, multiple buffered stacks of memory devices are preferably coupled in a point-to-point arrangement, thereby further reducing capacitive loading.

Abstract: A memory module MM, in which a module wiring substrate 5 is equipped with function switching means KK1 and KK2 for arbitrarily switching function switching signals to be inputted to function switching pins FP0 and FP1 of memories 1. By these function switching means KK1 and KK2, moreover, the function switching signals are arbitrarily switched from any of no connection, a supply voltage Vcc and a ground potential Vss. These signals are inputted altogether to all the mounted memories 1 to switch and arbitrarily set functions including reading modes and refresh cycles.

Abstract: A memory module for an electronic device is disclosed which provides means for reducing the amount of power necessary to access a desired number of data bits. This provides a design of memory modules which requires fewer DRAMs to be turned on during a read or write cycle than present module designs, thereby using much less power.

Abstract: A data bus architecture for integrated circuit embedded dynamic random access memory (“DRAM”) having a large aspect ratio (length to width ratio) which serves to reduce power requirements in the data path through the use of multiple metal layers to reduce capacitance on the data busses. This architecture is particularly advantageous for use in addressing data bussing problems inherent in integrated circuit devices having embedded DRAM with a large aspect ratio as well as a relatively large number of input/outputs (“I/Os”) which must be located along one narrow side of the memory. In accordance with the present invention, the memory is divided into multiple sections with data bussing in those sections routed in one metal, or conductive, layer. A different metal layer is used to route global data across these sections to a data register located on one edge of the memory.

Abstract: The present invention discloses a method and system to optimize electrical interconnection of electrical components in a periphery area of a memory device thereby minimizing the periphery area. The periphery area is divided into a plurality of sub-circuits formed by selectively electrically connecting the electrical components. Electrical interconnection of the electrical components to form the sub-circuits is accomplished using a first metal layer and a second metal layer. The first metal layer is formed to create a plurality of first metal layer lines that are oriented to extend in substantially one direction on the memory device. The second metal layer is formed to create a plurality of second metal layer lines that are oriented to extend substantially perpendicular to the first metal layer lines.

Abstract: Disclosed is a dynamic random access memory (DRAM) device having word line low voltage supply lines for driving word lines in a mesh structure. The DRAM device includes a plurality of cell arrays each of which is formed of memory cells coupled to word lines and bit lines in a matrix. The memory device further includes regions of sense amplifiers disposed between the cell arrays arranged along the row direction, regions of word line drivers disposed between the cell arrays arranged along the column direction, conjunction regions disposed at positions adjacent to the regions of the sense amplifiers and word line drivers, and a plurality of word line low voltage supply lines disposed on the conjunction regions. The word line low voltage supply lines are electrically interconnected for each other at least on the conjunction regions. According to the layout arrangement, loadings of the word line low voltage supply lines are almost equally distributed, and thereby word line low noise are decreased.

Abstract: Disclosed are semiconductor devices having terminal arrangements in which mirrored pairs of the semiconductor devices can be tested by a common test device.

Abstract: A memory module for preventing skew between bus lines is provided. The memory module includes a printed circuit board, memory chips, module tabs and bus lines. The memory chips are disposed on the printed circuit board, and the module tabs are disposed at one edge of the printed circuit board. The bus lines are connected to the module tabs, respectively, and are connected to the memory chips. Each of the bus lines is formed a closed circuit loop. Each of the bus lines is connected to the memory chips through a circuitous or roundabout path which includes first and second paths of, in general, different lengths. The first and second paths of the roundabout path branch from each other at a position on the closed circuit loop. Since each bus line on the memory module forms a closed loop, skew does not occur between control signals or output data, which are transmitted through the bus line.

Abstract: Disclosed is a memory device, comprising a memory controller, a clock input pin for receiving a clock signal, a first chip selection signal input pin for receiving a first chip selection signal for a row address strobe from the memory controller, a second chip selection signal input pin for receiving a second chip selection signal for a column address strobe from the memory controller, a row command input pin for receiving a row command from the memory controller, a column command input pin for receiving a column command from the memory controller, a plurality of row address input pins for receiving row addresses from the memory controller, and a plurality of column address input pins for receiving column addresses from the memory controller.

Abstract: A module substrate has a plurality of module data terminal pairs individually provided in association with respective chip data terminals in a plurality of memory chips, and a plurality of module data wirings which respectively connect between the plurality of module data terminal pairs. The plurality of module data wirings are connected to their corresponding chip data terminals and are configured so as to be available as a memory access data bus. In a memory system in which a plurality of memory modules are arranged in parallel, module data wirings of each of the individual memory modules are connected in serial form, and each of the individual module data wirings do not constitute branch wirings with respect to a data bus on a motherboard of the memory system. In the memory modules, parallel access for the number of bits corresponding to the width of the memory access data bus is assured.

Abstract: Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

Abstract: A multichip semiconductor package provides redundancy mapping from one semiconductor chip to another. The semiconductor device can be salvaged, where normally it normally would be considered scrap. This is particularly important where multiple semiconductor chips are physically connected as a common unit. One multichip integrated circuit package has semiconductor chips integrally formed on a unitary substrate, and each semiconductor chip includes redundant circuitry adapted to selectively replace primary circuitry. Electrical interconnects couple the redundant circuitry from a one semiconductor chip to a second semiconductor chip.

Abstract: A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.

Abstract: A quad in-line memory module (QIMM) includes a circuit board having top and bottom edge connectors and a number of memory devices mounted on each side of the circuit board. Generally, half of the memory devices are electrically connected to the bottom edge's connector and half are electrically connected to the bottom edge's connector. One edge of the QIMM can be connect directly to a computer system's memory bus. The other edge can be connected to operated as a cache memory or a video memory.

Abstract: Disclosed herein is a card having a controller and a clock control circuit. The controller incorporates a core logic, and the clock control circuit incorporates a PLL. When a card becomes idle to wait for commands, the clock control circuit stops the supply of a clock signal to the core logic. The clock control circuit can operate in two clock control modes. In the first clock control mode, the circuit stops the PLL. In the second clock control mode, the circuit shuts off the clock signal to be supplied from the PLL to the controller.

Abstract: The RAMBUS compatible configuration of the present invention is achieved by stacking one of the two modules in the stacked configuration in an upside-down position with respect to the other. This way, the corresponding electrical leads of each memory module will extend on opposite sides of the stacked package and will be securably connected to vertical rails. The vertical rails are electrically and securably connected to the bonding pads which electrically connect to the RAMBUS signal channel. In this embodiment, the electrical leads of one memory module electrically connect to the signal channel at points located on one side of the stacked package and the electrical leads of the other memory module connect to the signal channel at points located on the opposite side of the stacked package. The resulting distance between the points of contact between corresponding leads of each memory module in the stacked package is sufficient to satisfy the requirements of the RAMBUS signal channel.

Abstract: Disclosed is an integrated circuit device with expandable nonvolatile memory characterized in that a control unit and a voltage generator for memory operation are independently integrated into a common circuit instead of included in each single integrated circuit memory device and shared by at least one integrated circuit memory device. Therefore, multiple circuits such as control urn its and voltage generators and the chip area they occupy in each single integrated circuit memory device are reduced, so that not only the chip size and fabrication cost of the integrated circuit memory devices are decreased, but also the memory capacity is more flexible and adaptive for various applications.

Abstract: A diual-die integrated circuit package having two integrated circuit chips “flip chip” attached to each other and with one of the chips being aligned at a specified angle in relation to the other chip to allow access to bonding pads on the surface of each chip for wirebonding connection into the chip package. In a first embodiment, the two chips are rectangular in shape and are aligned at an angle of 90 degrees with respect to each other, thus allowing the end portions of the bottom chip to be accessible for connection into the chip package. Other embodiments maintain the chips at angles of less than 90 degrees, such that corner portions of each chip are accessible for connection into the chip package. The invention allows two identically constructed chips to be used for doubling or even greater multiplication of the functionality or memory of the IC package, while still using the same package footprint as for a single chip.

Abstract: A memory system configured to provide thermal regulation of a plurality of memory devices is disclosed. The memory system comprises a memory module having a plurality of memory devices coupled to a bus. Additionally, the memory system also comprises a controller coupled to the bus. The controller determines an operating temperature (actual or estimated) of the memory device. Based on the determined operating temperature of the memory device, the controller is further operable to manipulate the operation of the memory system.

Abstract: A memory module is described which can be programmed with module information, identifying the type and size of the memory module, after completed assembly of the memory module. The memory module includes a plurality of edge connectors for electrically connecting the memory module circuitry external to the memory module, and a plurality of DRAM memory devices electrically connected to corresponding edge connectors for receiving and providing data from and to the external circuitry. The memory module also includes a Serial EEPROM for storing the module information. The Serial EEPROM has a Serial Data pin connected to a first of the edge connectors for providing the module information to the external circuitry. The Serial EEPROM has a Write Control pin for receiving an enabling signal which selectively enables the operation of the Serial EEPROM in Write or Read-Only mode. The memory module further includes interface circuitry which couples the Write Control pin with a second and a third of the edge connectors.

Abstract: A memory address driver circuit with memory module slots on a computer main board that can be divided into two groups. One group of memory module slots includes the slots whose trace line to a control chipset is smaller than 2500 mils or closest to the control chipset. The other group of memory module slots includes all the remaining slots. The control chipset includes two memory control circuits. The memory control circuit for supporting DDR DRAM is connected to the address leads of the memory module slot closest to the control chipset. However, no terminal resistors are connected to any address leads of the memory module slot. Hence, engineers may have to design one set of terminal resistors only. In addition, the memory control circuit uses one-cycle access command timing to boost system performance.

Abstract: A package according to the invention comprises at least two integrated circuit (IC) chips encapsulated therein. Each of the IC chips has its option pad, and the option pads of the IC chips are biased, at the package level, to different logic levels so as to distinguish between the IC chips. Particularly, the chips of the present invention have identical address coding scheme and are each comprised of a memory cell array for storing data; a command register for activating one of master signals each indicative of a read mode, a program mode and an erase mode in response to an externally applied command; and a chip disable circuit coupled to a corresponding option pad, for determining whether or not a corresponding semiconductor memory device is selected, and for resetting the command register so as to disable the activated master signal when the corresponding semiconductor memory device is unselected.

Abstract: A terminating circuit module and a computer system using the same, in which a voltage regulator and a plurality of pull-up resistors can be provided on the terminating circuit module by the mainboard producer to reduce the area of the printed circuit board of the mainboard. Also, a nonvolatile memory can be provided on the terminating circuit module to store the information representing such terminating circuit module. The computer can automatically read the configuration of the memory and the terminating circuit module such as the slotted positions for the terminating circuit module and the memory module to prevent users from using the terminating circuit module in an incorrect way.

Abstract: A method for accessing a memory array for an electronic device comprises a design which requires fewer memory devices to be activated to access a plurality of data bits, thereby reducing the amount of power required to access the data bits. The design comprises the use of a plurality of memory devices, each of which has a plurality of arrays and data out lines.

Abstract: A computer system for multi-type DRAM support includes a first slot for receiving a first type DRAM, a second slot for receiving a second type DRAM, a north bridge chip, and a control circuit. The first slot includes a plurality of first slot pins, and each of them corresponds to a first pin assignment. The second slot includes a plurality of second slot pins, and each of them corresponds to a second pin assignment. The north bridge chip includes a plurality of chip pins, and each of them corresponds to a first and second pin assignment. When the control circuit generates a first control signal, the pin assignments of the chip pins are defined as the first pin assignments. When the control circuit generates a second control signal, the pin assignments of the chip pins are defined as the second pin assignments.

Abstract: A semiconductor device connected to at least one semiconductor device of the same type. The semiconductor device includes first pins, provided on a first side of the semiconductor device, for receiving signals commonly used with the at least one semiconductor device, and second pins, provided on a second side of the semiconductor device substantially perpendicular to the first side, for being connected to signal lines which are not connected to the at least one semiconductor device.

Abstract: A memory module MM, in which a module wiring substrate 5 is equipped with function switching means KK1 and KK2 for arbitrarily switching function switching signals to be inputted to function switching pins FP0 and FP1 of memories 1. By these function switching means KK1 and KK2, moreover, the function switching signals are arbitrarily switched from any of no connection, a supply voltage Vcc and a ground potential Vss. These signals are inputted altogether to all the mounted memories 1 to switch and arbitrarily set functions including reading modes and refresh cycles.

Abstract: Memory modules and a controller are arranged and two clock lines are provided to go and return along the arrangement of the memory modules and the controller. A first basic clock and a second basic clock having twice the cycle period of the first basic clock are transferred over the go portions of the respective clock lines to the memory modules and the controller. After passing through the turnaround point, the first and second basic clocks are transferred as return clocks over the return portions of the clock lines to the memory modules and the controller. The first and second basic go clocks and the first and second basic return clocks are fed into the memory modules and the controller. The input/output operation of data is controlled synchronously with these clocks.

Abstract: This abstract is being provided in accordance with the provisions of Section 1.72 of the Rules of Practice in Patent and Trademark Cases (37 CFR). The applicant intends that this abstract be used only to aid in determining the general nature of the technical disclosure. The applicant does not intend that this abstract be looked to in order to aid or assist in the determination of the scope of any claim. An electronic module (FIG. 1, 100) includes an upper portion (135) and lower portion (130) of a connector (110) which allows the electronics module to attach to both a second, identical electronics module (200) as well as to motherboard (10). Signals which are intended to terminate on the electronic module (100) are routed directly to the appropriate component (120) on the module.

Abstract: Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2.

Abstract: An assembly comprising at least one device remotely controlled by at least one transmitter (ESA, ESB) possessing an identity number capable of transmitting a signal consisting of a frame containing the identity number (A, B) and a command and a receiver (R1, R2) which are associated with the remotely controlled device (VR1, VR2) and capable of extracting the identity number from the signal received and of storing it. At least one transmitter of the assembly is a transmitter of simple type, that is to say whose signal frame contains an identifier signifying that this transmitter may control only a single receiver and the program contained in the processor of at least one receiver contains a routine for testing and identifying the type of transmitter preventing the recording of additional transmitter identity numbers in the memory if the identity number identified is that of a transmitter of simple type. A transmitter can then control only a single receiver.

Abstract: A plurality of memory modules interface through a daisy-chain providing a point-to-point connection for each memory module. The first and the last memory module in the daisy chain each connect to a separate memory controller port forming a ring circuit. A distinct set of signals connect the memory modules in each direction. A junction circuit in each memory module provides line isolation, a coupling to the adjoining memory modules in the daisy chain, or in the case of the first and last memory module in the daisy chain, a memory module and a memory controller, and a data synchronization circuit. Each junction circuit provides as well as voltage conversion so that the memory devices on a memory module operate at a different voltage than the memory controller, and multiplexing/de-multiplexing so that a lesser number of lines interface with each junction circuit.

Abstract: A dual port memory cell having reduced architecture utilizing silicon on insulator is provided. Each storage capacitor has respective access transistors, for connecting the storage capacitor to two separate digit lines. One of the access transistors connects the capacitor to a first digit line which runs above the silicon on insulator layer while the second access transistor connects the capacitor to a second digit line which runs below the silicon on insulator structure.

Abstract: System modules are described which include a stack of interconnected semiconductor dies. The semiconductor dies are interconnected by micro bump bonding of coaxial lines that extend through the thickness of the various dies. The coaxial lines also are selectively connected to integrated circuits housed within the dies. In one embodiment, a number of memory dies are interconnected in this manner to provide a memory module.

Abstract: A method for transferring programs to an electronic unit, in which the program to be transferred is stored on a plug-in device. The program is transferred to the electronic unit after the plug-in device has been inserted into the electronic unit, the transfer being controlled by a controller in the plug-in device. The method relates in particular to the loading of programs from a plug-in card with a SIM interface to a mobile radio terminal.

Abstract: The invention is directed to a memory controller for use with memory having varying timing characteristics. In particular, the timing characteristics of the various memory devices are determined and used to generate timing signals commensurate with each particular memory device.

Abstract: The present disclosure relates to an upgradable storage system. The storage system comprises a memory device compartment that is adapted to receive memory devices in a stacked orientation, and at least one memory device disposed within the memory device compartment. Typically, each of the memory devices has electrical contacts disposed on top and bottom surfaces of the memory devices with which the memory devices electrically connect to each other. In a preferred arrangement, each memory device comprises an ARS device.

Abstract: The invention pertains to a layout for a semiconductor memory with multiple memory cells. The layout according to this invention takes into account the “design rules” specified by the manufacturing process or those required by the technology, and attempts to optimize the surface area of the layout of the semiconductor memory. The particular advantage of the invention rests in the fact that for each memory cell, effectively only one contact terminal is needed. In this manner, the required surface area for the semiconductor memory can be reduced significantly. Due to the reduction in the number of contact terminals, the leakage currents can also be reduced.

Abstract: An apparatus for testing a semiconductor memory is disclosed, which includes a power control module for varying an output voltage of the power supply unit and supplying to the semiconductor memory in accordance with a power control signal from a CPU(Central Processing Unit) of the main board, and an interface unit for supplying the power control signal from the CPU of the main board to the power control module, thus implementing an accurate operation state of an actual mounting environment of a semiconductor memory device by varying and supplying a certain voltage supplied from a power supply unit when testing whether a semiconductor memory device is defective or not using a main board of a computer apparatus.

Abstract: A memory bar for use in high density memory modules. A memory bar comprises a substrate that provides a mounting for at least two IC chips, such that the substrate and associated IC chips may be mounted, for example, on one side of a memory module.