Abstract: A double capacity stacked memory device. In the present invention, two memory chips each have a plurality of control terminals and address terminals, and two data input/output terminals. The control terminals and address terminals of the first memory chip are electrically coupled to those of the second memory chip correspondingly to serve as control terminals and address terminals of the stacked memory respectively, and the data input/output terminals of the two memory chips construct four data input/output terminals of the stacked memory, such that the stacked memory accesses data in the first and second memory chip simultaneously according to an access command, and is thus suitable for double capacity memory devices in a standard package.

Abstract: A substrate pad VREFT provided outside of the mold resin and word line driving voltage generation circuits within a plurality of bare chips are electrically connected only through electrical wires on a module substrate. Therefore, it becomes possible to force a voltage to the word line driving voltage generation circuits from the outside not only after the plurality of bare chips is mounted on the module substrate but also after the plurality of bare chips is integrally covered with mold resin by applying a desired voltage to the substrate pad VREFT. There is provided a semiconductor memory module capable of performing a test for a semiconductor chip after the semiconductor chip is mounted on a module substrate.

Abstract: Buffering data transfer between a chipset and memory modules is disclosed. The disclosure includes providing and configuring at least one buffer. The buffers are provided in an interface between a chipset and memory modules. The buffers allow the interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the at least one buffer. The second sub-interface is between the at least one buffer and the memory modules. The buffers are then configured to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.

Abstract: A memory card substrate includes a first solder pad assembly formed on a top edge of the memory card substrate. The first solder pad assembly has multiple first solder pads equally spaced from each other and multiple first gaps each sandwiched between two adjacent first solder pads. A second solder pad assembly is formed on a bottom edge of the memory card substrate and has multiple second solder pads equally spaced from each other and multiple second gaps each sandwiched between two adjacent second solder pads. Each first solder pad corresponds to one of the second gaps so that the first solder pads are alternately arranged on the top edge relative to the second solder pads on the bottom edge.

Abstract: A bare chip is provided with a pad for activation/deactivation control to which a deactivation control signal for converting a bare chip that has been detected as being defective into the deactivated condition is inputted. When a deactivation control signal is inputted to the pad for activation/deactivation control, internal circuit prevent a signal that has been inputted from the pad for data input/output control from being inputted to an internal circuit located further inside than the input buffer circuit. Thereby, the bare chip that has been detected as being defective can be converted to the deactivated condition. As a result, a semiconductor memory module can be obtained that can be repaired by newly mounting a good function chip without allowing the bare chip that has been detected as being defective to interfere with the functions of the semiconductor memory module.

Abstract: A method for directly writing data into an optic disk is performed by an optic disk drive incorporating a control unit to which an external data storage device, such as compact flash memory device, is connected. The method includes steps of (1) initiating a writing operation, (2) setting the optic disk drive to busy condition, (3) checking if an optic disk is properly loaded and if the external memory device is correctly connected, (4) issuing a warning, if they are not properly loaded or connected, (5) checking if the optic disk is a UDF disk, (6) issuing a warning, if it is not, (7) creating a folder in the optic disk, (8) retrieving data from the external data storage device and writing the data into the folder of the optic disk, and (9) ending the writing operation. No computer-based interface is required between the optic disk drive and the external data storage device in performing the data writing operation.

Abstract: A memory module MM, in which a module wiring substrate 5 is equipped with function switching means KK1 and KK2 for arbitrarily switching function switching signals to be inputted to function switching pins FP0 and FP1 of memories 1. By these function switching means KK1 and KK2, moreover, the function switching signals are arbitrarily switched from any of no connection, a supply voltage Vcc and a ground potential Vss. These signals are inputted altogether to all the mounted memories 1 to switch and arbitrarily set functions including reading modes and refresh cycles.

Abstract: The present invention includes a card memory device (20) comprising a microprocessor (2), a plurality of memory units (5-12) for storage of digital data, the memory units (5-12) being embedded in the card memory device (20). A selecting device (3, 4) is provided for selecting one of the memory units (5-12) and for routing address information and data to the selected memory unit (5-12), both the microprocessor (2) and the selecting device (3, 4) being embedded in the card memory device (20). The card memory device integrates components into a thin flexible memory card with surface contacts (1) so that the components can cooperate as a compact unit providing environmental sealing and secure access to several Mbytes of digital data. A specially designed set (1) of contacts (21-25) are also described which reduce the risk of electrostatic discharge. The card memory device (20) may be used for secure control of a personal computer.

Abstract: A memory module is capable of constituting short loop-through form memory bus systems in which the length of the entire channel can be reduced. As a result, the systems are suitable for a high-speed operation, and costs for fabricating systems such as a board and a module connector can be reduced. The memory module includes a plurality of tabs located in one side of the front and in one side on the rear of the memory module, for being interconnected by a connector on a system board, a plurality of vias for connecting two different signal layers of the memory module, and a plurality of data buses extended from the tabs on the front of the memory module to the tabs on the rear of the memory module through each of the vias. At least one memory device is connected to each of the data buses. Preferably, each of the data buses is formed to be perpendicular to one side of the memory module on which the tabs are formed.

Abstract: A smart card having improved non-volatile memory and a processor. The memory includes of a plurality of memory cells. The semiconductor memory cells each have a data storage element constructed around an ultra-thin dielectric, such as gate oxide. The gate oxide is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. The memory cell is read be sensing the current drawn by the cell. A suitable ultra-thin dielectric is high quality gate oxide of about 50 angstroms thickness or less, as commonly available from presently available advance CMOS logic process.

Abstract: Support circuitry for a three-dimensional memory array is formed in a substrate at least partially under the three-dimensional memory array and defines open area in the substrate under the three-dimensional memory array. In one preferred embodiment, one or more memory arrays are formed at least partially in the open area under the three-dimensional memory array, while in another preferred embodiment, logic circuitry implementing one or more functions is formed at least partially in the open area under the three-dimensional memory array. In yet another preferred embodiment, both one or more memory arrays and logic circuitry are formed at least partially in the open area under the three-dimensional memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: A memory module architecture that supports Flash and static memory devices in addition to dynamic memory devices. The module architecture of the present invention preferably redefines standard application of chip select signals on existing module architectures to provide requisite signaling to support Flash and static RAM devices. Use of serial presence detect signaling features of standard memory modules is also modified to provide desired identity and parameters of such an enhanced module. Extending the range of supported memory devices in an otherwise standard memory module reduces the need for special designs to accommodate different and evolving types of memory and is therefore particularly applicable to embedded systems where a variety of memory types are often utilized.

Abstract: The present invention utilizes a buffer to isolate a stack of memory devices, thereby taking advantage of the increased memory density available from stacked memory devices while reducing capacitive loading. A memory module in accordance with the present invention may include a stack of memory devices and a buffer coupled to the first and second memory devices and arranged to capacitively isolate the first and second memory devices from a bus. In a memory system in accordance with the present invention, multiple buffered stacks of memory devices are preferably coupled in a point-to-point arrangement, thereby further reducing capacitive loading.

Abstract: A memory module MM, in which a module wiring substrate 5 is equipped with function switching means KK1 and KK2 for arbitrarily switching function switching signals to be inputted to function switching pins FP0 and FP1 of memories 1. By these function switching means KK1 and KK2, moreover, the function switching signals are arbitrarily switched from any of no connection, a supply voltage Vcc and a ground potential Vss. These signals are inputted altogether to all the mounted memories 1 to switch and arbitrarily set functions including reading modes and refresh cycles.

Abstract: A memory device is constructed by connecting a plurality of flat high-speed memory modules each including a connector on one side of which input side and output side terminals for dealing with a high-speed signal of plural-bit width whose impedance is controlled and which is transmitted from a memory controller to a terminal resistor are arranged. The memory device in which memory modules can be cascade-connected and which can maintain the impedance of a memory bus signal in a constant value by use of an inexpensive multi-layered circuit board structure is provided. A socket mounting structure of the memory device and a mounting method of the memory device is provided.

Abstract: A semiconductor circuit having a power supply voltage detection circuit to detect a potential level of an external power supply voltage and to output a detection signal depending on a comparison result with the potential level. A system control circuit detects the detection signal, outputs a status signal and an interrupt signal, and outputs a clock selection signal in response to an operation control signal. A CPU outputs the operation control signal to the system control circuit in response to the status signal and the interrupt signal. A clock generation circuit generates a plurality of clock signals and a clock selection circuit selects one clock signal among the plurality of clock signals in response to the clock selection signal. The clock selection circuit then outputs the one clock signal as a system clock signal.

Abstract: A communications method is described in which two memory modules receive data and commands from a controller module via a common data and command bus. The memory modules contain active line terminations. By a second chip select input, one of the memory modules can monitor the write commands that pass from the controller module to the other memory module, and thus activate the line terminal in the monitoring memory module.

Abstract: A non-volatile semiconductor memory device is capable of having its individual banks controlled separately from the outside, and a semiconductor disk device is capable of proceeding immediately to the next writing to a bank of non-volatile semiconductor memory device which has become ready. Each bank has the independent write operation of data from its data register to memory cells, enabling the transfer of data from the outside to the data register of the bank even during the write operation of other bank from the data register to memory cells thereof.

Abstract: The preferred embodiments described herein provide a three-dimensional memory cache system. In one preferred embodiment, a modular memory device removably connectable to a host device is provided. The modular memory device comprises a substrate, a cache memory array, a three-dimensional primary memory array, and a modular housing. The cache memory array and the three-dimensional primary memory array can be on the same or separate substrates in the modular housing. In another preferred embodiment, an integrated circuit is provided comprising a substrate, a cache memory array in the substrate, and a three-dimensional primary memory array above the substrate. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

Abstract: A memory module socket having a transposed pinout allowing the socket to be mounted on the second, or reverse, surface of a motherboard and connected to circuit traces configured for mounting of a memory socket on the first, or processor, surface of the motherboard to correctly accommodate signals between the motherboard and the memory module is disclosed. A motherboard having at least one memory socket mounted on the second, opposing surface enhancing access to the memory socket or sockets for insertion and removal of memory modules for testing the memory modules in multimotherboard test systems is also described. The invention further includes a method of converting a conventional motherboard and memory socket assembly for such testing.

Abstract: A memory module socket having a transposed pinout allowing the socket to be mounted on the second, or reverse, surface of a motherboard and connected to circuit traces configured for mounting of a memory socket on the first, or processor, surface of the motherboard to correctly accommodate signals between the motherboard and the memory module is disclosed. A motherboard having at least one memory socket mounted on the second, opposing surface enhancing access to the memory socket or sockets for insertion and removal of memory modules for testing the memory modules in multimotherboard test systems is also described. The invention further includes a method of converting a conventional motherboard and memory socket assembly for such testing.

Abstract: A high-density folded bitline memory array architecture is disclosed. High memory cell packing density is achieved by dividing polysilicon wordlines into short individual segments in the folded bitline scheme. Each wordline segment forms the gate of one or two DRAM memory cell transistors, and each segment is connected to a metal wordline, or conductor having low resistivity. By eliminating spaces between the memory cells due to passing wordlines, a cell arrangement and density similar to open bitline schemes is achieved. Further packing is obtained by arranging two columns of memory cells parallel to each bitline, each column offset with the other by a predetermined pitch. Therefore, by increasing the number of memory cells connected to each complementary bitline pair, each bitline pair can be cut in half and connected to its own bitline sense amplifier to reduce the bitline capacitance.

Abstract: A substrate pad VREFT provided outside of the mold resin and word line driving voltage generation circuits within a plurality of bare chips are electrically connected only through electrical wires on a module substrate. Therefore, it becomes possible to force a voltage to the word line driving voltage generation circuits from the outside not only after the plurality of bare chips is mounted on the module substrate but also after the plurality of bare chips is integrally covered with mold resin by applying a desired voltage to the substrate pad VREFT. There is provided a semiconductor memory module capable of performing a test for a semiconductor chip after the semiconductor chip is mounted on a module substrate.

Abstract: A computer motherboard selectively uses various memories in the light of a dummy card. The computer motherboard comprises a serial resistor, and a first slot and a second slot for holding various memories, respectively. Various memories can be configured on the motherboard without additional settings by means of predefined dummy card or/and rearranging the location of the serial resistor.

Abstract: A memory module with any combination of driver line terminators, power supply circuits, and components integral to a memory control subsystem mounted directly on the memory module for use with high speed, impedance-controlled memory buses. The memory module may be formed on a conventional printed circuit card with unpacked or packed memory chips attached directly to the memory module. Including the additional functionality directly on the memory modules improves the EMC/EMI performance as well as signal quality and integrity, thereby enhancing the memory subsystem performance. Such designs may also eliminate the need for bus exit connections, thereby allowing the freed-up connection capacity to be used to address additional memory capacity on the module. Another embodiment features a module with the additional features but without memory devices.

Abstract: A high-performance memory module. The memory module is designed for a computer system with a wide data path. The memory module is implemented using a small printed circuit board (PCB), with a plurality of memory chips and a connector mounted upon the PCB. Signal traces for control, address, and data signals are arranged in such a manner as to minimize the length of each signal trace, thereby saving PCB area. On the connector, an electrical ground pin is located between each pair of signal pins, which may allow for a low-resistance return current path, and may therefore allow the module to operate at higher clock frequencies. Furthermore, locating a ground pin between each pair of signal pins may help reduce signal interference, or “crosstalk”, thereby improving signal integrity of the memory module.

Abstract: Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

Abstract: A memory system. The system includes at least two ferroelectric memory devices arranged sequentially. Each memory device has a data in signal and a data out signal, and the data out signal each memory device is transmitted as the data in signal of the next device in sequence. A system controller generates an initial data in signal for the first memory device. A data bus transfers data between each memory device and the system controller and an address bus provide addressing of the memory devices.

Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.

Abstract: The control logic for a hot-pluggable memory cartridge for use in a redundant memory system. To implement a hot-pluggable memory cartridge in a redundant memory system, control logic to control the sequence of events for powering-up and powering-down a memory cartridge is provided.

Abstract: A memory chip package with a controller die on a first side of a printed circuit board and a memory die on a second side of the same printed circuit board. The memory chip package is integrated into a microprocessor controlled device or alternatively is integrated into a portable memory card.

Abstract: A very small computer memory card is densely packed with a large number of flash EEPROM integrated circuit chips. A computer memory system provides for the ability to removably connect one or more of such cards with a common controller circuit that interfaces between the memory cards and a standard computer system bus. Alternately, each card can be provided with the necessary controller circuitry and thus is connectable directly to the computer system bus. An electronic system is described for a memory system and its controller within a single memory card. In a preferred physical arrangement, the cards utilize a main circuit board with a plurality of sub-boards attached thereto on both sides, each sub-board carrying several integrated circuit chips.

Abstract: A method including routing a signal from a memory device on an integrated circuit in a package to a memory module, and returning the signal to a reference line in the package between the memory module and the integrated circuit. Also, a method including providing a memory module including at least one memory package configured for electrically coupling to a bus on a system board, the at least one memory package comprising an integrated circuit including a plurality of memory devices, and a package substrate including a surface having a plurality of externally accessible contact points coupled to the memory devices and an externally accessible reference signal line and a surface of the package, and tuning the electrical characteristics of the memory package using an electrical potential between the contact points and the reference signal line.

Abstract: A semiconductor memory device with a high-capacity memory cell array includes a plurality of global word lines per memory cell row of the memory cell array. The global word lines are formed in two wiring layers (upper and lower layers). This substantially reduces the number of memory cells connected per global word line without increasing the memory cell size, allowing for an improved operation speed of the memory cells and reduced power consumption.

Abstract: A plurality of memory modules interface through a daisy-chain providing a point-to-point connection for each memory module. The first and the last memory module in the daisy chain each connect to a separate memory controller port forming a ring circuit. A distinct set of signals connect the memory modules in each direction. A junction circuit in each memory module provides line isolation, a coupling to the adjoining memory modules in the daisy chain, or in the case of the first and last memory module in the daisy chain, a memory module and a memory controller, and a data synchronization circuit. Each junction circuit provides as well as voltage conversion so that the memory devices on a memory module operate at a different voltage than the memory controller, and multiplexing/de-multiplexing so that a lesser number of lines interface with each junction circuit.

Abstract: In a semiconductor memory device composed of a semiconductor chip and overlaid to a surface of another semiconductor chip so as to connect together, a control circuit provided in the semiconductor memory device is provided with a chip connector portion having a plurality of pads. The chip connector portion is formed to have a configuration corresponding to the maximum capacity of the memory cell array provided in the semiconductor memory device, and the location and the number of the pads are invariably determined even when the memory cell array has a capacity less than the maximum capacity. The control circuit incorporating the chip connector portion is also invariably determined so as to control reading and writing data from and into the memory cell array having the maximum capacity, regardless of the capacity of the memory cell array provided.

Abstract: An information processing apparatus and method operate using a removable medium such as a removable disk on which all necessary software and content are recorded. The information processing apparatus includes a removable disk drive for recording and reproducing an information signal onto or from the removable disk, a main memory and a flash memory for storing information, and a central processing unit (CPU) for controlling the above-described parts such that when the removable disk is inserted into the removable disk drive, software is automatically loaded into the main memory and executed, necessary information is recorded on the removable disk, and, if the execution of the software is ended, the removable disk is ejected. An information processing apparatus based on this single medium activated platform (SMAP) architecture may serve as various devices depending on the application program or software that is stored on the removable disk.

Abstract: Memory systems and methods of making the same are described. In one aspect, a memory system may includes multiple memory layers that may be identical when manufactured and may be readily customized before or after the layers are arranged into a three-dimensional stack so that data may be sent to or retrieved from individual layers (either serially or in parallel) independently of the other layers.

Abstract: A portable storage device is detachably connectable to an information processing unit such that when a file management system is loaded into a main storage device of the portable storage device, a particular value is written to a register, a central processing unit (CPU) checks if the contents of the register coincides with the particular value, the CPU accesses a flash ROM (read only memory) if they are in coincidence, and the CPU re-loads the file management system if they are not in coincidence.

Abstract: A process for evaluating and correcting virtual integrated circuit designs includes a method and apparatus for determining a ratio of an amount of material, i.e. polysilicon or metal, in any given layer to an area of the layer. The ratio is then compared to a predetermined target ratio, which is based on a ratio of the total amount of the material to the entire area of the I-C design. The process then automatically inserts or deletes an amount of material from the layer as needed, using any of four methods. These methods include deletion, scaling, deletion and scaling or striping. The ratio for an erroneous layer is rechecked after the first correction is performed and the entire process is repeated using a Newton-Raphson or a Least Absolute Deviation Regression method until the ratio falls within the predetermined tolerances. If the layer has been filled, the layer is further checked for short circuits, fill isolation violations, antenna violations and the like which may have resulted from the material fill.

Abstract: A semiconductor memory architecture is provided where isolation between adjacent memory cell pairs is accomplished by using an isolation transistor incorporating a programmable gate voltage to minimize subthreshold leakage. A testkey is provided internal to the memory chip that can be enabled while the memory chip is in a test mode. The testkey is capable of testing the isolation transistors for excessive leakage. The testkey is coupled to a translator, responsible for converting control signals from the testkey to isolation gate voltages. The testkey is used to determine whether the isolation transistor is leaky. The translator may adjust the isolation gate voltage to turn the transistors off harder. The present invention may further include an antifuse to permanently change the isolation gate voltage to a suitable value when the semiconductor leaves the testing mode.

Abstract: A semiconductor configuration is described and has a temperature sensor, which measures a temperature of a semiconductor module. The measured temperature is provided to a control unit, so that the control unit can adapt a refresh cycle in the semiconductor module to the retention time corresponding to the measured temperature.

Abstract: A single event upset (SEU) resistant semiconductor circuit element and a method of making are provided by the invention. The single event upset resistant semiconductor circuit element includes a plurality of parallel-connected semiconductor cell elements. Each semiconductor cell element of the plurality of parallel-connected semiconductor cell elements is physically separated from the other cell elements. Moreover, the semiconductor cell elements may be physically separated by at least one intervening semiconductor cell element of another circuit element.

Abstract: A system and method for providing protection of content which may be transmitted over unsecure channels, including storage and transmission in bulk media, transmission over a network such as the Internet, transmission between components of an open system, and broadcast transmitted, to compliant storage devices and/or compliant use devices is disclosed. The technique for providing protection from unauthorized utilization of the content so stored is provided publicly in order to allow for those utilizing a conforming media device to master or generate content protected according to the present invention. According to a preferred embodiment, public key cryptography is utilized to identify compliant devices and to transmit cryptographic keys protecting content data. In the preferred embodiment content is protected using private key cryptography to optimize system performance.

Abstract: The present invention is a family of memory modules. In one embodiment a memory module with granularity, upgradability, and a capacity of two gigabytes uses 256 MB SDRAM or DDR SDRAM memory devices in CSPs in a volume of just 4.54 inches by 2.83 inches by 0.39 inch. Each module includes an impedance-controlled substrate having contact pads, memory devices, and other components, including optional driver line terminators, on its surfaces. The inclusion of spaced, multiple area array interconnections allows memory devices to be symmetrically mounted on each side of each of the area array interconnections, thereby reducing the interconnect lengths and facilitating the matching of interconnect lengths. Short area array interconnections, including BGA, PGA, and LGA options or interchangeable alternative connectors provide interconnections between the modules and the rest of the system. Thermal control structures may be included to maintain the memory devices within a reliable range of operating temperatures.

Abstract: A modular memory device includes a support element, a memory unit comprising a three-dimensional memory array carried by the support element, a device interface unit carried by the support element and coupled with the memory unit, and an electrical connector carried by the support element and coupled with the device interface unit. The memory array is well suited for use as a digital medium storage device for digital media such as digital text, digital music, digital image or images, and digital video. The device interface unit is not required in all cases.

Abstract: A memory housing is provided comprising at least one memory device positioned within the housing, the at least one memory device having a performance parameter responsive to an environmental condition, and an environmental maintaining device for non-ambiently changing an environmental condition within the memory housing to cause the performance parameter of the at least one memory device to meet a criteria.

Abstract: A memory module has memory chips in stacks. The lower memory chip in a stack has pins that are soldered to pads on the module substrate. A hollowed printed-circuit board (PCB) has a hollow opening on the bottom with about the same width, length, and depth as the top cap of the lower memory chip. The hollowed PCB fits over the top cap of the lower memory chip and has lower pads on its lower surface but outside of the hollow opening. The lower pads are soldered to the top shoulders of the pins of the lower memory chip. An upper memory chip has pins that are soldered to pads on the upper surface of the hollowed PCB. The hollowed PCB has a metal trace that re-routes a second bank-select signal from a no-connect pin of the lower memory chip to a bank-select pin of the upper memory chip.

Abstract: A memory module has one or more memory devices, a clock generator providing clocking signals, and a clocking topology providing the clocking signals to the memory devices(s).

Abstract: The present invention provides a nonvolatile memory system whose storage capacity can be easily changed. The nonvolatile memory system comprises plural memory modules, a controller for controlling the operation of the plural memory modules according to access requests from the outside, and a module selecting decoder for selectively enabling the memory modules by decoding a selection signal outputted from the controller, wherein the memory modules are freely mounted or dismounted. With this arrangement, the storage capacity can be changed by increasing or decreasing the memory modules.