Abstract: A time interval analyzer for measuring time intervals between events in an input signal includes a trigger circuit that receives the input signal and that outputs a time trigger signal at a first triggering level upon occurrence of a first input signal event. A time counter receives a time base signal and increments a time count at each period of the time base signal. The time count is calibrated to a predetermined reference time. A processor circuit is in communication with the trigger circuit and the time counter so;that the processor circuit receives the time trigger signal and reads the time count from the time counter. The processor circuit is configured to read the time count upon receiving the time trigger signal at the first triggering level so that the time count read by the processor circuit indicates the time at which the first input signal event occurred with respect to the predetermined reference time.

Abstract: A stopwatch has a measuring section for measuring a primary physical quantity, a memory section for previously storing as a target value the value of the primary physical quantity at a point where a time is to be recorded, and recording sections for recording a measured value of time at a time point when the value measured by the measuring section becomes equal to the target value, after initiation of measurement of time. The target value is, for example, a value actually recorded before initiation of measurement of time by the measuring section at the point where time is to be recorded.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC A designers to minimize the guard band and consequently guarantee higher speed performance.

Abstract: An electronic chronograph watch (1) with an analogue display wherein the measured times are displayed on small dials (5, 6, 7) located on the periphery of the main dial (2). The measured times are displayed by small hands (8, 9, 10) each driven by a motor. The watch (1) includes a stem-crown (11) used to adjust the position of the hands (3, 4) indicating the current time via conventional mechanical means. The watch further includes at least two push-buttons (12, 13) which, when manipulated, allow access to all the functions of the chronograph part, including the function of adjusting the rest position of the chronograph hands (8, 9, 10).

Abstract: A method and apparatus is described for computing a duration of a reduced power consumption state. A time of exiting from the reduced power consumption state is read prior to an execution of an interrupt routine. The read time of exiting is then stored in a register and a calculation of a reduced power consumption state duration may be performed.

Abstract: The invention concerns electronic chronograph watches which include a central hour hand (3), a central minute hand (4) and a small off-central second hand (6) for permanently indicating the current time, chronograph hands (7, 8, 9) for indicating a measured time when the watch is operating in chronograph mode, drive units for driving said hands and generator means responding to manual control means (P1, P2, 10) to apply control pulses to said drive units. According to the invention, the watch also includes a central second hand (5) driven by its own drive unit and the generator means include means for selectively applying the control pulses to this drive unit, so that the central second hand indicates the seconds of the current time, in phase with the small off-center second hand (6), when the watch is operating normally and the measured seconds when the watch is operating in chronograph mode.

Abstract: A timepiece has an ordinary time measuring section including an ordinary time display unit for measuring an ordinary time and time information (i.e., chronograph) measuring sections including chronograph displays for measuring time information other than the ordinary time (i.e., chronograph information). The timepiece is configured such that the ordinary time display unit and the chronograph display units, are disposed on a display surface of the timepiece without overlapping each other.

Abstract: A clock stores time data indicative of time of operation of a power machine. A timing circuit provides a timing signal and a controller is coupled to a timing circuit and to a memory, which includes a plurality of memory locations. An elapsed time value is maintained, based on the timing signal, by the timing circuit, and a subset of a plurality of memory locations is intermittently updated with the elapsed time value.

Abstract: A pre-conditioner for enabling high-speed time interval measurements in an ATE system having a relatively low-bandwidth pathway between a UUT and a timer/counter includes a frequency divider and a D flip-flop located near the UUT. The frequency divider receives a first input signal from the UUT and produces a first output signal having a frequency equal to 1/N times the frequency of the first input signal. The first output signal connects over the low-bandwidth pathway to a first channel of the timer/counter. The first output signal also connects to the D input of the D flip-flop. The pre-conditioner receives a second input signal from the UUT that drives the CLOCK input of the D flip-flop. The Q output of the D flip-flop supplies a second output of the pre-conditioner. The second output connects over the low-bandwidth pathway to a second channel of the timer/counter.

Abstract: A timing circuit for measuring time of arrival of an asynchronous event is disclosed. The timing circuit includes a counter, a register, a gray code-to-binary converter, and a cascade circuit. In response to a time of arrival of a trigger signal that denotes an occurrence of an asynchronous event, the counter generates a set of high-order binary bits and the register generates a set of gray code bits. The gray code-to-binary converter then converts the set of gray code bits to a set of low-order binary bits. Finally, the cascade circuit concatenates the high-order binary bits and the low-order binary bits to form the time of arrival of the asynchronous event.

Abstract: A key mode timer with a displaying window and an improved plate structure. The plate structure includes the setting keys, an upper plate and an inner plate. The upper plate has a displaying window. The upper plate is rotated with the setting keys to set the time and the inner plate is fixed. When the displaying window rotates with the upper plate, the numbers and the letters printed on inner plate are shown through the window to enable the user to easily read the time information shown on the timer.

Abstract: A time measurement device includes a first motor (1300) for indicating standard time, a second motor (1400) for indicating a chronograph, a generator (1600) which generates driving power for driving the first and second motors by converting mechanical energy into electrical energy, and a zero reset mechanism (1200) for mechanically resetting the chronograph to zero. A compact time measurement device, operable from a low power, is thus provided.

Abstract: The timer (100) is suitable for indicating the progress of an activity, such as a movie or a download, in an intuitive fashion. Time bars (103, 104) are provided for indicating the total time of the activity in hours and minutes in hour and minute hands (101, 102) indicate the current time either relative to the start time or absolute. In case the total time exceeds sixty minutes, the minute time bar (104) can be filled completely up to the last hour, after which it is filled with the remaining time in minutes. The system, which may be a television set or a computer, uses the timer (100) to indicate the duration of programs.

Abstract: Each flip-flop-to-flip-flop path delay and a target machine cycle obtained in the stages of physical design and packaging design are used as input, and with respect to a path in which the path delay is not less than the target machine cycle, a closed loop including the path is extracted, and the timing of a clock signal of each flip-flop is adjusted so as to permit data transmission along the closed loop in a required cycle-number. At this time, a path along which data transmission is impossible in the target machine cycle or a closed loop including the path is listed in order to be modified. As methods of supplying a clock signal to each flip-flop, a plurality of methods different in the adjustable range of clock timing are combined and used.

Abstract: A semiconductor circuit is provided including circuitry for producing a pulse. A plurality, n, of delay elements are provided each enabled and disabled in parallel by the pulse. Each delay element is adapted to transmit the pulse from an input to an output, with the pulse reaching the respective outputs at different times. A plurality, n−1, of detectors is provided each having an input coupled to an input of a corresponding delay element. Each detector is adapted to set a state of its output to a predetermined state, from a plurality of states, in response to receiving a portion of the pulse. The outputs of the detectors are coupled to output pins of the semiconductor circuit. A tester is provided that is adapted to couple to the semiconductor output pins and detect the state of the detector outputs.

Abstract: There is disclosed an electronic chronograph watch (1) with an analogue display wherein the measured times are displayed on small dials (5, 6, 7) located on the periphery of the main dial (2). The measured times are displayed by small hands (8, 9, 10) each driven by a motor. The watch (1) includes a stem-crown (11) used to adjust the position of the hands (3, 4) indicating the current time via conventional mechanical means. The watch further includes at least two push-buttons (12, 13) which, when manipulated, allow access to all the functions of the chronograph part, including the function of adjusting the rest position of the chronograph hands (8, 9, 10).

Abstract: A method to aid the treatment of sleeping disorders that are aggravated by an insomniac's underestimation of total sleep time and sleep efficiency, and overestimation of time necessary to fall asleep. The method includes an observation of the beginning of rest time and self-actuated measurement of the time necessary to fall asleep. The insomniac is made aware of the elapsed wake time and total sleep time upon wakening by further observing the time of awaking and the elapsed wake time as recorded on a wrist watch or other device. The apparatus can include a wrist mounted timer with a hand mounted actuator that stops timing when the insomniac falls asleep and disengages contact with the actuator.

Abstract: A timing device for tracking the length of time a user is absent from a particular location comprises a base member that includes a housing, a timer mounted to the housing, a display connected to the timer, and a timing-key receiver attached to the housing and in communication with the timer and utilized in starting and stopping the timer. Provided is a visually prominent timing-key releasably mountable to the timing-key receiver that comprises a key body and a coupler attached to the key body which releasably mates with the timing-key receiver. The device is commonly employed in tracking how long a student is temporarily absent from a classroom.

Abstract: A light clock measures time by having a light pulse source initiating a light pulse which travels a preset distance in an open or closed loop. A counter is increases incrementally upon detection of the light pulse by a light pulse detector. Each increment is a time interval, which is determined by the preset distance divided by the speed of the light pulse. If the loop is an open loop, another light pulse may be initiated upon detection of the previous light pulse. If the loop is a closed loop, no further light pulse initiation beyond the initial light pulse is required, but, when necessary, a light pulse amplifier is used to amplify the light pulse for the next cycle around the closed loop in the light pulse transmission device.

Abstract: A timing device for keeping time by marking the time boundaries between contiguous time periods. Time is measured by measuring charging voltage on a pair of capacitances where each capacitance is charged and discharge in successive cycles. Detection of a preset value of potential on each one of the capacitances is used to initiate commencement of charge on the other capacitance and detection of another preset value on the other capacitor is used to record measurement of potential at a full scale potential point on the one capacitor. By this means “dynamic” measurements of potential are made by which is meant that the potentials are measured while the potential is changing, rather than when the potential has reached a target end point. This technique eliminates errors arising from unstable conditions at the capacitor due to, for example, dielectric hysteresis, a requirement to measure a charging or discharging step simultaneous with a measuring step, etc.

Abstract: Dummy cell test circuit for measuring delay times in embedded, said embedded circuits being connected to access circuits equipped with input access pads and output access pads, between which is comprised an electrical main path, said test circuit comprising a test input pad and a test output pad, between which is comprised an electrical dummy test path. According to the present invention the test input pad correspond to the access input pad (IN1′ IN1″) of the embedded circuit (2).

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the period of the oscillator. The period of the oscillator is then related to the average signal propagation delay through the test circuit. The invention can be applied to synchronous components that might fail to oscillate by connecting the asynchronous set or clear terminal to the output terminal so that the oscillator oscillates at a frequency determined by the clock-to-out delay of those components.

Abstract: A clock stores time data indicative of time of operation of a power machine. A timing circuit provides a timing signal and a controller is coupled to a timing circuit and to a memory, which includes a plurality of memory locations. An elapsed time value is maintained, based on the timing signal, by the timing circuit, and a subset of a plurality of memory locations is intermittently updated with the elapsed time value.

Abstract: A timing device for keeping time by marking the time boundaries between contiguous time periods. Time is measured by measuring charging voltage on a pair of capacitances where each capacitance is charged and discharge in successive cycles. Detection of a preset value of potential on each one of the capacitances is used to initiate commencement of charge on the other capacitance and detection of another preset value on the other capacitor is used to record measurement of potential at a full scale potentail point on the one capacitor. By this means “dynamic” measurements of potential are made by which is meant that the potentials are measured while the potential is changing and rather than when the potential has reached a target end point. This technique eliminates errors arising from unstable conditions at the capacitor due to, for example, dielectric hysteresis, a requirement to measure a charging or discharging step simultaneous with a measuring step, etc.

Abstract: An on-chip I/O timings measurement circuit that improves measurement accuracy compared to conventional external test methods. This circuit guarantees AC timing specifications that are too small for the measurement capabilities of today's high-frequency memory testers. This system in incorporated into the SRAM via the JTAG interface and a JTAG private instruction. A private instruction refers to an unused instruction from the industry-standard public instruction set. Private instructions are usually reserved for the manufacturer, but may be provided to the user as an enhancement to the standard JTAG instruction set.

Abstract: A semiconductor circuit is provided including circuitry for producing a pulse. A plurality, n, of delay elements are provided each enabled and disabled in parallel by the pulse. Each delay element is adapted to transmit the pulse from an input to an output, with the pulse reaching the respective outputs at different times. A plurality, n−1, of detectors is provided each having an input coupled to an input of a corresponding delay element. Each detector is adapted to set a state of its output to a predetermined state, from a plurality of states, in response to receiving a portion of the pulse. The outputs of the detectors are coupled to output pins of the semiconductor circuit. A tester is provided that is adapted to couple to the semiconductor output pins and detect the state of the detector outputs.

Abstract: A device for monitoring the travel time of mail shipments and including a motion sensor, a memory for compiling the measured motion values, an electronic evaluation unit and a current supply. The motion sensor, the memory for the measured values, the electronic evaluation unit and the current supply are arranged on a partially flexible support or circuit board that is configured such that it includes rigid circuit board portions for the arrangement of the motion sensor, the memory for the measured values and the electronic evaluation unit as well as the current supply and these rigid circuit board portions are connected with one another by flexible circuit board portions or components.

Abstract: A stopwatch has a measuring section for measuring a primary physical quantity, a memory section for previously storing as a target value the value of the primary physical quantity at a point where a time is to be recorded, and recording sections for recording a measured value of time at a time point when the value measured by the measuring section becomes equal to the target value, after initiation of measurement of time. The target value is, for example, a value actually recorded before initiation of measurement of time by the measuring section at the point where time is to be recorded.

Abstract: An apparatus for measuring a time interval between a start signal edge and a stop signal edge provides a stable clock signal as input to a delay line formed by a series of similar logic gates. The output signal of the last gate of the series is phase locked to the clock signal by adjusting a bias signal controlling the switching speed of all gates. The clock signal and the output signal of each gate form a set of phase distributed periodic timing signals applied to a start time measurement unit (TMU) and a similar stop TMU. The start TMU counts edges of one of the timing signals occurring between an edge of an arming signal and the start signal edge and generates output data representing a time delay between the arming signal and the start signal edge. The data represents the start delay as a whole and fractional number of clock signal periods by conveying the counter output and by indicating which of the timing signals had an edge most closely following the start signal edge.

Abstract: A system and method for measuring hysteresis effects of a wafer process. The method comprises steps of generating a pulse having a pulse width equal to the delay of a transition through a delay chain wherein the delay chain has been in a static condition for a substantial length of time; counting a number of oscillations from a ring oscillator generated during the pulse width wherein the ring oscillator has been operating in a steady state condition; comparing the number of oscillations with an expected value; and correlating a difference resulting from the comparing step with a level of hysteresis effected by the wafer process.

Abstract: An athletic training device including a housing. Also included is light or speaker mounted on the housing for providing an indication upon the actuation thereof. At least one impact sensor is mounted on the housing for actuating the indication means upon being struck by a user.

Abstract: A timing signal generating apparatus capable of automatically detecting any erroneous set state that a pulse duration of a test pattern signal and a time duration between adjacent two pulses of the test pattern signal have been set in a program with the durations being shorter than corresponding limit values respectively, and a method of detecting any set error to the program for a timing signal. At the outside of a clock generator 113A for generating a set pulse PS and a reset pulse PR are provided a fourth latch circuit 16 for latching therein an integer delay signal MT outputted from a down-counter 11 of an integer delay giving device 10, and a fifth latch circuit 17 for latching therein an odd value MDAT outputted from a first latch circuit 12 of the integer delay giving device 10, thereby to detect a time duration from the set pulse until the reset pulse or a time duration from the reset pulse until the set pulse.

Abstract: A time interval analyzer includes a signal channel that receives an input signal. A plurality of measurement circuits are defined within the signal channel in parallel with each other. Each measurement circuit is configured to receive the input signal, measure an occurrence of a first event of the input signal with respect to a predetermined time reference and to output a time signal corresponding to the measurement of the occurrence. A processor circuit is in communication with the signal channel. It is configured to receive and compare time signals from the measurement circuits to each other to determine a time interval between the first event measured by a first measurement circuit and an event measured by a second measurement circuit.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with an inverting feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. One embodiment of the invention includes a phase discriminator that samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.

Abstract: The invention relates to a device for measuring the rise time of the electronic component of a signal disturbed by electronic noise and whose signal-to-noise ratio is mediocre. It incorporates a differentiating circuit (C12, C11) having at least one resistor (r) and one capacitor (c) implementing a high pass filter for filtering the low frequency background noise of the signal from the detector and a discriminating circuit (C21, C22) incorporating a comparator (k) for performing a comparison with the filtered signal from the differentiating circuit and an offset voltage selected as a function of the noise level interfering with the signal from the detector.

Abstract: A test signal retiming circuit that captures an input signal to produce a first output signal and generates a second output signal in response to the first output signal and a predetermined reference signal. The second output signal is resistant to an input signal timing variation. A verification is performed to insure the second output signal conforms to timing of a predetermined output signal. The input signal produces the first output signal by acquiring the input signal in a first buffer in response to a first signal and transferring the acquired input signal from the first buffer to a second buffer in response to the first signal. The first output signal is transferred from the second buffer to a third buffer in response to a second signal to produce a second output signal. The second output signal is resistant to a plurality of clock and data skews.

Abstract: An IC testing apparatus which is able to measure the execution time of an automatic function for each DUT by a one-time test, and to grade said automatic function automatically based on the above measured execution time. A IC testing apparatus comprises a evaluation circuit of the automatic function with minimum execution time, a timer which is activated by the above evaluation circuit, and a timer counter which is activated by the above timer and stopped by the evaluation of each DUT, and automatically measures the execution time of automatic function of each DUT.

Abstract: A microelectronic device such as a Field-Programmable Gate Array (FPGA) includes a large number of elements which can be individually configured or programmed to provide a desired logical functionality. Input and output pins enable external connection of the elements. Each element is configurable to produce an output in response to a first pulse which is applied more than a minimum length of time after a second pulse. The first pulse can be a clock pulse, and the second pulse can be a data pulse, in which case the minimum length of time is the setup time for the element. Each element of a device is tested by repeatedly applying first and second pulses to the device with a delay of the second pulse relative to the first pulse being progressively changed from a first value until a second value corresponding to the minimum length of time is reached as indicated by a transition between the output being produced and the output not being produced.

Abstract: A method for re-programming a memory device in a micro-controller system is provided. The method includes the steps of installing a software RTC service routine running outside the flash memory device, wherein a counter measures the total re-programming procedure duration (100). The software RTC service routine running outside the flash memory device is stopped (102) and the current absolute unit time saved in a read/write accessible memory cell (104). A re-programming cycle is executed (106) and the former running application will be prepared to continue (108). The unit is set to the previous stored value (110) and the software RTC service routine running outside the flash memory device re-started (112). The software RTC service routine running outside the flash memory device is stopped (114) and the measured total re-programming duration added to the current RTC value (116). The application then recommences (118).

Abstract: A device for the determination of the elapsed time since the initial activation of a unit of equipment. The device consists of a first and second circuit and a switch-on element. The first circuit establishes a connection between the item of equipment and the switch-on element. The second circuit consists of at least a time-counter and a source of energy to power the time-counter. Both circuits can be activated simultaneously by the switch-on element. The first circuit can be used both as the current flow for the item of equipment and also for detecting voltage or physical energy in a component of an item of equipment. The switch-on element can be activated both mechanically and electronically. The counter-information can be presented in a display unit in both a deletable or non-deletable manner. The time-counter and the display unit are powered by their own energy source.

Abstract: To measure relatively long time intervals with very high resolution, apparatus and method operate to receive a first pulse and a clock signal that has a known period, synchronize the first pulse with the clock signal, stretch the first synchronized pulse in accordance with a first stretch ratio, produce a first compared output pulse corresponding to the first stretched signal, synchronize the first compared output pulse with the clock signal, generate a first pulse sequence from the first synchronized pulse and the first synchronized compared output pulse, convert times of occurrences of the edges of the first pulse sequence to respective time values, receive a second pulse and generate a second pulse sequence in a manner similar to that of the first pulse sequence, convert times of occurrences of the edges of the second pulse sequence to respective time values, count the elapsed number of clock periods between the first and second synchronized pulses, derive the time interval between the received pulses from

Abstract: A delay test system includes an electronic circuit, such as a normal circuit which has a portion to be tested and a plurality of flip-flop circuits. In this event, each of flip-flop circuits is serially connected to each other to perform a delay test for said normal circuit. Further, a first clock input terminal is connected to the flip-flips and a normal circuit to input a normal mode clock signal. Moreover, a second clock input terminal is connected to the flip-flop circuits and the normal circuit to input a test clock signal. With such a structure, an input and output operation of data signals is carried out in synchronism with edge timings determined by both the normal mode clock signal in the normal mode on the condition that the test clock signal is not supplied to the second clock input terminal. On the other hand, the first and second clock input terminals are separately driven by the normal mode clock signal and the teat clock signal in the test mode.

Abstract: An integrated circuit tester produces an output TEST signal following a pulse of a reference CLOCK signal with a delay that is a sum of an inherent drive delay and an adjustable drive delay. The tester also samples an input RESPONSE signal following a pulse of the reference CLOCK signal with a delay that is a sum of an inherent compare delay and an adjustable compare delay. The inherent drive and compare signal path delays within an integrated circuit tester are measured by first connecting a salphasic plane to transmission lines that normally convey signals between the tester and terminals of an integrated circuit device under test. A standing wave signal appearing on that salphasic plane is phase locked to the CLOCK signal so that a zero crossing of the standing wave occurs at a fixed interval after each pulse of the CLOCK signal.

Abstract: A method for displaying the used time of a video processing apparatus. If the power of the video processing apparatus is turned on, the total used time of the video processing apparatus is read from a memory and the presently elapsing time is counted accumulatively to the read total used time. Then, the total used time accumulatively counted up to the present is displayed for a predetermined time period. When the predetermined time period has elapsed, the total used time display operation is stopped and it is checked whether a used time display function is turned on by the user. If the used time display function is turned on by the user, the total used time accumulatively counted up to the present time is displayed and it is checked whether the used time display function is turned off by the user. If the used time display function is turned off by the user, the total used time display operation is stopped and it is checked whether the power of the video processing apparatus is turned off.

Abstract: A time measurement circuit (100) measures a time interval between two events. The time measurement circuit (100) includes two digital phase counters (10' and 10"), a period counter (210), and a digital calculator (310). The first digital phase counter (10') converts a time interval from a leading edge of a start signal to a leading edge of clock signal following the start signal into a first binary number. The second digital phase counter (10") converts a time interval from a leading edge of a stop signal to a leading edge of clock signal following the stop signal into a second binary number. The period counter (210) converts a time interval between the two leading edges of the clock signal into a third binary number. The digital calculator (310) combines the three binary numbers to generate a number representing the time interval between the start signal and the stop signal.

Abstract: A time interval analyzer for measuring time intervals between events in an input signal includes a trigger circuit that receives an input signal and that outputs a trigger signal at a triggering level upon occurrence of the event. A first current circuit has a constant current source or a constant current sink. A second current circuit has (1) a current sink where the first current circuit has a constant current source or (2) a current source where the first current circuit has a constant current sink. A capacitor and a shunt are operatively disposed in parallel with respect to the first current circuit. The shunt is disposed between the first current circuit and the second current circuit.

Abstract: An athletic training device includes a main control unit coupled to one or more finish line units via a communication link. The main control unit arranged to provide a pre-race start signal and a race start signal simulating an actual race event starting condition. The main control unit further arranged to time the race events, to determine reaction times and to measure weather and/or atmospheric conditions and to store all these as training statistics.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. A phase discriminator samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.

Abstract: An automatic, accurate and inexpensive timing bench, able to be purchased and used by any amateur. The bench consists of a conventional chronograph wristwatch (2) and a control box (1) provided with a housing (12) for the chronograph and a transparent cover (17). The box (1) further includes input ports, for receiving electric signals originating from timing cells, and electromagnets (51, 52) for automatically pressing the push buttons (8, 9) of the chronograph as a function of said input signals. As a result of auxiliary electric ports on each box, several of these boxes can be coupled in cascade to form a more complex timing bench.

Abstract: A multifunction electronic analog timepiece includes a face and a plurality of indicators positioned on the face for displaying at least two time keeping functions. At least two step motors are provided for driving the plurality of time keeping function indicators. The time keeping function indicators are arbitrarily disposed about the face dependent upon the number of step motors and position of step motors required to drive the indicators. A microcomputer is provided and includes a program memory for storing software instructions for controlling the step motors.