Abstract: An ATM switching system has a subscriber input module, a trunk input module, an ATM switch, a subscriber output module, and a trunk output module. The subscriber input module includes: a 2B+D frame handler for splitting 2B+D channel data output from an N-ISDN subscriber into B-channel data and D-channel data, and multiplexing the split B- and D-channel data to corresponding highways; a first time switch module for sorting the channel data on the respective highways by time slots corresponding to destination time switch module numbers, and switching channel stream data grouped by destinations to the respective highways; and a first input CLAD for collecting voice data output from the time switch module by destinations to assemble an ATM cell.

Abstract: The present invention comprises a smart subscriber line interface card (SLIC). The SLIC of the present invention includes a first and a second switch. A data receiver is coupled to a first output of the first switch to receive a user output signal and is adapted to generate a data receiver output therefrom. An ADC (analog to digital converter) is coupled to a second output of the first switch to receive the user output signal and is adapted to generate an ADC output therefrom. A data transmitter is coupled to a first input of the second switch and is adapted to generate a data transmitter output from a received digital network signal and couple the data transmitter output to the first input of the second switch. A DAC (digital to analog converter) is coupled to a second input of the second switch and is adapted to generate a DAC output from the received digital network signal and couple the DAC output to the second input of the second switch.

Abstract: An arrangement and a method provide access between a number of user stations connected by radio via a number of radio base stations and a switching arrangement of a telecommunication network. At least one access network is provided, and it connects to the switching arrangement over at least one interface. A radio access network including a number of base stations is provided which also includes the access network. An address field of an addressing mechanism of the interface between the access network and the switching arrangement is so structured that it includes a first part for addressing base stations and a second part for addressing/identifying selected bearer channels on the existing interface.

Abstract: An extract-and-insert optical wavelength division multiplexer includes a broadcaster (D1) for applying an incoming multiplex signal to N outputs, a combiner-diffuser (D2) for broadcasting the multiplex to be inserted (MI) on N outputs, a first set of N tunable filters (FIT, . . . , FNT) for selecting the carriers of the signals which are to be used for modulating the carriers of the outgoing multiplex (MS), a second set of N tunable filters (F1E, . . . , FNE) for selecting the carriers which are to constitute the extracted multiplex (MT), N wavelength converter devices (CL1, . . . , CLN) suitable for supplying N carriers of the outgoing multiplex (MS), and N two-input, two-output optical switches (SW1, . . .

Abstract: A digital communication trunk employing digital discrete multitone communication over twisted pair copper network segments to increase the effective bandwidth therethrough. Each central office includes an end unit to connect to the network segments and digital discrete multitone repeaters are employed throughout the trunk at defined distances to maintain signal quality. A multiplexer can be employed at the central offices to combine multiple baseband signals before transmission and to extract those multiple signals after reception. In one embodiment of the present invention, four T1 rate baseband signals are combined by the multiplexer into a single signal which is transmitted at T2 rates through the trunk.

Abstract: An IP communication interface device includes first and second connecting units (51, 52), a first processing unit ( 931, 932, 933) for coding first media-corresponding data as B-channel data inputted to the first connecting unit from the switched circuit network, decoding packet-deassembled media-corresponding data into which a packet of second media-corresponding data inputted to the second connecting unit from the LAN is deassembled, and for transmitting the decoded media-corresponding data to the first connecting unit for forwarding the same data as the first media-corresponding data to the switched circuit network, a second processing unit (941, 942, 943) for assembling the coded media-corresponding data coded by the first processing unit into a packet, deassembling the packet of the second media-corresponding data, and transmitting the same data as packet-deassembled media-corresponding data to the first processing unit, and a third processing unit (53) for generating the second media-corresponding data

Abstract: A switch including a plurality of input/output (I/O) ports and a switching element programmably coupling a first of the I/O ports with a second of the I/O ports. An analysis device is associated with the first I/O port measuring at least one data traffic parameter specific to data traffic between the first I/O port and the second I/O port.

Abstract: A transport interface (10) provides add drop multiplex functionality and termination requirements for the transportation of network traffic. The transport interface (10) includes high speed units (12), broadband interfaces (16), and SONET formatters (18). Each high speed unit (12), broadband interface (16), and SONET formatter has redundant protection pairs (A and B). The high speed units (12), broadband interfaces (16), and SONET formatters (18) communicate with each other by in-band datalinks (40). The redundant protection pairs (A and B) communicate with one another by protection pair datalinks (42). The in-band datalinks (40) and the protection pair datalinks (42) provide protection switching within the transport interface (10) in the event of component failure. The in-band datalinks (40) are generated out of available or consumed bytes within either a section overhead (32) or a line overhead (34) of SONET OC-N frame (30).

Abstract: Improved telecommunication apparatus is realized with a structure that is tailored to provide an ID signal to the telecommunication network, which signal uniquely identifies the apparatus. The ID signal can be communicated to the network under control of the apparatus, or polled by the network. The apparatus includes a second port through which communication services are provided to a customer, and the ID signal can be sent to that second port as well. The apparatus further includes circuitry for processing signals flowing between the two ports, allowing the characteristics of the signal to change and thereby provide for format conversions, encryption, and other capabilities.

Abstract: Given a transmission of digitized voice information (spi) compressed in originating communication systems (KS (S)) via a plurality of communication systems (KS) of a communication network (KN), the compressed voice information (spi′) is matched to the switching bit rate of the transit communication systems (KS (T)) in the systems and are switched compressed. By avoiding the decompression and repeated compression of compressed voice information (spi′), delay times and distortions of the voice information (spi) are reduced.

Abstract: One aspect of the invention is a multichannel facility datalink processor. The processor comprises input circuitry operable to receive a first plurality of facility datalink signals. In addition, the multichannel facility datalink processor comprises output circuitry operable to transmit a second plurality of facility datalink signals. A state machine operable to be loaded with a predetermined state also forms a portion of the processor and is further operable to process ones of the first plurality of facility datalink signals and ones of the second plurality of facility datalink signals. The processor further comprises storage circuitry coupled to the state machine which is operable to store state information and facility datalink data for each of the first plurality of facility datalink signals and each of the second plurality of facility datalink signals.

Abstract: The router disclosed herein employs a plurality of forwarding processors and a matrix switch for selectively connecting input ports, output ports and the forwarding processors. Each of the input ports includes means for selecting a respective forwarding processor for each incoming data packet in accordance with data in the respective packet header and for transmitting the packet header to the selected forwarding processor. The selected forwarding processor operates to transmit to the originating input port the identity of an output port appropriate for the packet's next hop.

Abstract: Management data is selectively supplied to a management agent by a network switch using either a media access control (MAC) layer interface or PCI bus interface to provide maximum flexibility for the management agent. The management data includes management packets having at least a portion of a received data packet, and management information specifying receive status and network switch response characteristics to the corresponding received data packet. The network switch includes a plurality of network ports, including network traffic ports and one management queue for selectively supplying the management data to either the PCI interface or the management MAC interface. The selective output of the management frame via the alternate output paths enables the disclosed network switch to be implemented in existing switch fabric that uses a predetermined management protocol. The paths may also be segregated to optimize bandwidth for high priority data and low priority data, respectively.

Abstract: An UTOPIA level 2 interface over a backplane for connecting up to 31 Physical layer devices to one ATM layer device in a logically partitioned manner utilizing full bandwidth. The communications data is received on a first terminal at a first transfer rate. The communications data transfer rate is reduced from the first transfer rate to a second transfer rate. At the second transfer rate, the communications data is transferred over a backplane to a second terminal. On the second terminal, communications data transfer rate is increased from the second transfer rate to the first transfer rate. The first transfer rate is greater than the second transfer rate.

Abstract: A line interface unit terminates individual subscriber lines and supports conventional telephone service and high speed data service. It provides an interface between subscriber customer premises equipment and central office equipment. The use of large diplex filters is not required in order to terminate subscriber lines at the central office while providing high speed data services.

Abstract: A system for managing access by a plurality of terminal devices to an access line of a public switched telephone network (PSTN). The system comprises a SAU (service access unit) connected to the access line, and a FSP (full service provider) which is interconnectable through a call connection within the telephone network to the SAU. The SAU includes a plurality of interfaces each adapted to communicate with a respective terminal device connected thereto. This combination of the SAU and the FSP interconnected through the PSTN enables each of the terminal devices to access or be accessed from multiple service networks. The management system effectively provides multiple independent telephony "service" over the single access line by sharing the available bandwidth of the PSTN connection between the SAU and the FSP amongst the various terminal devices as required.

Abstract: A line interface selection circuit comprises a bus switch operable to receive signals from a plurality of line interface units and to facilitate a connection between at least one of the plurality of line interface units and a telecommunication network. The bus switch is coupled to a line interface transformer having a primary side and a secondary side.

Abstract: Method for improved configuration of a link between an end station and an intermediate device in a network. The intermediate device communicates through the link using a point-to-point protocol, and a lower layer protocol and is capable of translating between the lower layer protocol used by the link and a lower layer protocol used by a portion of the network. The intermediate device detects the lower layer protocol used by the end station and configures the link to use the point-to-point protocol, the lower layer protocol used by the end station, and an asymmetric digital subscriber line (ADSL) protocol. A method including signaling the end station to use on the link a lower layer protocol having a particular relationship with the lower layer protocol used by the portion of the network.

Abstract: A cell bus, which reduces the number of conductors required to transfer data in a telecommunications switching fabric, contains a plurality of conductors, Data[X:0], for transmitting information. A cell bus interface generates a cell bus frame that includes a plurality of words, "X" bits in length, of both data and control information that includes, in part, routing information for the data. As a result of encapsulating data and control information into and cell bus frame for transmission on the Data[X:0] conductors, the number of conductors required to transmit data is reduced. An asynchronous transfer mode (ATM) switching fabric, which includes a plurality of cell buses configured in a point to point fashion between a cell routing unit (CRU)/ATM fiber bank interface unit (AFIU) and a plurality of optical line units (OLUs), is also disclosed.

Abstract: A system and method for reducing signal attenuation of integrated services digital network (ISDN) digital transmissions at the subscriber loop, thereby increasing the available subscriber loop range, is provided. An ISDN digital transmission system is used for transmitting and receiving digital information via a line termination at a central office. Customer premises equipment is coupled to a network termination (NT-1) within the customer premises, which is in turn coupled to interface the line termination at the central office. A plurality of inductive load coils are coupled in series with the two-wire subscriber loop ISDN BRI at predetermined distance intervals, which are calibrated to resonate the two-wire bus.

Abstract: A system for interfacing a plurality of analog telephones to an integrated services digital network (ISDN) line of telecommunications network is disclosed. The system comprises a plurality of line interface units connected to respective telephones and a distribution line, and a communications controller interconnects the distribution line and the ISDN line. The communications controller transmits digital data frames on the distribution line, each frame having a frame start and a plurality of control channels and voice channels of which respective voice and control channels are associated with respective line interface units. The controller can instruct each line interface unit on the control channel of that unit, to issue ringing voltage, dial tone, busy tone or ringing tone, and it selectively couples the voice channels to the ISDN line.

Abstract: The multi-stage interconnection network of the present invention includes the use of switches in the first stage that have parallel path seeking capabilities. With these switches, a directed flash-flood can be instigated from any one node wherein multiple paths through the network to a designated destination node are tried in parallel in an attempt to find a connection path therebetween. The switches in the first and second stages are interconnected such that each switch in the first stage is connected with every possible priority level to the switches of the second stage. The parallel path seeking switches and network are further configured to test for rejection of the flash-flood by monitoring all connections in combination.

Abstract: A transport interface (10) provides add drop multiplex functionality and termination requirements for the transportation of network traffic. The transport interface (10) includes high speed units (12), broadband interfaces (16), and SONET formatters (18). Each high speed unit (12), broadband interface (16), and SONET formatter has redundant protection pairs (A and B). The high speed units (12), broadband interfaces (16), and SONET formatters (18) communicate with each other by in-band datalinks (40). The redundant protection pairs (A and B) communicate with one another by protection pair datalinks (42). The in-band datalinks (40) and the protection pair datalinks (42) provide an effective means for performing protection switching within the transport interface (10) in the event of component failure. The in-band datalinks (40) are generated out of available or consumed bytes within either a section overhead (32) or a line overhead (34) of SONET OC-N frame (30).

Abstract: The present invention comprises a smart subscriber line interface card (SLIC). The SLIC of the present invention includes a switch coupled to a data transmitter, a DAC (digital to analog converter), and a controller circuit. The data transmitter is coupled to a first input of the switch and is adapted to generate a data transmitter output from a received digital network signal and couple the data transmitter output to the first input of the switch. The DAC is coupled to a second input of the switch and is adapted to generate a DAC output from the received digital network signal and couple the DAC output to the second input of the switch. The controller circuit is coupled to the switch and functions by configuring the switch for either efficient data transmission via the data transmitter, or conventional communication via the DAC.

Abstract: A multiplex extender 26 for permitting discrete I/O devices 34, not individually equipped to decode multiplex channel addresses, to be multiplexed on a time division multiplexed control bus 10. The multiplex extender 26 is connected intermediate the time division multiplexed control bus 10 and a branch line 30 and includes a multiplex channel address decoder 78, a data disconnect switch 82 and a branch line controller 90. The multiplex channel address decoder 78 is selectively programmed to one of the multiplex channel addresses of the time division multiplexed control bus 10. The multiplex channel address decoder 78 produces one or more output signals, each being determined by the multiplex channel address which has most recently been decoded.

Abstract: An enhanced Time Slot Interchange (TSI) facility, in addition to serving synchronous channels of communication, decomposes and composes asynchronous data cells to provide real-time communication among and between both synchronous and asynchronous channels served by a network access switch. An asynchronous cell comprises a 5 byte header and a 48 byte payload. The payload comprises voice samples from a temporarily defined set of DSO facilities and/or data from a variety of data facilities. Time slots of the TSI are temporarily assigned to the payload bytes of each incoming asynchronous cell; the payload bytes are stored in memory locations corresponding to those time slots; and the stored data is read out during time slots assigned to the destination channels of communication. The TSI comprises three data rams to accommodate for frame to frame jitter in the time of arrival of payload samples.

Abstract: A D4 channel bank data bus monitoring scheme automatically determines if a channel unit connector slot is occupied, without having to gain physical access to the interior of the channel bank cabinet and inspect the channel bank's backplane slot positions. To this end, for a respective channel unit connector slot the channel bank's transmit data bus, which is initially pulled high via a pull-up resistor, is monitored for an all `1`s state. If the data on the bus is not all `1`s, then it is inferred that a channel unit is installed. If an all `1`s state is not detected, then, during the next time slot for that channel unit, the bus is decoupled from the pull-up resistor and coupled instead to a `soft` pull-down resistor. If the data on the bus is now all `0`s, it is inferred that the previously read all `1`s condition was due to the fact that no channel unit is installed, and the channel unit connector slot is declared as empty.

Abstract: A TR-8 compatible Remote Terminal (RT) with 96 subscriber line capacity is partially or wholly replaced with one or more D4 channel banks each comprising 24 subscriber line capacity without changing the TR-8 interface module within the servicing telecommunications exchange. The D4 channel bank is connected via a T-1 digital link to any one of the A, B, C, and D links within the TR-8 interface module. A-B bit pattern data and time slot assignments communicated between the D4 channel bank and the TR-8 interface module are converted to be compatible with each other. If a D4 channel bank is connected to the TR-8 interface module via an A-link, the maintenance data are further ignored. Connecting a D4 channel bank to a TR-8 interface module allows small telecommunications service providers to more economically provide line access to sparsely populated customer sites.

Abstract: It is disclosed hereby that a switch system comprises a N:M switch circuit, a plurality of layer 2 switches, each comprising a plurality of packet processing channels, and a plurality of network interfaces, each comprising a fixed number of pairs of ports to be directly connected to the same number of devices. The N:M switch is coupled with the N number of the packet processing channels of the layer 2 switches at the N-side and with the M number of the ports of the network interfaces at the M-side. When a packet containing a destination to a receiving device sent by a sending device arrives at the network interface, the N:M switch establishes an electronic connection between an available packet processing channel and a port to which the sending device is connected, the packet passes through to the packet processing channel in which the packet is processed and stored.

Abstract: A switch executes complex protocol processing on control cells easily at a high speed in the same manner as normal cells are processed. The switch flexibly copes with new or modifies specifications and standards which might be established in the future for processing RM and OAM cells. Each link interface portion 1 of the ATM switch includes an input cells processing portion 7 and an output cell processing portion 8 provided at the input side and output side of a cell exchange portion 2, and cooperates with a control information maintenance portion 9 to execute application of switching information that the cell exchange portion 2 requires in input cells, and rewriting of ATM cell headers of input cells to and output cells from the cell exchange portion 2. The input cell processing portion 7 and the output cell processing portion 8 of each include a fixed sequencer and a microcode sequencer to execute complex protocol processing such as OAM, RM and other control functions in the microcode sequencer.

Abstract: Ports of an ATM (Asynchronous Transfer Mode) switch are consolidated into cluster modules to increase the aggregate throughput of the switch. Packets are routed between cluster modules using an intercluster switching network. The intercluster switching network includes a plurality of input channels and output channels. During a switch cycle, a maximum of "K" packets are delivered to each of the output channels of the intercluster switching network. This maximum of "K" packets is a speedup per cluster module that is shared between ports of each cluster module. Consequently, each output port of a cluster module operates with a peak speedup of up to "K" packets per switch cycle thereby increasing the aggregate throughput of the switch.

Abstract: A multiplex conversion unit is configured with the functions required for a specific network to which it is applicable more economically. Each OC-12IF circuit pack includes a switch for performing time slot assignment (TSA) between a plurality of high-speed transmission lines accommodated in the OC-12IF circuit pack and at least a low-speed transmission line accommodated in at least a DS3IF circuit pack. An ADM circuit pack includes a switch for performing time slot interchange (TSI) between the high-speed transmission lines and the low-speed transmission line. In an application to a network requiring the TSI function, the switch of the OC-12IF circuit pack performs only the add/drop multiplex (ADM) operation between the signals input/output by the high-speed transmission lines and the ADM circuit pack, and the switch on the ADM circuit pack performs the TSI operation.

Abstract: An internal signal within a SONET element has a transport format having overhead and payload mapped in a manner similar to the Synchronous Optical Network standard mapping, except having selected overhead bytes defined differently, including a byte used for communicating odd parity calculated over an odd number of bytes of a frame of the transport format to determine correct or incorrect parity, selected bytes used for inter-module automatic protection switching, and a pointer having a selected fixed value, along with an adjusted virtual tributary pointer in a virtual tributary mode.

Abstract: In the inbound direction, a tributary processor (32) includes an SPE encoder/decoder for extracting a synchronous payload envelope (SPE) from an STS-1P signal. A path terminator (62) may extract DS3 signals or a matrix payload envelope (MPE) from the STS-1P SPE. A DS1/DS3 extractor (68) generates DS1 signals from either the DS3 or MPE signals. An MPE mapper (70) creates MPE signals from the DS1 signals. A wideband stage interface (74) converts the MPE signals into matrix transport format (MTF) signals for cross-connection in a wideband center stage matrix (22). In the outbound direction, the wideband stage interface (74) receives MTF signals from the wideband center stage matrix (22) and generates MPE signals therefrom. The MPE signals are sent through the MPE mapper (70) in order to extract DS1 signals. The DS1 signals are converted to DS3 signals or another MPE mapping by the DS1/DS3 extractor (68). The path terminator receives DS3 or MPE signals for conversion into an STS-1P SPE.

Abstract: A method or apparatus for offering multiple switch access to selected lines and trunks of a multiple telecommunications switch complex. The selected lines and trunks are connected to peripheral units whose outputs are distributed by a network to a group of switches. The switches are interconnected by a second network. Advantageously, the selected lines can be served by several switches so that the failure of one switch does not deprive these lines of service. Advantageously, the two networks and the group of switches form a giant switch having high reliability.

Abstract: A common macro interface between chips that have design features in common and communicate with each other. The common macro interface (CMI) uses VHDL (VHSIC Hardware Description Language) which is the industry standard hardware design language. A common protocol is provided to resolve communication problems and comprises four signals: request; acknowledge request; data acknowledge, and read/write. A freeway system within the interfaces facilitates parallel and pipelining processes and an arbiter (also called a scheduler) is placed in front of every slave resource to control the traffic independently and to avoid traffic collisions from locking the freeway. The freeway is unique for each integrated circuit. Accordingly, macros may be moved from chip to chip without requiring complete system modifications and the effort involved in designing macros common to several chips may be shared.

Abstract: When a host connected to physical ports carries out communication outside virtual LANs formed by grouping the physical ports, a CPU for a switch determines a MAC address of the router as a destination MAC address corresponding to logic ports grouped in the same virtual LAN including a receive port to receive a packet and writes the packet and a virtual LAN number attached thereto into a first buffer for switch-router communication. A CPU for a router writes the packet written in the first buffer for switch-router communication along with the virtual LAN number into a second buffer for switch-router communication. The CPU for the switch writes the packet written in the second buffer for switch-router communication into a third buffer for physical port transmit-receive to transmit the packet to the physical ports.

Abstract: An ATM destination switch includes an ATM layer device coupled to a physical layer device. The ATM layer device includes a ATM layer interface which receives incoming ATM cells, a processor which is typically with an associated translation RAM, and an ATM layer to physical layer interface. The processor decodes the incoming ATM cell to obtain a VPI/VCI, and provides additional routing information (session number) for the cell for multicast purposes. The cell with the additional routing information is forwarded to the physical layer device which has a header processor, a multicast indicator storage table, preferably in the form of a bit map, for storing output line indications by session number, and a plurality of ATM line output interfaces.

Abstract: A multi-stage interconnection network includes the use of switches in the first stage that have parallel path seeking capabilities. With these switches, a directed flash-flood can be instigated from any one node wherein multiple paths through the network to a designated destination node are tried in parallel in an attempt to find a connection path therebetween. The switches in the first and second stages are interconnected such that each switch in the first stage is connected with every possible priority level to the switches of the second stage. The parallel path seeking switches and network are further configured to test for rejection of the flash-flood by monitoring all connections in combination.

Abstract: A system, method and article of manufacture, for improving object security in distributed object systems, in an information handling system employing object oriented technology, includes one or more processors, a storage system, a system bus, a display sub-system controlling a display device, a cursor control device, an I/O controller for controlling I/O devices, all connected by system bus an operating system such as the OS/2* operating system program (OS/2 is a registered trademark of International Business Machines Corporation), one or more application programs for executing user tasks and an object oriented control program, such as, DSOM Objects program, which is a commercially available product of International Business Machines Corporation, the object oriented control program including a system authorization policy (SAP) object, a system authorization oracle (SAO) object, and a system registration object (SRO). The SAP object encapsulates management of a resource authorization policy.

Abstract: A system and method for enabling a remote user to maintain a virtual presence at a corporate office and behave substantially as if the user were physically present at the corporate office. The remote user's telephone behaves as a PBX extension, and the remote user may send and receive faxes and email, have Internet access and maintain LAN connectivity, substantially as if the user were present at the corporate office. The remote computer system includes an individual remote worker unit or communication device, and the remote computer executes virtual presence software according to the present invention. The corporate office includes a virtual presence server according to the invention which connects to the corporate PBX and also to the corporate LAN. The virtual presence server executes software which enables the remote user to maintain a virtual presence at the corporate office.

Abstract: A switching network for the pick-up and forwarding of data streams has a plurality of input line units and output line units which respectively accept or output data streams in fixed multiplex frames, and which are connected in common to an exchange bus. A respective data memory whose memory cells are individually allocated to the bit places of a multiplex frame for the individual output line units is provided in the input line units. The data bits of a multiplex frame are entered bit-by-bit into the corresponding memory cells in the data memories based on the criterion of allocation information. The memory cells of the individual data memories are synchronously driven by a central control unit in a fixed sequence for the output of stored data bits onto the exchange bus. Only one of the data bits corresponding to one another in the individual data memories is thereby enabled based on the criterion of enable information, whereas the others are masked.

Abstract: A serial input/output circuit with an automatic transfer function can easily re-transfer correct data even if a transfer error occurs during automatic transfer. When the transfer of one data has been completed, an automatic transfer data pointer normally automatically updates its contents and indicates an address in an automatic transfer RAM, which corresponds to data to be next transferred. An error generation active circuit makes an error control signal significant when an error detecting circuit detects an error produced in data or the occurrence of the error in the data is notified from a transfer opposite party. When the error control signal is made significant, the automatic transfer data pointer and the transfer counter do not update their values.

Abstract: A digital access arrangement, coupled between a data terminal equipment having a transmit line and a receive line and tip and ring lines of a network, having a circuit that provides polarity check, hook/switch control, and data modulation functionality. The circuit includes a controller and six controllable switches, each having a conducting state and a blocking state.

Abstract: In the inbound direction, a tributary processor (32) includes an SPE encoder/decoder for extracting a synchronous payload envelope (SPE) from an STS-1P signal. A path terminator (62) may extract DS3 signals or a matrix payload envelope (MPE) from the STS-1P SPE. A DS1/DS3 extractor (68) generates DS1 signals from either the DS3 or MPE signals. An MPE mapper (70) creates MPE signals from the DS1 signals. A wideband stage interface (74) converts the MPE signals into matrix transport format (MTF) signals for cross-connection in a wideband center stage matrix (22). In the outbound direction, the wideband stage interface (74) receives MTF signals from the wideband center stage matrix (22) and generates MPE signals therefrom. The MPE signals are sent through the MPE mapper (70) in order to extract DS1 signals. The DS1 signals are converted to DS3 signals or another MPE mapping by the DS1/DS3 extractor (68). The path terminator receives DS3 or MPE signals for conversion into an STS-1P SPE.

Abstract: A method for controlling an operation and management subsystem in a signalling message exchange No.1 system, the operation and management subsystem including a user interface subsystem, a target interface subsystem, an operation control subsystem, a signalling network operation system interworking subsystem, an operation and management subsystem management subsystem and a data management subsystem.

Abstract: A high-speed signal input to and output from a high-speed optical interface part connected to an optical fiber transmission line is switched to different lines such that the switching is conducted by cross connect parts on an arbitrary basis. The high-speed signal is separated so as to obtain the low-speed signal. The low-speed signal output from the cross connect parts is separated so as to obtain the subscriber signal by signal terminal parts. Call connections are conducted for each subscriber by a time slot interchange part, whereupon a subscriber interface part performs analog-to-digital and digital-to-analog conversion so as to serve as an interface for a subscriber.

Abstract: A CPE such as an ISDN telephone subset or multimedia equipment includes an interface recognition unit that connects to the network interface and adapts itself to allow the CPE to be used with standard ISDN interfaces and an analog interface. The interface recognition unit includes an interface recognition switch (IRS) that performs two functions. First, the IRS protects the CPE from damage in those instances where a non-standard network interface is connected to the CPE. Second, for standard interfaces, it identifies the type of network interface and routes the incoming signals appropriately. Specifically, if the IRS detects a T interface, the incoming signals are switched directly to a T interface circuit for controlling and powering the higher functions of the CPE. If the IRS detects a U interface, incoming signals are automatically switched to a U interface circuit for controlling and powering the CPE.

Abstract: A private exchange includes a changeover control in order to control existing POTS customer premises equipment access redefinition in a changeover to an ISDN basic rate interface. The exchange includes a first port for connection to a local exchange, a second port for connection to a conventional analog subscriber station, and a controller which is connected with the first and second ports. The controller includes a digital network communication circuit and a cutover device for bypassing the digital network communication circuit in order to directly connect the first and second ports. The controller further includes a detector for activating the cutover device to bypass the digital network communication circuit in response to the first port being connected to a plain old telephone service and for deactivating the cutover device to connect the first port to the second port through the digital network communication circuit when the detector determines that the first port is connected to a digital exchange.

Abstract: A switch (25) for a service node (18) forming part of a telecommunications network (FIG. 1), having a switching matrix (32) and a plurality of line interface circuits (37). Each of the line interface circuits (37) includes a cross-point switch (47), a plurality of a first type of processing devices (such as digital signal processors 52) and a second type of processing devices, such as a microprocessor (38). The digital signal processors are connected to the cross-point switch (47) by a serial interface (56) suitable for receiving digitized speech signals. The microprocessor is connected to the cross-point switch via a parallel bus (57) and the cross-point switch includes devices for facilitating a communication between the digital signal processor and the cross-point switch.