Abstract: An improved telephony adapter compresses voice data, creates IP packets, and prioritizes the voice IP packets over the data IP packets. Preferably, the compression and packetization interval is such that the bandwidth occupied by the voice IP packets is approximately half of the minimum average available bandwidth in the upstream direction, thereby maintaining acceptable latency and voice quality of the speech. Further enhancement is achieved by causing the ISP to also give priority to voice packets that are destined to the telephony adapter, over the data packets that are destined to the telephony adapter.

Abstract: A network management apparatus interconnects a plurality of computers through physical lines having a predetermined line speed to manage a switch apparatus constructing a parallel computer system. The switch apparatus comprises a plurality of physical port units to enable or disable the same through individual power supply ON/OFF control for the physical port units, thereby changing and controlling the line transmission speed according to the enable number. A logical port constructing unit in the network management apparatus bundles the physical lines by a plurality of physical port units in the switch apparatus to construct logical lines. A port control unit changes the number of operations of a plurality of physical port units assigned to the logical port units through the power supply ON/OFF control according to a necessary data transmission speed for the logical port units, thereby dynamically changing the line transmission speed.

Abstract: A trace detector prevents network mapping and tracing by detecting an initial packet containing an initial time to live value that meets a first predetermined threshold range. The trace detector identifies a source address of the initial packet and adjusts a threshold time to live range for detection of at least one subsequent trace route or response packet associated with the source address of the initial packet. In response to detecting the subsequent packet(s), the trace detector processes the subsequent packet(s) associated with the source address of the initial packet according to a security policy to prevent a trace process originating the initial packet from tracing a network using the at least one subsequent packet.

Abstract: A system and method for routing operations, administration, and maintenance traffic for an optical network are described. A subset of a routing information set is transmitted to tributary cards of a network element. The tributary cards route operations, administration, and management traffic based on the subset of the routing information.

Abstract: An addressing type frequency counter circuit is disclosed, which receives a multiple parameter and a clock of addressing input from an external circuit, and uses a hardware address to perform the addressing operation for outputting a clock value, thereby utilizing memory more efficiency, reducing the cost by purchasing less memory to achieve the same performance, and improving integration of the addressing type frequency counter circuit.

Abstract: A high speed communications interface divides data into a plurality of lanes, each lane encoded with clocking information, serialized, and sent to an interface. During cycles when there is no available data to send, IDLE_EVEN and IDLE_ODD cells are sent on alternating cycles. Data is transmitted by sending a header which spans all lanes and includes a START symbol. The final data transaction includes a Frame Check Sequence (FCS) which operates over the entire header and data. The packet is terminated by an END symbol, which is sent after the final data, and the remainder of the lanes are padded with IDLE_EVEN, IDLE_ODD, IDLE_EVEN_BUSY, or IDLE_ODD_BUSY cycles. The interface has a variable clock rate.

Abstract: Methods and systems for performing stateful signaling transactions in a distributed processing environment are disclosed. A method for performing stateful signaling transactions in a distributed processing environment includes receiving a signaling message at a routing node, such as a signal transfer point. The signaling message is distributed to one of the plurality of stateful processing modules. The receiving stateful processing module buffers the signaling message and initiates a stateful transaction based on the signaling message. Initiating the stateful transaction may include generating a query message and inserting a stateful processing module identifier in the query message. The query message is sent to an external node, such as an SCP, which formulates a response. The SCP may insert the stateful processing module in the response and send the response back to the signal transfer point.

Abstract: A method and apparatus for multi-modal communication includes a controller (236) operably coupled to at least one multi-modal session proxy server (226). On a per multi-modal session basis, the controller (236) provides the multi-modal session proxy server (226) with a multi-modal proxy identifier (138). The multi-modal proxy identifier (138) is then provided to at least one browser with a per session multi-modal proxy evaluator (220) having a browser proxy identifier (140) wherein the browser proxy identifier (140) is evaluated in view of the multi-modal proxy identifier (138). The multi-modal session proxy server (226) then receives an information request (231) from the browser with per session multi-modal proxy evaluator (220) wherein the requested information is fetched from a content server (240).

Abstract: A multiple-contents distribution in a client and server system is disclosed. The multiple-contents contain contents-pieces, which are to be distributed to a set of clients including mobile phone terminals. The set of clients are registered with the server in response to registration requests. The server determines an order of the registered set of clients. The server then initiates a distribution of the contents-pieces to the registered sets of clients, wherein the contents-pieces are selected in accordance with the order of the clients.

Abstract: The present invention relates to a switching unit with a scalable and QoS aware flow control. The actual schedule rate of an egress queue, wherein the outgoing traffic belonging to a particular class of service is backlogged, is measured and compared to its expected schedule rate. If the egress queue is scheduled below expectation, then the bandwidth of every virtual ingress-to-egress pipe connecting an ingress queue, wherein the incoming traffic belonging to the same class of service is backlogged before transmission through the switch core fabric, to that egress queue is increased, thereby feeding that egress queue with more data units.

Abstract: A channel adapter, configured for sending frame data according to link widths selected based on management frames received from a link partner, includes a multiplexer circuit configured for selectively switching the frame data supplied according a prescribed maximum link width, to one of a plurality of available link widths for a transmit bus, and a bus controller. The bus controller is configured for controlling the multiplexer circuit to switch the frame data to one of the available link widths, including the prescribed link width, based the selected link width. Hence, a channel adapter can be configured for an optimum link width for communication with a corresponding channel adapter on a peer node.

Abstract: A source process communicates with a sink process by writing messages to a finite queue. The source process determines whether the finite queue is full. If the source process determines that the finite queue is full, the finite queue is emptied and a refresh-all message is written to the finite the queue. When the sink process reads a refresh-all message from the finite queue, the sink process performs a refresh-all operation in which a refresh operation is performed for each member of a set of objects.

Abstract: A scalable, two-stage rotating priority arbiter with re-circulation and bounded latency for use in multi-threaded, multi-processing devices. An apparatus implementing the two-stage arbiter includes a plurality of masters configured in a plurality of clusters, a plurality of targets, and an chassis interconnect that may be controlled to selectively connects a given master to a given target. The chassis interconnect includes multiple sets of bus lines connected between the plurality of clusters and the plurality of targets forming a cross-bar interconnect, including sets of bus lines corresponding to a command bus. A two-stage arbitration scheme is employed to arbitrate access to the command bus. The first arbitration stage is used to arbitrate between target requests issued by masters in a given cluster. The second arbitration stage is used to arbitrate between winning first-stage target requests. One embodiment of the arbitration scheme employs a rotating priority arbitration scheme at the first stage.

Abstract: A method for transmitting and receiving short message broadcast services in a communication system is disclosed. The present invention reduces a battery consumption of a mobile station by additionally using an inserted message field of a broadcast indicator for notifying whether a broadcast message is being transmitted from a base station to the MS, thereby allowing a more efficient short message broadcast service.

Abstract: A method for decreasing routing latency of a switching platform comprises identifying ports which have changed their operational state and modifying the port polling code associated with the respective ports so that operational ports are polled for frames to be routed, while non-operational ports are not polled. In one embodiment, the method is implemented in a fiber channel switch. Non-operational ports are identified as having operational states below a pre-determined threshold level of functionality. The polling code for the ports is modified while polling operations are carried out in the switch. The code for a newly operational port is modified by copying into the code one or more instructions that poll the port for a frame and routes the frame. The code for a newly non-operational port is modified by copying into the code a branch instruction that bypasses the remainder of the polling code for the port.

Abstract: A bus structure providing pipelined busing of data between logic circuits and special-purpose circuits of an integrated circuit, the bus structure including a network of pipelined conductors, and connectors selectively joining the pipelined conductors between the special-purpose circuits, other pipelined connectors, and the logic circuits.

Abstract: A device on a process control network transmits scheduled messages at periodic intervals and unscheduled messages between scheduled message transmissions. A dynamic time remaining value is produced by subtracting a current timer value from a next scheduled event time each time the timer is incremented. If the time required to transmit an unscheduled message is greater than the time remaining value, the message is not transmitted.

Abstract: A method and apparatus for improved operation of a packet network by controllably providing switched physical alternate links between packet network nodes, at least one of which is a host, and using those switched physical alternate links to supplement the capacity of the packet network. A switched physical alternate link is composed of physical elements, switchable connection devices, and a manager, such that a switched physical alternate link behaves as a single point-to-point physical link between nodes in a packet network. Creating and removing switched physical alternate links as the packet network operates provides supplemental carrying capacity between the packet network nodes connected by switched physical alternate links, while overall packet network congestion is simultaneously reduced.

Abstract: A packet scheduling apparatus corrects an overhead amount between a DSL rate and a packet rate, converts DSL rate information to the packet rate, and shapes the IP packets from the Internet such that the IP packets are delivered at a transmission rate equal to or lower than the packet rate. An IP/ATM converter converts the IP packets from the packet scheduling apparatus to ATM cells. A DSL multiplexer has a DSL current rate detector for supplying DSL rate information indicative of a currently set DSL rate, and transmits the ATM cells from the IP/ATM converter or the IP packets from the packet scheduling apparatus to user terminals through DSL processing using telephone lines.

Abstract: An internally-integrated type computer network switching unit is proposed, which is designed for internally integrated to a computer platform, such as a server, for providing the server with a network switching capability that allows the server to selectively switch between various connections to a number of network nodes for the purpose of establishing a LAN (Local Area Network); and which is characterized by that it is internally integrated to the internal circuitry of the server so that it can be implemented without having to utilize a dedicated set of microprocessor, memory, and operating system (OS), and can be directly controlled via the CPU and OS of the server. This feature allows the internally-integrated type computer network switching unit of the invention to represent a more cost-effective and highly expandable LAN solution for network applications.

Abstract: A method for utilizing a household's existing telephone line wiring and existing analog telephone sets to make VoIP calls and PSTN calls is provided. The method allows the installation of a simple VoIP routing device in the existing wiring without restructuring of the existing wiring or a deployment of a totally separate network. The method deploys a number of mapping devices to take advantages of the un-used wires in the existing wiring. The mapping devices are installed between the wall jacks and the phone sets, and between a wall jack and the VoIP routing device. The installation of the mapping devices is easy and requires no special tools and experienced personnel.

Abstract: An apparatus and method for performing congestion management in a switch or router is disclosed. The apparatus acquires and or generates performance metrics for a plurality of switching module coupled via a switching fabric, generates a performance index based on the attributes from the switching modules, and allocates switching fabric bandwidth based on a weighted combination of the performance metrics. The performance metrics may include past and presents values of some attributes as well as predicted values.

Abstract: In a redundant system where multiple network interfaces can be switched, an interface switching device includes: a transformer for transforming automatic switch information between a predetermined type used for a predetermined network interface and each of other types used for network interfaces other than the predetermined network interface; a switch controller for performing switch control for automatic switch information of the predetermined type; and a control interface for connecting a first network interface to the switch controller via the transformer when first automatic switch information received from the first network interface is not of the predetermined type.

Abstract: A method and system of data communication, switching network board are disclosed. The data communication system includes multiple line card chassis, each including multiple line cards, at least one switching chip and at least one relay chip. The line card is respectively connected to the switching chip and the relay chip of the same line card chassis. The switching chip of one line card chassis is connected to the relay chip of at least one of other line card chassis. The relay chip of the one line card chassis is connected to the switching chip of the at least one of other line card chassis. The switching network board includes a switching chip and a relay chip. By implementing the above embodiments, the networking complexity is reduced, the networking cost is saved and the system reliability is enhanced in the case that a few line card chassis are cascaded.

Abstract: The invention relates to a data transmission device having a number of N uplink interfaces (E1, UP) that can be directed via a processing line (A, B) provided with a data processing component (T, LIC) to a starting element (F). The invention is characterized in that a first processing line (A) and a second processing line (B) are provided, each comprising two separate processing rows (A1, A2, B1, B2) for N/2 data lines each. A first half (1 to 8) of the N uplink interfaces (E1, UP) is connected to the first processing line (A) and the second half (9 to 16) of the N uplink interfaces (E1, UP) is connected to the second processing line (B). Every processing line (A, B) comprises a circuit arrangement (8<SB>A</SB>, 8<SB>B</SB>) that connects the N/2 data lines connected to the processing line (A or B) to the respective other processing line (B or A) to one of the processing rows (A1, A2, B1, B2) available there.

Abstract: A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(1,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, together with the error-tolerant sync mark detection and the ability to recover data when the sync mark is obliterated, allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery.

Abstract: A switching system compatible with ATCA/ATCA 300 architecture and a method for improving switching bandwidth, including: a backplane, a plurality of node boards and at least two hub boards; the node boards are connected with the hub nodes through the backplane; each node board is connected with the at least two hub boards; different data is transmitted on at least two data links between the node boards and the at least two hub boards, and the at least two hub boards cooperate with each other to implement a data switching between the node boards.

Abstract: The present invention relates to a system and a method for distributing both IP signals and non-IP signals in an Ethernet based network, wherein the Ethernet based network comprises UTP cabling comprising a number of wires, the method comprises distributing said non-IP signals through a signal path based on wires comprised in said cabling and not being used for distributing said IP signals. The invention further relates to a gateway, a router and a switch for receiving both IP signals and non-IP signals, processing said IP signals and non-IP signals and transmitting said processed IP signals and non-IP signals via the Ethernet based network.

Abstract: One embodiment of the present invention provides a system for routing data between integrated circuit devices. This system couples together an n-dimensional grid of integrated circuit devices using multiple independent communication networks, wherein each of the communication networks only moves data in two orthogonal directions (e.g., North and East, North and West, South and East, or South and West). The system also includes a routing mechanism that routes data across these communication networks, as well as, into, out of, and through integrated circuits within the n-dimensional grid of integrated circuits. Note that the process of routing a signal across a given network is greatly simplified because it is not possible to create a cycle that causes a deadlock within a given network.

Abstract: A system for path finding and terrain analysis. The system includes at least one processing unit, a graph processing unit and an artificial intelligence logic unit. A local bus is coupled to the at least one processing unit, the graph processing unit, the artificial intelligence unit and a bus interface unit. A memory bus is coupled to said bus interface unit, the at least one processing unit, a data memory, and a program memory. The graph processing unit further includes a network of interconnected nodes. Each of said nodes have at least one digitally programmable delay unit.

Abstract: The present invention provides a method of controlling media streams in an electronic device that includes receiving an input stream from a plurality of applications executed on the electronic device outside of an execution thread of any of the plurality of applications and routing each of the input streams to an output device according to a set of preconfigured rules. In a second aspect, the present invention also provides an electronic device that includes a plurality of output device components and a processor that is adapted to execute 1) a plurality of applications producing streams of data, and 2) a mediator that is coupled to each of the output devices adapted to receive the data streams from each of a plurality of applications and route the data streams from the plurality of applications to one or more of the output devices according to a set of preconfigured rules.

Abstract: Network data switching includes receiving a cell; associating the cell with a destination port; selecting, based at least in part on a mapping of a plurality of output ports and a plurality of egress links, a selected egress link that has been soft configured to be associated with the destination port, wherein each of the plurality of egress links is configured to send data from a switch fabric to a corresponding access node; and switching the cell to the selected egress link.

Abstract: This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video source without an operating system. The method relates to operation of a microprocessor which is suitably arranged to carry out the steps of the method. The method includes details of operation of the specialized microprocessor.

Abstract: A synchronous read channel having a single chip integrated circuit digital portion which provides digital gain control, timing recovery, equalization, digital peak detection, sequence detection, RLL(l,7) encoding and decoding, error-tolerant synchronization and channel quality measurement is disclosed. The integrated circuit accommodates both center sampling and side sampling, and has a high degree of programmability of various pulse shaping and recovery parameters and the ability to provide decoded data using sequence detection or digital peak detection. These characteristics, error-tolerant sync mark detection, and the ability to recover data when the sync mark is obliterated allow a wide variety of retry and recovery strategies to maximize the possibility of data recovery.

Abstract: Systems and methods for switching electronic signals are disclosed. The switching may be performed with a low loss and low peak voltages. The switching scheme is suitable for switching RF signals, for example, and may be used in devices such as wireless systems, terminals, and handsets. One exemplary embodiment is directed to a CMOS-implemented transmit/receive switching system. The system comprises one or more transmit ports, each coupled via a respective transmit path to an input/output port and one or more receive ports, each coupled via a respective receive path to the input/output port. Each receive path comprises a switching circuit comprising a transistor and an inductor in parallel with the transistor. The switching circuit is adapted to at least substantially isolate the respective receive port from the input/output port when the transistor is in an on state and operatively couple the respective receive port to the input/output port when the transistor is an off state.

Abstract: By obtaining the address of a circuit switching controller in a network with which a mobile station is registered, a packet call controller instructs the circuit switching controller to send notification of when a handoff request is received for a mobile station by the circuit switching controller. The handoff request is for transferring a packet switched call to the circuit switching controller as a circuit switched call. The notification request includes an identifier, which the circuit switching controller uses in notifying the packet call controller of the handoff request. In response to the notification, the packet call controller re-establishes call control and bearer paths between the call endpoints.

Abstract: An information management system within a client/server based computer system is disclosed. The information management system manages information as to the dynamic locations and continuous changes relating to services offered within the computer system. The information management system utilizes a service point map (SPM) that monitors such changes. The SPM tracks changes relating to services, sphere, location, port, and epoch value. The SPM may be hierarchical in nature. Parallel or duplicate services may also exist within the system.

Abstract: A configurable switching fabric port is disclosed having, in a particular configuration. A first interface that employs port interface resources and leaves at least one interface resource dormant and a second interface utilizing the dormant resource. One particular fault non-tolerant architecture, the RapidIO System, is specifically addressed. One implementation of this system incorporates transmission and reception ports configurable as 16 and 8 bit interfaces. In the 8-bit configuration, an 8-bit interface incorporates the least significant 8-bits of signal resources. Further, in the reduced, or 8-bit configuration, the most significant port interface resources of the 16 bit port are surplus.

Abstract: Method for providing a transmission link includes providing a proxy equipment including cache or buffer, establishing a streaming connection or session between the proxy equipment and the mobile terminal, upon request of a service from the terminal requesting streaming data, receiving and storing at the equipment the requested streaming data from a server intended for the mobile terminal and forwarding the received and stored streaming data from the proxy equipment to the mobile terminal if the mobile terminal is detected to be under the coverage of and/or connected to the discontinuous coverage network, where when the request for the service by the mobile terminal is received by the proxy equipment, the proxy equipment establishes a continuous data and signaling transmission link with the server to receive the requested streaming data, and a discontinuous data transmission link with the mobile terminal to forward the received streaming data to the mobile terminal.

Abstract: This invention relates to a SIP and SDP protocols. The idea of the invention is to modify SDP descriptions included in SIP messages to facilitate transcoding. After receiving an INVITE message from a calling party, the SIP proxy negotiates with a transcoder for getting a list of codecs of the transcoder and their address information. The SIP proxy adds the codec list of the transcoder to the received SDP description in the invite message, and sends this way modified SDP description in an INVITE message to a called party. After receiving the modified SDP, the called party selects codecs or a list of suitable codecs according to preferences in the modified SDP and its own preferences.

Abstract: A reliable packet communication device capable of flexibly adding new functions. A packet communication device is composed of multiple interface elements (IFEs), switching elements (SWE) connecting these IFEs, and a routing manager element (RME) and may also if necessary comprise special functional packet processors (xFPs) capable of different special functions. The interface element and special functional packet processor are connected by a logical bus. For the purpose of connecting the interface elements and special functional packet processors through the switching element when the logical bus has a failure, the logical bus data format is made identical to the data format for passing data through the switch element and a selection circuit is installed in the interface element for selectively sending and receiving data to/from either the logical bus or the switching element.

Abstract: A data processing system performs any-to-any transmission of data blocks. The system receives the data blocks on incoming data streams, and load balances the data blocks across a number of processing paths. The processing paths process the data blocks causing one or more of the data blocks to become out of order relative to an order in which the data blocks were received. The system hashes the data blocks to determine a manner in which to transmit the data blocks, reorders the data blocks to restore the order in which the data blocks were received, and transmits the reordered data blocks on outgoing data streams.

Abstract: The invention provides a method and system for operating a switch, in which incoming data cells are converted from parallel to serial for synchronous input to a switch interconnect, converted from serial to parallel for parallel switching, converted from parallel to serial for synchronous output from the switch interconnect, and converted from serial to parallel for output. The switch interconnect and its input and output interfaces are controlled by a single frequency source, so that all serial data communication paths into and out of the switch interconnect are phase synchronized to within one clock cycle. A single frequency source for the switch system is coupled to the input interfaces, to output interfaces, and to the switch interconnect. The input interfaces each include a PLL which synchronizes to the single frequency source once for all serial communication to the switch interconnect.

Abstract: Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.

Abstract: Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.

Abstract: Methods and apparatus are described relating to a crossbar which is operable to route data from any of a first number of input channels to any of a second number of output channels according to routing control information. Each combination of an input channel and an output channel corresponds to one of a plurality of links. The crossbar circuitry is operable to route the data in a deterministic manner on each of the links thereby preserving a partial ordering represented by the routing control information. Events on different links are uncorrelated.

Abstract: A system and method to emulate any TDM circuit on a Real-Time Scheduled Packet Network. The TDM circuit can be any serial or parallel bit stream, of any bit rate, and can either be synchronized to the Real-Time Scheduled Packet Network, or can be asynchronous to the network. The present system and method determines the requisite descriptors of a scheduled IP itinerary for any emulated TDM circuit.

Abstract: A remote test unit (RTU) and method of operation are provided for utilizes the ability of an access matrix ability to route signals. The RTU can emulate a central Digital Subscriber Line Modem (DSLM-C) for testing customer premises equipment containing a remote Digital Subscriber Line Modem (DSLM-R). The RTU can also emulate a DSLM-R for testing central offices equipment including a digital subscriber line access multiplexer (DSLAM) containing a DSLM-C. The RTU can also emulate a concentrator connected to the DSLAM, a router connected to the concentrator, an Internet service provider (ISP) connected to the router, and a web site connected to the ISP over the Internet. The RTU can further test, using emulation, ISO/OSI layers defined in the ISO/OSI reference model which are connected to the DSLAM.

Abstract: A data transmission system includes a plurality of dynamic route control units each disposed for one of a plurality of interfaces provided in the data transmission system. The route control data prepared by the dynamic route control units are combined by a specified dynamic route control unit to obtain in-system route control data, which is delivered to all the dynamic route control units. Each dynamic route control unit calculates costs for the routes between the own system and other data transmission systems based on the in-system route control data and new route control data received.

Abstract: A method and apparatus for managing the flow of data within a switching device is provided. The switching device includes network interface cards connected to a common backplane. Each interface card is configured to support the maximum transfer rate of the backplane by maintaining a “pending” queue to track data that has been received but for which the appropriate routing destination has not yet been determined. The switching device includes a switch controller that maintains a central card/port-to-address table. When an interface card receives data with a destination address that is not known to the interface card, the interface card performs a direct memory access over a bus that is separate from the backplane to read routing data directly from the central table in the switch controller. Each interface card builds and maintains a routing information table in its own local memory that only includes a routing information for the destination addresses that the interface card is most likely to receive.