Abstract: A method for processing a great amount of intra-calls in the remote control system of a full electronic exchange system, whose time switch block is provided with a voice memory device and a control memory device to switch the PCM data to the intra-direction, and with a call pass controller to transfer to the host system or loop to the intra-direction the PCM data, comprises the steps of writing call direction data for designating the intra-call direction into the data region of the control memory device to switch the PCM data sequentially stored in the voice memory device to the intra-direction, and looping the entire channels to the intra-direction to switch the PCM data from the time switch block to the intra-direction if the call direction data designates the intra-call direction according to the treatment of the great amount of the intra-calls.

Abstract: An input data (input frame) is sequentially stored in memory in time slot units. A counter counts the number of input pulses of a clock synchronous with the time slot of the input frame, outputs the count value as a write address to the memory, and outputs it as a read address to the memory. A processor in a cross-connection device preliminarily writes to the memory data indicating switching information of a time slot. The memory outputs the data stored at an address input from the counter as a read address to the memory. The memory outputs data of a time slot of an input frame stored at the address as time slot data of an output frame.

Abstract: A memory system having multiple memory banks is configured to prevent bank conflict between access requests. The memory system includes a memory controller and a plurality of memory banks operatively coupled to the memory controller, with each of the memory banks configured for storing a plurality of data items. More particularly, a given data item is stored as multiple copies of the data item with the multiple copies being stored in respective ones of a designated minimum number of the memory banks. The memory controller is adapted to process requests for access to the data items stored in the memory banks in accordance with a specified bank access sequence.

Abstract: The data multiplexing device includes a header information memory storing header information, ES buffers holding encoded data of a plurality of media, an output buffer holding packetized data, and a transfer controlling unit controlling a transfer of the header information stored in the header information memory and the encoded data held in the ES buffers and writing into the output buffer as the packetized data. The transfer controlling unit can generate the packetized data simply by controlling the transfer of the header information stored in the header information memory and the encoded data held in the ES buffers, whereby the media multiplexing can be readily achieved.

Abstract: A system for queuing packets written to memory for switching includes a data memory logically divided into multiple blocks. The system also includes multiple input ports each operable to receive packets and write the packets to the data memory. The system also includes multiple output ports each having a memory structure and one or more output queue pointers. The memory structure includes multiple memory structure entries that each correspond to one of the blocks. Each of the memory structure entries includes a memory structure next pointer that can link to another one of the memory structure entries. An output queue pointer can link to one of the memory structure entries, and the output queue pointers and memory structure next pointers form output queue linked lists. Each of the output ports can read packets stored in the data memory using the output queue linked lists and communicate the packets.

Abstract: A message transmitting queue delivers messages between a source controller and a destination controller. According to the message transmitting request of the source controller, sequentially distribute the free message row of the message transmitting queue, and set the message row to the distributed state. After the source controller writes the message of the message row, set the message row to the written state. At this moment, when the message row is in the position that is read sequentially by the destination controller, a read request is issued, so that the destination controller reads the message according to the read request when the reading completes, clears the distributed signal and the written signal, so that the message row goes back to the free state. When the message transmitting queue has no free message row, a no free message row signal to inform the source controller is issued.

Abstract: In order to enable a pointer register device including registers called shadow registers to conduct updating operation rapidly by arithmetic operation of a pointer value between the registers, a front/back register set includes a first register and a second register. A switch control section allows a read select switch and a write select switch to select different registers. When the read select switch selects the first register and the write select switch selects the second register, the sum obtained by an adder can be stored in the second register while retaining the pointer value of the first register. In this case, the pointer value need not be transferred between the registers.

Abstract: Voice services provided over a packet switched facility such as a Frame Relay network are enhanced with routing capability by providing for attachment devices which, on initialization with the network, attempt to discover other similar attachment devices on the network. Thereafter the attachment devices exchange information on terminal accessibility to improve connectivity over the network.

Abstract: Systems and techniques for transmitting a data stream to a client include transmitting a data segment from one of a plurality of nodes of a continuous media server to a client according to a scheduler on the node. A system includes a plurality of data processing devices, each data processing device coupled with at least one storage device. Each data processing device includes a scheduler to schedule transmission of the data segment to a client in sequence with other data segments, and a module to transmit the data segment to the client.

Abstract: A packet memory system including a memory space having a multiplicity of addressable memory locations for the storage of data packets, pointer control means for generating a write pointer which progressively defines where data is to be written to the memory space and a read pointer which progressively defines where data is to be read from the memory space and an ageing clock which defines a succession of intervals. The pointer control means generates a ‘current’ pointer and a ‘discard’ pointer and for each interval is operative to cause the ‘current’ pointer to correspond to an immediately previous value of the write pointer and to cause the discard pointer to correspond to an immediately previous value of the said current pointer. In this manner the portion of the memory space between the ‘discard’ pointer and the read pointer denotes data which has been in said memory space for at least two of said intervals.

Abstract: A method for employing an associative memory to implement a message passing switch. The method comprising the step of receiving data in a time slot. The method also comprising the step of examining an interrupt register to determine if the data is a message. Additionally, the method comprises the step of storing the data in a memory location and transferring the data to an external device.

Abstract: The present invention discloses a network address forwarding table lookup apparatus and method for identifying a network address to determine a next hop address to which data packets having the network address should be forwarded. The apparatus comprises a memory storing a compression-trie forwarding table. The forwarding table has multiple level modules in a compression-trie structure. With the present invention, it is possible to achieve fast IP address lookup with a compact-sized compression-trie forwarding table.

Abstract: In a switched configuration in which data links can be bundled to increase data throughput, the links in a bundle are ordered. A data sender sequentially transmits cells in the data packet over links in the bundle. For example, a first cell is transmitted over a first ordered link in the bundle. The next cell is transmitted over the next link in the bundle order and operation continues in a “round robin” fashion. The data receiver is informed in advance of the order of links in the bundle and expects cells to be distributed over the links in that order. The data sender transmits a bundle sequence number with each data cell. As each new data cell is transmitted, the bundle sequence number is incremented. The receiver uses the bundle sequence number to validate cell order, to detect lost cells, and to resynchronize cell order with the sender in the case of cell errors.

Abstract: The present invention discloses a method and apparatus for detecting a specified event in a wireless communication system. The present invention includes an application program interface (API) that facilitates communications between a mobile station communication protocol stack, which communicates with a communication network, and a mobile station application. The mobile station communication protocol stack polls a memory when the mobile station application registers a specified event. Based on the polling, the mobile station communication protocol stack then detects the specified event. In another implementation of the present invention, the mobile station communication protocol stack detects the specified event by an interrupt notice, which is triggered when the specified event occurs.

Abstract: A network switch configured for switching data packets across multiple ports uses an external memory to store data frames. A scheduler controls access to the external memory based on predetermined arbitration logic. When a data frame is transmitted to the external memory, a portion of the data frame is stored on the switch for processing by decision making logic to generate frame forwarding information. The data frame is then transmitted back to the switch for transmission through the appropriate port(s) on the switch.

Abstract: A channel interface architecture for a time division multiplexed (TDM) data communication system has a plurality of TDM communication ports coupled to serial TDM communication channels. The channel interface architecture interfaces data from any channel of any TDM communication port with any TDM communication channel of any other TDM communication port, on a per time slot/channel basis. The architecture includes a parallel data bus portion, an address bus portion, and a control portion. Each of a plurality of TDM communication channel interface units, associated with the ports, includes a multipage memory that stores data received from an associated serial communication link. The memory also selectively stores data that has been asserted onto the data bus portion of the bus architecture from another interface unit.

Abstract: For use with a fast pattern processor having an internal function bus, an external device transmission system, method for transmitting commands to an external device, and a fast pattern processor employing the system and method. In one embodiment, the external device transmission system includes a context memory subsystem that maintains a plurality of argument signature registers, each of the plurality of argument signature registers being associated with a corresponding context and containing a corresponding argument. The external device transmission system also includes a pattern processing engine that dynamically modifies an argument and generates a transmit command as a function of a context associated with the modified argument. The external device transmission system still further includes an output interface subsystem that receives the transmit command, and transmits the modified argument based upon the transmit command to an external device.

Abstract: The present invention provides a method and an apparatus for transferring data between a computer system and a network interface card that avoids virtual-to-physical address translations. The computer system allocates blocks of memory during system initialization for storing data in transit between the computer system and the NIC, and the physical addresses of these blocks of memory are stored in a table on the NIC. Consequently, address conversion is performed only once, when the memory is allocated. When a request to transfer data to the NIC is received from the upper layers, the device driver copies the data from the upper layers into the next available memory block. The device driver then formats a command and passes it to the NIC for processing. Data transfer commands are communicated to the NIC through a packet descriptor command (PDC), which is a 32-bit value subdivided into fields that completely describe the data transfer operation.

Abstract: The invention provides a method and apparatus for re-ordering data traffic units, such as IP data packets, that may have been miss-ordered during a transmission over a multi-pathway link between a source node and a destination node in a network. The re-ordering apparatus includes a storage medium for intercepting the IP data packets and holding the IP data packets to allow IP data packets delayed on slower pathways to catch-up. The IP data packets in the storage medium are re-ordered based on their sequence number in an attempt to restore the original order of the IP data packets. A maximal time delay variable determines how long a certain IP data packet can be held in the storage medium. The TP data packet is released prior to the maximal time delay variable or as the maximal time delay variable is exceeded.

Abstract: A channel interface architecture for a time division multiplexed (TDM) data communication system has a plurality of TDM communication ports coupled to serial TDM communication channels. The channel interface architecture interfaces data from any channel of any TDM communication port with any TDM communication channel of any other TDM communication port, on a per time slot/channel basis. The architecture includes a parallel data bus portion, an address bus portion, and a control portion. Each of a plurality of TDM communication channel interface units, associated with the ports, includes a multipage memory that stores data received from an associated serial communication link. The memory also selectively stores data that has been asserted onto the data bus portion of the bus architecture from another interface unit.

Abstract: A data processing system. The data processing system includes a time division multiplexed (TDM) bus and a plurality of system components coupled to the TDM data bus. A memory stores a table of allocation entries. Each allocation entry indicates which one of the plurality of system components, if any, to be allocated a corresponding bandwidth unit (BU), wherein each BU comprises a contiguous block of TDM timeslots. An allocation control circuit is coupled to the system components and the memory for accessing the allocation table and allocating BUs to the system components on a BU-by-BU basis so that the allocation control circuit operates at a slower speed than the TDM data bus.

Abstract: A switching apparatus provides adaptive high-speed operation in an asynchronous transport mode (ATM) network. The switching apparatus includes a number of switch units, with each switch unit further including storage regions corresponding to other switch units. The switching apparatus has a writing phase in which a first switch unit stores received data in its storage region that corresponds to a second switch unit. During the writing phase, data is received by the first switch unit for later output by a second switch unit. Then, in a reading phase, the second switch unit retrieves the stored data from its corresponding storage region in the first switch unit and then outputs the retrieved data. In both phases, the switch units operate simultaneously under control of a control unit which monitors traffic flow conditions and selects data transfer paths within the switch to achieve optimum data throughput.

Abstract: A digital data transfer system comprises a source module and a destination module interconnected by an information transfer medium. The source module initiates a transfer operation in which it transfers a data item and an associated address over an information transfer medium. The address having an aperture identification portion that identifies one of a plurality of apertures. The destination module receives the data item and the associated address from the information transfer medium during the transfer operation, the destination module using the one of the plurality of apertures identified by the aperture identification portion to generate an aperture value for association with the data item. The source module can also initiate a retrieval operation, during which it transfers an address over the information transfer medium to retrieve previously transferred information.

Abstract: A digital switch array, includes a serial input bus providing a plurality of input streams, each defining a plurality of time division multiplexed input channels, a serial output bus providing a plurality of output streams, each defining a plurality of time division multiplexed output channels, and an array of digital switches arranged in rows and columns. Each row is connected to a respective group of input streams and each column is connected to a respective group of output streams. The digital switches are capable of performing timeslot interchange between any input and any output channel. Each digital switch includes an enabling device for each output timeslot so that when the enabling device is enabled the associated output timeslot is driven, and at least first and second enabling inputs which when simultaneously activated cause the enabling device to become enabled. An array of activation lines are arranged in rows and columns.

Abstract: An integrated network switch operable in either full-frame or half-frame switching modes on a circuit-by-circuit basis. To effect selective operation in either full-frame or half-frame switching modes, an information memory buffer has the capacity of storing two samples per port. A connection memory contains the source addresses for the output ports. The most significant bit of an address designates the first or second sample of the two sample information memory buffer. For half-frame mode operation, the current value of the most significant bit of the write pointer (the address being written to) is used in the source address for reading when the source address is less than the write pointer. However, when the source address is greater than the write pointer, the most significant bit position is switched. For full-frame mode operation, the most significant bit of the source address will always take the inverse of the most significant bit for the write pointer.

Abstract: A multi-media-access-controller (henceforth "multi-MAC") in accordance with this invention includes a plurality of transmit data path circuits and a plurality of receive data path circuits that respectively transmit and receive data serially on a corresponding plurality of network buses, a single transmit data path controller and a single receive data path controller that monitor status of and control operation of the respective transmit and receive data path circuits. Use of only two data path controllers eliminates the plurality of MACs used in prior art devices and therefore results in significant savings in die area. Use of a single CRC calculator also results in savings in die area.

Abstract: A message-passing multiprocessor system, such as, a network interface, a method for transferring messages between a node and a node, and a method for formatting the same in a message-passing computer system are disclosed herein. In the network interface for a computer system there are a plurality of nodes connected with one another through an interconnection network for communicating messages, and more than one processor, and a local shared memory, which are connected with one another through a node bus.

Abstract: A crosspoint switch routes signals between its terminals in routing patterns defined by routing data from a host controller. The crosspoint switch includes an array of pass transistors. Each pass transistor, when turned on, provides a signal path interconnecting a separate, unique pair of the switch terminals. The crosspoint switch also includes two static random access memory banks. Each memory bank stores routing data defining a separate routing pattern and produces a separate set of output signals reflecting its stored data. A multiplexer delivers the output signals of a selected one of the memory banks to the switch array for controlling its pass transistors so that the switch array implements the routing pattern defined by the data in the selected memory bank. By loading routing data defining different routing patterns into the two memory banks, a host controller can thereafter quickly make the crosspoint switch alternate between the two routing patterns by toggling the multiplexer's control input.

Abstract: A switching network for the pick-up and forwarding of data streams has a plurality of input line units and output line units which respectively accept or output data streams in fixed multiplex frames, and which are connected in common to an exchange bus. A respective data memory whose memory cells are individually allocated to the bit places of a multiplex frame for the individual output line units is provided in the input line units. The data bits of a multiplex frame are entered bit-by-bit into the corresponding memory cells in the data memories based on the criterion of allocation information. The memory cells of the individual data memories are synchronously driven by a central control unit in a fixed sequence for the output of stored data bits onto the exchange bus. Only one of the data bits corresponding to one another in the individual data memories is thereby enabled based on the criterion of enable information, whereas the others are masked.

Abstract: An input/output switching apparatus which can construct the system more flexibly as compared with the conventional system. The input/output switching apparatus is configured so that a user can manage the connection state of a physically-existing switching unit as the connection state of a virtual switching unit which corresponds to the physically-existing switching unit. Thus, the user can control the physical switching unit merely by operating the virtual switching unit which is constructed so as to be convenient for operation.

Abstract: An integrated network switch operable in either full-frame or half-frame switching modes on a circuit-by-circuit basis. To effect selective operation in either full-frame or half-frame switching modes an information memory buffer has the capacity of storing two samples per port. A connection memory contains the source addresses for the output ports. The most significant bit of an address designates the first or second sample of the two sample information memory buffer. For half-frame mode operation, the current value of the most significant bit of the write pointer (the address being written to) is used in the source address for reading when the source address is less than the write pointer. However, when the source address is greater than the write pointer, the most significant bit position is switched. For full-frame mode operation, the most significant bit of the source address will always take the inverse of the most significant bit for the write pointer.

Abstract: A communication data switching apparatus for use between an input line, an output line, and a memory bus includes a receiver connected to the input line, a transmitter connected to the output line, a buffer memory for storing data received by the receiver and data to be transmitted by the transmitter, a memory transfer controller for controlling transfer of data between the buffer memory and the memory bus, and a main control unit for controlling the receiver, the transmitter, the buffer memory, and the memory transfer controller to store a signal which has been received from the input line by the receiver, in the buffer memory, to transfer the signal to the memory bus, to confirm whether data on the memory bus are addressed to a station to which the main control unit belongs, based on the content of the data, and to deliver the data through said transmitter to the output line if the data are addressed to the station.