Abstract: Methods and systems are provided for providing hot swapability of TSIs in a TDM system using FPGA hot swap logic. The hot swap logic is used to provide isolation for the TSIs from a system TDM bus in the TDM system. Moreover, the hot swap logic is capable of improving the performance of the TDM system. For example, the hot swap logic is capable of compensating for clock distortion associated with the distribution of a common clock signal to various TSIs in the TDM system. Additionally, for example, the hot swap logic is capable of compensating for the limitations imposed in conventional TDM systems due to the relatively high clock-to-out times of conventional TSIs.

Abstract: High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.

Abstract: A mobile device, system, and method are disclosed for use in a wireless communication system during the mobile device's transition from a dual mode, in which a packet switched connection and circuit switched connection are used together, to a single mode in which packets are transferred. When the circuit switched connection is released, packet resources are allocated by converting timeslots used for circuit switched connection traffic into timeslots used for packet data traffic. Also included is a new alert signal within an existing message to the mobile device during the circuit switched connection release phase, before completion of the circuit switched connection release phase, in order to inform the mobile device that the converting step will occur after release of the circuit switched connection.

Abstract: A system and a method is disclosed that provides that access to a communications medium that is suitable for allowing HPNA v2-formatted frames in a centralized manner. A list of sessions in enhanced STAs using the communications medium is maintained at a Media Control Station (MC STA). Each enhanced STA gains access to the communications medium in a centralized manner. A message is transmitted from the MC STA to a selected non-MC STA. The transmitted message is transmitted with a highest physical layer priority level available in a first HPNA v2-formatted frame. After the message is received at a non-MC STA, the non-MC STA transmits a reply message to the MC STA in response to the received message that is transmitted at the highest physical layer priority level available in a second HPNA v2-formatted frame.

Abstract: A method and a system is disclosed for providing access to a communications medium that is suitable for allowing use of a plurality of Home Phoneline Network Association (HPNA) v2 frames. A sequence of blocking frames is transmitted on the communications medium, such that each blocking frame has timing to allow an Inter-Frame Gap (IFG) having a duration that is not recognized by an HPNA v2 station (STA) as a duration defined by an HPNA v2 specification for an HPNA IFG. A message is transmitted from a Media Control Station (MC STA) to at least one selected non-Media Control Station when the blocking frames are transmitted. A reply message to the transmitted message is received at the MC STA from a selected non-MC STA when the blocking frames are transmitted.

Abstract: A method and a system is disclosed for providing access to a communications medium that is suitable for allowing use of a plurality of Home Phoneline Network Association (HPNA) v2 frames. A sequence of blocking frames is transmitted on the communications medium, such that each blocking frame has timing to allow an Inter-Frame Gap (IFG) having a duration that is not recognized by an HPNA v2 station (STA) as a duration defined by an HPNA v2 specification for an HPNA IFG. A message is transmitted from a Media Control Station (MC STA) to at least one selected non-Media Control Station when the blocking frames are transmitted. A reply message to the transmitted message is received at the MC STA from a selected non-MC STA when the blocking frames are transmitted.

Abstract: A high capacity switching node comprises a lattice structure of low-latency switch units and a plurality of balanced connectors interfacing electronic edge nodes to diagonal subsets of said switch units. The edge nodes may be collocated with the switch units or remotely located. The switch units may be bufferless, having optical switch-fabrics for example, thus requiring a compound vacancy-matching process. Using switch units each of dimension 64×64, a fast switching node having a dimension of the order of 10,000×10,000 can be constructed. With a typical wavelength-channel capacity of 10 Gb/s, the fast-switching node would scale to a capacity of 100 terabits per second, which is orders of magnitude higher than the capacity of known fast optical switches. A fast-switching optical switch of such scalability significantly reduces network complexity and cost.

Abstract: The invention relates to a communications network with at least two network nodes, between which data may be transmitted via a transmission medium, in which a communications schedule is provided which allots time slots to the network nodes for access to the transmission medium, in which the network nodes each comprise at least one communication controller with a first scheduler for controlling access by the network nodes to the transmission medium according to the communications schedule, in which the communications network comprises at least one bus guardian with a second scheduler for monitoring accesses by the network nodes to the transmission medium according to a monitoring schedule, in which the communication controller comprises means for generating a local, independent clock signal and a global clock signal, which may be influenced by at least one parameter of the communications system and in which the global clock signal is provided both to control the first schedulers of the communication control

Abstract: A beacon slot position control section (205) of a radio communication apparatus constituting a radio network system which detects whether empty beacon slots are present in a beacon period. When an empty beacon slot is present before the period in which the radio communication apparatus transmits a beacon, a movable counter (206) starts counting a specified number of super frames. When the count is completed, the radio communication apparatus transmits a beacon of the radio communication apparatus at the earlier empty beacon slot. Consequently, since the empty beacon slots are eliminated and the beacon period is compacted, even if the number of radio communication apparatuses joining the radio network system fluctuates dynamically, the radio communication apparatus can perform radio communication with high efficiency and less waste of consumed electricity.

Abstract: Technology is disclosed for directing data through a network switch. One version of a network switch employs a mid-plane architecture that allows data to be directed between any link interface and any processing engine. Each time slot of data from an ingress link interface can be separately directed to any ingress processing engine. Each time slot of data from an egress processing engine can be separately directed to any egress link interface that supports the lower level protocol for the data. In one version of the switch, each processing engine in the network switch has the ability to service all of the protocols from the layers of the OSI model that are supported by the switch and not handled on the link interfaces. This allows the switch to allocate processing engine resources, regardless of the protocols employed in the data passing through the switch.

Abstract: A method for performing a synchronous time division switch is provided, and the method includes: dividing, by using a time period for transmitting one byte as a unit, a time period for receiving and sending an Ethernet frame with a constant length by an Ethernet port into input time slots and output time slots, and orderly numbering the input time slots and orderly numbering the output time slots; circularly receiving data via the Ethernet port according to serial numbers of the input time slots; switching the data received at each input time slot to the output time slots corresponding to the input time slot; and circularly outputting the data at the output time slots via the Ethernet port according to serial numbers of the output time slots. An apparatus for performing a synchronous time division switch and an Ethernet switch are also provided. The method for performing a synchronous time division switch can be applied to the Ethernet and can reduce the costs of the synchronous time division switch.

Abstract: A method of time division multiplex switching reduces the implementation area by reducing the area required for both memory storage at each egress port and the multiplexing circuitry required. Ingress and egress processors are implemented to control the storage and selection of data grains to allow for the reduction in the memory and multiplexer areas.

Abstract: A method of providing a data file that defines a modified SONET ring network including at least one sub-tending ring is disclosed. The method comprises identifying a set of low data rate sub-tending ring candidate traffic handling elements within a SONET ring network to be modified. For a first candidate element of the set of low speed sub-tending ring candidate traffic handling elements, the method includes evaluating selected characteristics of a first parent SONET UPSR ring with respect to adding the first candidate element sub-tending SONET ring. Based on a positive evaluation of each of the selected characteristics of the parent SONET ring, the method includes creating a data model that indicates addition of the first and subsequent candidate element sub-tending SONET ring to the parent SONET ring, and providing a data file based on the data model that defines a modified SONET ring network including the parent SONET ring(s) and the sub-tending SONET rings.

Abstract: An apparatus and method includes receiving frames from multiple channels, each frame partitioned into multiple timeslots, reading a timeslot lookup table including an entry that specifies an assignment associated with each timeslot, and storing the data associated with a particular timeslot in a memory location based on the assignment.

Abstract: A bidirectional line switched ring network which enables high-speed operation with improved reliability because of a reduced software processing load is disclosed, and the network includes a plurality of optical transmission equipment sets connected in a ring form, wherein optical transmission equipment provided in a node on the transmission side performs transmission to each lower-order channel by attaching a transmission-side node ID, and, optical transmission equipment provided in a node on the reception side collates the received transmission-side node ID with an expected value of the transmission-side node ID having been set in advance, and when the collation does not match, the optical transmission equipment in the node on the reception side prevents a misconnection in the event of a failure by inserting an alarm indication signal.

Abstract: An apparatus has a cross connection circuit, first switching sections located on the input side of the cross connection circuit to switch a presently-used transmission path and a reserve transmission path, and second switching sections located on the output side of the cross connection circuit to switch the presently-used transmission path and the reserve transmission path and comprises slot sections, first selecting section selectively connecting any one of the slot sections to the input side of the first switching section, second selecting section connecting the output side of the first switching section to the input side of the cross connection circuit, third selecting section selectively connecting the output side of the cross connection circuit to the input side of any of the second switching sections, and fourth selecting section connecting the output side of the second switching section to any one of the slot sections.

Abstract: A channel sharing method and device thereof are disclosed. The method starts by providing a plurality of channels, wherein each of the channels comprises a time interval. A time slot having a width being X times of a maximum value of all the time intervals is provided, wherein C is a positive number. Each of the channels is generated by a permutation of at least one repeat time, which is M times of the width of the time slot, wherein M is an integer larger than 0. A first time slot of the repeat time comprises a signal. A maximum time span of the signals in each channel is the time interval of each channel. All the channels are arranged so that at least one of the signals in each channel is not collided with the signals of other channels in a worst time delay.

Abstract: A user interface for managing connections in a communication network cross connect. The user interface provides for creation, viewing and removing connections in the cross connect. When displaying connections, a granularity may be adjusted to allow for effective viewing of connections having high data rates. A multi-layer display is used having at least a coarse and fine layer with granularities corresponding to a time slot resolution. The user interface may include a search tool for locating connections and/or a protection setup routine to facilitate establish protection connections.

Abstract: A system and method is provided for making highly accurate data propagation delay measurements in a serializer/deserializer (SERDES) integrated circuit. The invention detects a selected special character when the special character is present at the input of a transmit data path of the SERDES integrated circuit. The invention also detects the special character when the special character appears at the output of the transmit data path. The invention then counts the number of clock cycles during which the selected character was in the transmit data path. This provides the data propagation delay of the special character through the transmit data path. The invention also makes data propagation delay measurements for a receive data path of a SERDES integrated circuit.

Abstract: A method of communicating over a network of nodes using a plurality of time slots is disclosed. According to the method, at least one of the plurality of time slots are assigned to a first node. The first node communicates, to neighboring nodes within one hop of the first node, which time slots assigned to the first node are scheduled to be used by the first node. Each neighboring node determines whether it has a need to use more time slots than it has been assigned. Each neighboring node communicates its respective need to the first node. At least one of the neighboring nodes is permitted to use one of the unscheduled time slots.

Abstract: The present invention relates to transmissions and retransmissions in a communications system. It reveals a method and system for backward compatible detection of an introduced channel sub-frame structure particularly well suited for data transmissions. The invention is well suited for a cellular mobile radio communications system, particularly a Universal Mobile Telecommunications System, UMTS.

Abstract: A procedure for sorting a plurality of circuit data flows (7, 8, . . . ) located, according to an initial configuration, in a plurality of sets of slots (space, time, frequency or wavelength) in a transport sub-network, comprising the following steps:—calculating a theoretical configuration in which flows are optimised in terms of occupied band by applying a theoretical flow routing algorithm; on the basis of the theoretical configuration defined above, exchanging the position of the flows in the sub-network slots to obtain an optimal arrangement which minimises the occupied slots; flows whose position corresponds to the position assumed by the flows in the initial position are identified to reduce the number of exchanges; defining and implementing a minimum shift sequence of single flows needed to shift each single flow from an initial position occupied in the initial flow configuration to a final position corresponding to the position assumed by the flow in the optimal slot set arrangement.

Abstract: A circuit and method are presented for signal processing and routing of digital voice telephony signals, using a specialized high-density integrated circuit voice processor. The voice processor performs several essential functions required for telephony processing, including echo cancellation, protocol conversion, and dynamic range compression/expansion. These functions are traditionally performed by multiple circuits or modules. By combining these capabilities in a single device, power and circuit board area requirements are reduced. The embodiment of the circuit and method disclosed herein include novel implementations of a time-slot interchange circuit and a telephony signaling circuit. Both of these circuits are designed to minimize demands on the signal processing engines incorporated within the voice processor, and account for very little of the on-chip circuitry.

Abstract: A method detects a defective module in a signal processing apparatus having modules capable of communicating with each other. The method includes the step of incrementing the number of occurrences of communication failure for each module relevant to communication where a communication failure has occurred, upon occurrence of the communication failure, while monitoring communications among the modules. The method further includes the step of detecting a defective module based on the number occurrences of communication failure for each module incremented in the step of incrementing the number of occurrences of communication failure.

Abstract: An apparatus for generating a time slot in a home network system using home PNA 2.0 protocol and a method thereof are provided.

Abstract: A wireless data communication unit (700) shares a data communication resource with a plurality of other data communication units. The wireless data communication unit (700) receives channel status information from a wireless serving communication unit on an outbound channel (100) and transmits data to the wireless serving communication unit on an inbound channel. The wireless communication unit includes a processor (708) for monitoring channel status symbols inserted on the outbound channel, such that the processor (708) regulates time intervals between successive data transmissions (480) on the inbound channel dependent upon the monitored channel status symbols inserted on the outbound channel. A method of sharing a communication resource is also described.

Abstract: A timeslot interchange switch has a three stage pipelined construction. A cross-connect stage identifies egress timeslots for which there is a corresponding data source. The cross connect stage has a set of flags which indicate whether or not there is a data source for each of a plurality of egress timeslots. The cross connect stage takes the flags in groups. If one or more flags in a group indicates an egress timeslot has a corresponding data source then information identifying the egress timeslot is passed to a connection scheduler via a FIFO. The connection scheduler looks up the data source for each the egress timeslot.

Abstract: Time-slot interchange (TSI) switches include an input buffer that is configured to receive at least first and second groups of serial input data streams and an output driver that is configured to generate at least first and second groups of serial output data streams. A control circuit is also provided. This control circuit is electrically coupled to the input buffer and output driver. The control circuit is configured to provide programmable group-based output drive enable control to the at least first and second groups of serial output data streams that is independent of per-channel output stream programming. This per-channel output stream programming is defined by mode bits within the switch's connection memory.

Abstract: Time-slot interchange (TSI) switches and a pipelined data memory address generation circuit are provided. The TSI switches and the pipelined data memory address generation circuit include a first pipeline stage that reads data from a connection memory. A second pipeline stage compares the data read from the connection memory to provide a bank selection value. Optionally, a third pipeline stage reads data from a data memory based on the bank selection value and the data read from connection memory. The timing of the pipeline stages may be adjusted such that the duration of the first pipeline stage is extended and the duration of the second pipeline stage shortened.

Abstract: A switch system including a plurality of input ports and a plurality of output ports for transferring data from one of the input ports to one of the output ports, and a plurality of memory devices is disclosed. The memory devices include a first memory bank configured for data being written to the first memory bank while data is read from the first memory bank at a timeslot and a second memory bank, which is smaller than the first memory bank and configured for writing the data read from the first memory bank to the second memory bank and reading data from the second memory bank. The system further includes an address comparer configured to compare a write address of the first memory bank with a read address of the first memory bank and select data for output from the first memory bank if the write address is smaller than the read address and select data from the second memory bank if the read address is equal to or smaller than the write address.

Abstract: An integrated services digital network private branch exchange, which is capable of automatically choosing a synchronization clock source. The integrated services digital network private branch exchange comprises a plurality of trunk chips, a plurality of subscribe chips, and a plurality of priority selection circuits. Wherein, the trunk chips connect to the network terminal via the trunk interface, and then connect to the central office via the network terminal to receive the frame synchronization clock output signal and the data clock output signal. Whereas, the subscribe chips connect to the terminal equipment via the subscribe interface. The priority selection circuits that are connected to each other in a daisy chain circuit manner are connected to the trunk chips to send out the frame synchronization clock output signal and the data clock output signal.

Abstract: A signal router routes N inputs to M outputs. All inputs signals are ultimately applied to a data buss by spreading across multiple buss lines and time multiplexing. The data are read from the buss and written in identical images to K random access memories. The memories are addressed and read according to a different schedule for each of K output signals that are ultimately demultiplexed to M outputs. As each RAM image is read, another RAM image is written and vice versa. Since each RAM image contains the same data, the generation of signals from each RAM to supply each of the respective K output signals can be done at a rate that is substantially more independent of the input, buss, or RAM write operations than prior art techniques permit.

Abstract: A processor is programmed to reduce a problem of adding a new connection to a time-space-time (TST) switch of a communication network into a problem of graph theory, and to solve the problem using a heuristic instead of an exact algorithm. A solution, if provided by the heuristic, is used to rearrange the connections in the TST switch. Several embodiments of such a programmed processor reduce a connection rearrangement problem of a TST switch into any one of the NP-complete problems (such as the vertex coloring problem or the boolean satisfiability (SAT) problem). In some such embodiments, the processor is programmed based on the Brélaz heuristic to find a solution to the vertex coloring problem. In other embodiments, other heuristics, such as a genetic algorithm, may be used.

Abstract: A system and method for prioritizing the transmission of packets in a wireless local area network. A station selects a packet from local priority queuing and identifies the priority bits of the packet. The station declares the priority of the selected packet based on the binary value of the priority bits. If the station detects that another station has selected a packet with a higher priority, then the station ceases to contend for transmission during the current transmission cycle.

Abstract: A scalable multi-service node system uses a stackplane architecture which allows the transport capacity to be flexibly expanded while providing first traffic mode and second traffic mode link channels. The primary channel bank is provided, and one or more secondary channel banks are connected to the primary channel bank through the stackplane first traffic mode and second traffic mode links. The system is expandable by adding secondary channel banks to the system through the stackplane links.

Abstract: A router device has a plurality of ingress line interface cards (LICs), a plurality of egress LIC's, a backplane and a controller. Transmission of signals from the ingress LICs to the controller, and from the controller to each of the ingress and egress LICs takes place across the backplane. Each ingress LIC is provided with a dedicated timeslot in which it can send information to the controller via connection. Information is sent in a slice within the dedicated timeslot and each egress LIC ignores data sent by a given ingress LIC within the timeslot assigned to said ingress LIC. A similar system is used for transmission of communications from the controller to the LICs. It is thus possible to avoid provision of additional, dedicated communications paths between the LICs (ingress and egress) and the controller.

Abstract: A scalable digital loop carrier system uses a stackplane architecture which allows the transport capacity of the scalable digital loop carrier system to be flexibly expanded while providing time division multiplex (TDM) and asynchronous transfer mode (ATM) data link channels. The primary channel bank is provided in the scalable digital loop carrier system, and one or more secondary channel banks are connected to the primary channel bank through the stackplane ATM and TDM data links. The scalable digital loop carrier system is expandable by adding secondary channel banks to the system through the stackplane TDM and ATM data links.

Abstract: A multi-mode bi-directional communications device including a diplexer having a high-pass filter, a first low-pass filter, and a second low-pass filter. Downstream processing circuitry is coupled to the high-pass filter, and upstream processing circuitry is selectively coupled to the first low-pass filter and the second low-pass filter in response to an indicium of a desired spectral region.

Abstract: An arrangement for capturing data from a data stream of a predetermined data transfer rate using a flip-flop, comprises a symmetrical multi-phase clock generator that is adapted to be locked to a reference clock which in turn is adapted to generate a reference clock signal at the data transfer rate or at a fraction thereof. The multi-phase clock generator is adapted to generate “n” clock signals mutually shifted in phase 360°/n from each other. A selector is connected to the clock generator to receive the n clock signals and selects one of these n clock signals as the system clock signal in response to a control signal from a clock phase counter. The clock phase counter is controlled to count up or down in response to the phase of the system clock signal when a predetermined number of data transitions have occurred in the data stream. The flip-flop is controlled by the opposite phase of the system clock signal to capture the data from the data stream.

Abstract: A cordless digital telephone system which allows hierarchical call control in a cordless phone system is provided. Based upon a priority level associated with the identified phone number, a call controller unit directs the call to a selected one of a plurality of mobile units in communication with the base station, or a group of mobile units, or in some cases, at a highest priority level, broadcasts the call to all mobile units. In those cases where the phone number is not identifiable as being associated with a particular priority, then a lowest priority is set for that call in which case a predefined message is sent to the caller and the call is dropped. In this way, since in a broadcast mode a user does not have the chance to prevent a ring an unwanted call can be diverted based upon a priority level such as, for example, a “Do not disturb” priority level for calls and broadcasts.

Abstract: In a mobile communication system, a subscriber station MS11 changes the time slot for receiving a frame from a base station 1 in accordance with TS change information sent from the base station, while the base station 1 changes the time slot for receiving a frame from the subscriber station MS11 in accordance with TS change information sent from the subscriber station.

Abstract: A time slot interchanger (TSI) for a telecommunications node includes an exchange memory and a controller. The exchange memory includes a plurality of exchange memory slots. Each exchange memory slot is sized to store a traffic channel and includes a plurality of discretely addressable fields sized to store a sub-channel. The controller is operable in response to predefined switching instructions to write a sub-channel received in a first traffic channel to a first field in a memory slot and to write a sub-channel received in a second traffic channel to a second field in the memory slot.

Abstract: In a multi-mode scheduler including a N×kM scheduler for adjusting data transmission between N-pieces of input interface sections and kM-pieces of output interface sections, the multi-mode scheduler, k-pieces of N×M schedulers to be the N×kM scheduler, and (k?1)-pieces of selection circuits for switching allocated output port information input from an outside of the N×kM scheduler and information from a N×M scheduler at front step, so as to be input to the N×M scheduler as allocated output port information, and two operations are set freely with a switching operation of the selection circuits. As a result, it is possible to provide a general scheduler.

Abstract: A method for testing a transmission system is disclosed. The method comprises receiving a time division multiplexed (TDM) stream on an input of the transmission system. The method also comprises inserting test data in one or more of the plurality unused fields of the TDM stream. Additionally, the method comprises transferring the TDM stream along a plurality of components of the transmission system and comparing the test data against the transferred test data.

Abstract: The invention describes a method and a system for fast and economic synchronization of multiframe structures, such as PDH multiframe binary signals, by detecting a periodic binary signature in a binary signal using one final state machine (FSM) comprising a logical scheme interconnected with a memory block having a plurality of independent memory cells with serial numbers for cyclically connecting thereof to the logical scheme; the signature is detected by applying the signal to the FSM while synchronously switching the cells to the FSM. The arrangement is such that when the predetermined periodic binary signature occurs in the signal, one of the cells will reach its predetermined terminal state.

Abstract: A method and apparatus for sharing storage in a cross-connect. According to one embodiment of the invention, a cross-connect includes a number of sets of data input lines and a number of matrices. Each of the sets of data input lines is to be coupled to a different line card. Each of the matrices is coupled to every one of the sets of data input lines. In addition, each of the matrices has a set of data output lines, where the set of data input lines of each of the matrices is to be coupled to a different one of the line cards.

Abstract: For achieving elimination of unfairness between ports, reserved output port information transferred between respective modules is input to switch out of the module to vary destination of output. The module and the switch operate in synchronism with the frame for which the connection grant process of a plurality of time slot is performed to vary connection topology so that all connection topology appear. By variation of connection topology, variation combination of adjacent port appear to shuffle preference for the input port which is otherwise held fixed for resolving unfairness relating to reservation chance of the input port.

Abstract: A time/space switching component is provided with multiple functionality that includes a time switching unit, of a space switching unit of a data channel sequence correction unit and of a control unit. As a result of corresponding mode selection, the different functionalities for a switching network are obtained with a single component, resulting in a significant reduction in an overall expenditure for development and manufacture.

Abstract: A technique for performing a time slot interchange in a processor. The TSI process is surrounded by a multiplexing/demultiplexing circuit for converting a plurality of PCM highways into a single input serial data stream. The mux/demux circuit includes elastic stores to align frames and shift resisters to mux/demux with a minimum of delay. The TSI processor includes an input and an output buffered series port, a pair of input buffers, one to receive even-numbered frames from the PCM highways and one to receive odd-numbered frames, and an output buffer. Data is read from the appropriate input buffer in a non-sequential fashion as commanded by the processor in accordance with information stored in connection arrays (address buffers). The data is then written to the output buffer sequentially. The timing of the reading and writing steps is optimized relative to free running buffered serial port pointers for each BSP to reduce the frame delay.

Abstract: An interworking unit (14) for providing an interface between a digital communication network (12) and a public switched telephone network (PSTN) (16) includes a de-vocoder (30), a protocol termination unit (32), and a signal combiner (34) for processing signals being transferred from the digital network (12) to the PSTN (16). A digital communication signal received by the interworking unit (14) from the digital network (12) is processed by both the de-vocoder (30) and the protocol termination unit (32). The outputs of the de-vocoder (30) and the protocol termination unit (32) are then combined into a uniquely formatted signal that is then delivered into the PSTN (12). Similar functionality is also provided for processing signals in the reverse direction. The interworking unit 14 is capable of processing signals traversing the interface between the networks (12, 16) without a priori knowledge of the signal type being processed.