Abstract: A telecommunications gateway allows packets to be sent over a TDM system and allows TDM traffic to be sent over a packet switched network. The gateway is a universal port that includes a plurality of Digital Signal Processors (DSPs) that are controlled by software. The controlling software determines what single function the DSP will perform over multiple channels. Each DSP handles multiple channels, however, each DSP is restricted such that all of its multiple channels are permitted to handle the telecommunications traffic according to one signaling protocol.

Abstract: A telecommunications switch includes a plurality of digital signal processing modules resident on a communications services card, wherein each module includes its own time slot interchange (TSI). Significantly, this allows each digital signal processing module to simultaneously receive all information transmitted from the line cards. In addition, since each digital signal processing module includes its own dedicated TSI and each of these TSIs is connected in parallel to the same TDM bus, one or more TSIs may simultaneously output data onto the TDM bus during a time slot. Advantageously, this allows multiple TSIs to be assigned to the same transmit time slot and mux transmit time slots at the bit level. For example, if a first TSI on the digital signal processing module needs only three bits of an eight bit time slot, and a second TSI needs five or less bits, then both TSIs can be assigned to transmit during the same time slot.

Abstract: The invention relates to implementing switching in a switch in a digital telecommunications system. N incoming signals are introduced to the switch, each comprising successive one-bit time slots that form successive frames each comprising K time slots. The contents of the time slots for the incoming signals are stored in a memory at a memory location determined by a write address in such a way that a word having the width of at least one bit is stored at one memory location. One word at a time is read out from the memory, wherefrom the desired bit is selected for the outbound signal from the switch. To optimize the size and power consumption of the switch, the incoming signals are distributed to X multiplexers (A1 . . . Ax), each interleaving the incoming signals thereto into a single serial output signal (IN1 . . .

Abstract: The invention relates to a method and device for switching user data, belonging to a connection, between different time slots in a switch or a switch stage such that sequence and frame integrity are preserved. According to the invention, an efficient algorithm is utilized for determining distribution information, in form of storage positions in one or more control memories in the switch. User data is caused to be switched, according to this distribution information from the algorithm, such that these user data maintain the same reciprocal time order through the switch or switch stage. The distribution information determined by the algorithm assures sequence integrity and at the same time minimizes the delay of user data through the switch and/or switch stage. The algorithm also generates control information in form of delay values for delaying some user data such that data belonging to incoming time slots in one and the same frame are assigned to outgoing time slots in the same frame.

Abstract: A time slot interchange having a data channel memory, a channel circuit, having a write address output, the write address output connected to the data channel memory, a signal processing circuit, having a channel input coupled to the data channel memory, a gain input, and an output coupled to the time division multiplexed signal output port, and a connection memory, including a unique read channel field comprising a read address portion and a gain value portion for each data channel to be output by the time slot interchange network. The connection memory has an input connected to the write address output of the channel circuit, a read address output connected to the data channel memory, and a gain value output connected to the gain input of the signal processing circuit.

Abstract: A telecommunications terminal is provided that is compatible with, and capable of connecting to, a cellular switch. Also provided are a protocol engine programmed to convert signals used in the terminal to a protocol required by the cellular switch and a service element programmed to generate wireline services for wireline subscribers.

Abstract: An isochronous bus may includes a data signal, a data valid signal, a frame synch signal and a clock signal. The bandwidth of the data signal is partitioned into a plurality of frames. The frame rate may be selected based upon the sample rate of one of the isochronous devices connected to the isochronous bus or maybe some divisor of the data rate of the isochronous bus. Each frame is partitioned into a plurality of data channels. Each data channel transmits data from an isochronous device. A number of bit time slots are allocated to each data channel. The number of bit time slots allocated to each data channel varies based upon the sample rate of the device corresponding to the data channel. In one embodiment, each data channel is allocated more bit time slots than the nominal samples of its corresponding device. In this manner, any drift of the sample clock may be accommodated. A data valid signal is transmitted synchronous to the data signal and the clock signal.

Abstract: An isochronous bus may includes a data signal, a data valid signal, a frame synch signal and a clock signal. The bandwidth of the data signal is partitioned into a plurality of frames. The frame rate may be selected based upon the sample rate of one of the isochronous devices connected to the isochronous bus or maybe some divisor of the data rate of the isochronous bus. Each frame is partitioned into a plurality of data channels. Each data channel transmits data from an isochronous device. A number of bit time slots are allocated to each data channel. The number of bit time slots allocated to each data channel varies based upon the sample rate of the device corresponding to the data channel. In one embodiment, each data channel is allocated more bit time slots than the nominal samples of its corresponding device. In this manner, any drift of the sample clock may be accommodated. A data valid signal is transmitted synchronous to the data signal and the clock signal.

Abstract: A method and apparatus for accessing data of a telecommunications interface control RAM to meet the two different requirements of the two types of devices accessing the control RAM. Data for output ports are typically aligned such that time-slot 0 for each port leaves the network at the same time. The hardware therefore requests that the control RAM be organized such that the first N locations correspond to time-slot 0 of all output ports, the next N locations to time-slot 1 of all ports, and so on with the final N locations corresponding to the last time-slot of all ports. The software addressing under processor control, on the other hand, uses data structure groups which are a function of the communication ports.

Abstract: A switching network having a plurality of independent switching units with each switching unit switching one bit of each group of data from external data links through a telecommunication switching system. The plurality of switching units is greater than the number of bits that must be switched which increases reliability. This allows the extra switching units to be utilized as replacement switching units should a switching unit actively switching a bit of the incoming data be disabled. The switching units provide full broadcast switching of data from any individual external link to any number of the other external links. A plurality of port units terminate the external links, and a plurality of control paths are provide from a central controller to each of the port units. Each of the switching units communicated one of the control paths. For control, each port unit determines a set of control information that is identical from a majority of the control paths.

Abstract: Apparatus for switching full-rate (e.g., 64 kilobit per second) signals and composite signals comprising a plurality of sub-rate signals (e.g., 32 kilobit per second sub-rate signal). The apparatus includes a unit for compressing selected ones of a plurality of full rate signals into a smaller plurality of full rate single and composite signals, and apparatus for expanding composite signals into full rate signals. Advantageously, during periods of heavy load, the switching network fabric of a switching system can carry more calls, and more traffic can be carried between switches equipped for sub-rate switching.

Abstract: An enhanced form of time switch. Serial bit streams received in input buffers are stored in parallel under program control in the cache of a pipe lined microprocessor. The microprocessor, under program control, then rearranges the received time slots and feeds them in parallel to output buffers from which serial bit streams are generated. Advantageously, program control is used to flexibly control the various functions of different time switches without requiring a change in the hardware.

Abstract: A combined signalling and PCM cross-connect and packet assembly/disassembly engine includes a cross-connect memory, wherein the memory advantageously includes both a subscriber PCM channel memory that cross-connects bus side PCM channels to optical fiber timeslots, and a separate signalling memory that cross-connects associated signalling data channels to optical fiber timeslots. In particular, the PCM and signalling data memories are substantially the same size and each signalling data channel is mapped to an address in the signalling memory that corresponds to the PCM memory address of the associated PCM channel. Cross-connect information used for the PCM channels is also used to cross-connect the associated signalling channels. Cross-connect and packet engine functions are combined, thereby eliminating the need for a separate buffer to accommodate differences in transmission rates between them.

Abstract: Provided is a cross connection system for time-division multiplexed signals, upon detection of deterioration in quality, performs line setting to easily switch to a line having another directional orientation.

Abstract: An ATM switch includes a multi-destination delivery number counter. The counter stores a multi-destination delivery number of each inputted cell according to destination information in the cell correlating the multi-destination delivery number with an idle address where the cell is stored, on every writing of a cell into an idle address of the shared buffer, and decrements the multi-destination delivery number of the cell on every reading of the cell from the shared buffer. The multi-destination delivery numbers of the cells are utilized for management of switching output of the cells from the shared buffer. The multi-destination delivery number counter detects addressing errors to the shared buffer according to the multi-destination delivery numbers, on every inputting or outputting of the cells. According to the ATM switch, both miniaturization of circuit scale of the ATM switch and improvement of reliability of the ATM switch are made possible.

Abstract: In an apparatus and a method for interfacing a private exchange to an ISDN, the apparatus controls intralayer and interlayer entity communications to interface the private exchange to the ISDN. The apparatus is disposed in a universal card slot of a subscriber shelf of the private exchange in the form of a card to accommodate an ISDN terminal in the private exchange or connect the private exchange to an ISDN public network, thereby enabling voice and data communications.

Abstract: The invention comprises a time slot interchanger and method for multiplexing ISDN D-channel signals into multiplexed signals in a digital communications terminal. The method comprises receiving a frame of communication signals wherein some of the communication signals represent ISDN D-channel signals wherein each ISDN D-channel signal is represented by a first number of data bits and a second number of other bits. A first copy of the frame of communication signals is stored in a first memory while a second copy of the frame of communication signals is stored in a second memory during a first frame period. During a second frame period, at least some of the stored communication signals are retrieved from the first memory and at least some of the stored communication signals are retrieved from the second memory. Multiplexed signals are then assembled wherein at least one multiplexed signal comprises a multiplexed combination of the data bits of ISDN D-channel signals retrieved from the first and second memories.

Abstract: A plurality of voice-over-ATM modules operate in parallel and each processes at least one type of AAL. Interface circuitry and contention circuitry allow the parallel modules to interact. The result is an interworking between ATM streams and different types of equipment.

Abstract: A multiple bank memory device is described which can be tested by accessing the multiple memory banks simultaneously. The memory includes a test mode trigger which initiates a test which writes and reads from memory cells located in different memory banks. Error detection circuitry evaluates data read from different memory banks and determines if a defect is present in the memory cells. Different test patterns and techniques are described for identifying defective memories.

Abstract: A switch fabric is provided which comprises a shared memory, a number of switch fabric ports, and a switch fabric data controller. The switch fabric data controller routes blocks of data received at one switch fabric port to one or more other switch fabric ports and writes and reads data to and from, respectively, the shared memory. The switch fabric data controller preferentially routes a block of data from the one switch fabric port to the one or more other switch fabric ports without writing the block of data into the shared memory if the one or more other desired switch fabric ports are free or become free within a predetermined period, and otherwise writes the block of data into the shared memory for temporary storage if the one or more other switch fabric ports are busy. In this manner, the switch fabric facilitates "cut-through" of blocks of data across a switch without the need to write the blocks of data to a shared memory, thereby reducing latency.

Abstract: An enhanced Time Slot Interchange (TSI) facility, in addition to serving synchronous channels of communication, decomposes and composes asynchronous data cells to provide real-time communication among and between both synchronous and asynchronous channels served by a network access switch. An asynchronous cell comprises a 5 byte header and a 48 byte payload. The payload comprises voice samples from a temporarily defined set of DSO facilities and/or data from a variety of data facilities. Time slots of the TSI are temporarily assigned to the payload bytes of each incoming asynchronous cell; the payload bytes are stored in memory locations corresponding to those time slots; and the stored data is read out during time slots assigned to the destination channels of communication. The TSI comprises three data rams to accommodate for frame to frame jitter in the time of arrival of payload samples.

Abstract: In the method for assignment of time slots to a multichannel link, the incoming and outgoing time slots are each provided with an identification which unambiguously defines the sequence. At least one auxiliary variable is determined which, for a given time, relates to the difference between a number of outgoing time slots and incoming time slots for the multichannel link within the respective frames. The method and the switching device ensure a multichannel link with guaranteed bit integrity.

Abstract: A digital switch array, includes a serial input bus providing a plurality of input streams, each defining a plurality of time division multiplexed input channels, a serial output bus providing a plurality of output streams, each defining a plurality of time division multiplexed output channels, and an array of digital switches arranged in rows and columns. Each row is connected to a respective group of input streams and each column is connected to a respective group of output streams. The digital switches are capable of performing timeslot interchange between any input and any output channel. Each digital switch includes an enabling device for each output timeslot so that when the enabling device is enabled the associated output timeslot is driven, and at least first and second enabling inputs which when simultaneously activated cause the enabling device to become enabled. An array of activation lines are arranged in rows and columns.

Abstract: The invention comprises a time slot interchanger and method for multiplexing ISDN D-channel signals into multiplexed signals in a digital communications terminal. One method comprises receiving a frame of communication signals wherein some of the communication signals represent ISDN D-channel signals wherein each ISDN D-channel signal is represented by a first number of data bits and a second number of other bits. The first number of data bits are stored in one of four memories--a first memory, second memory, third memory or fourth memory. The data bits are stored during a first frame period. Multiplexed signals are then assembled wherein a multiplexed signal comprises a multiplexed combination of the data bits of ISDN D-channel signals retrieved from the frame of communications signals.

Abstract: The invention comprises a time slot interchanger and method for multiplexing ISDN D-channel signals into multiplexed signals in a digital communications terminal. The method comprises receiving a frame of communication signals wherein some of the communication signals represent ISDN D-channel signals. The frame of communication signals is stored in memory during a first frame period. During a second frame period, at least some of the stored communication signals are retrieved from memory. Multiplexed signals are assembled wherein each multiplexed signal comprises a multiplexed combination of the data bits of ISDN D-channel signals retrieved from memory. The multiplexed signals are then output during a second frame period.

Abstract: The invention comprises a time slot interchanger and method for multiplexing ISDN D-channel signals into multiplexed signals in a digital communications terminal. One method comprises receiving a frame of communication signals wherein some of the communication signals represent ISDN D-channel signals wherein each ISDN D-channel signal is represented by a first number of data bits and a second number of other bits. A copy of the frame of communication signals is stored in each of a first, second, third and fourth memory during a first frame period. At least some of the stored communication signals are retrieved from the first, second, third, and fourth memories during a second frame period. Multiplexed signals are then assembled wherein at least one multiplexed signal comprises a multiplexed combination of the data bits of ISDN D-channel signals retrieved from at least two of the first, second, third, and fourth memories.

Abstract: An interface device is provided which may be used to perform rate adaptation and time slot assignment, in either the transmit or receive directions, in a multiplexing unit for interfacing a high rate optical carrier line to a plurality of lower rate information carrier lines. The high rate optical carrier line may be a SONET or SDH carrier line. The interface device according to the present invention may be operationally configured to provide data rate adaptation and time slot assignment between an optical carrier line operating at an OC-12 rate with lower rate lines operating according to OC-3, OC-1, DS-3, or DS-1 protocols, or even virtual channels. A plurality of identical interface devices may be cascaded together and used to perform interface support for various channels operating at various rates, merely by manipulating the operational configuration of the individual interface devices in the cascade.

Abstract: An interface device serving as a bridge between a telephone-based bus with a plurality of TDM channels and a high speed data network to permit mixed data, voice, and video signals to be exchanged between the telephone bus and the data network, comprises a serial port for connection to the telephone bus; a parallel port for connection to the high speed data network; a bidirectional serial-to-parallel/parallel-to-serial converter connected to the serial port; and a rate converter circuit between the bidirectional converter and said parallel port, the rate converter circuit including a time-slot interchange device to permit rate adaptation with constant throughput delay and switching between the TDM channels.

Abstract: A telecommunications apparatus for transporting ATM cells having either of isochronous units of payload data and asynchronous units of payload data, between receiving and transmitting ports includes a buffer for asynchronously queuing units of payload data received from the receiving ports and for subsequently transmitting the queued units of payload data in a time division multiplex data stream toward the transmitting ports. A timeslot interchanger is used to reorder a time defined sequence of isochronous units of payload data from the first data stream into a second time defined sequence of isochronous units of payload data in a second TDM data stream. An outgoing TDM data stream is assembled by transferring the first data stream into the outgoing data stream while substituting each payload occurrence of isochronous units from the second TDM data stream, into corresponding TDM locations in the outgoing data stream.

Abstract: A processor (100, 500) that executes applications (99) which require access to time slots of a time-division multiplexed (TDM) communications medium (110) uses spare processing capacity and/or spare hardware of the processor to interface to the TDM medium and to implement a time-slot interchange (TSI) function in a simple and low-cost manner. The processor has a control store (104, 300, 504, 604) that stores a bit map of the time slots of the TDM medium. The bit map is either examined by the processor during each time slot (FIG. 2) to determine, or is used by external circuitry (301, 302) or spare internal circuitry (511) of the processor to generate interrupts (406) or DMA requests that indicate to the processor or to a host interface (510) of the processor, which time slots to access. The processor has a read buffer (105, 505) and a write buffer (106, 506) for effecting data transfers between the TDM medium and the applications.

Abstract: A port circuit (108) for a time-division multiplexed (TDM) switching system (100) is designed to effect sub-time-slot operation without external support, as well as to effect conventional, time-slot operation. A clock-frequency multiplier, such as a frequency-multiplexed phase-lock loop (PLL 202), and a multiplier-driven sub-time-slot operation circuit, such as a PLL-driven finite state machine (203), are incorporated into the port circuit. The clock-frequency multiplier and the sub-time-slot operation circuit generate all the additional control signals that are necessary to define sub-time slots and to effect multiple information transfers in a single time slot. The port circuit engages in conventional time-slot transfers with conventional port circuits, whereby it is compatible therewith, and engages in sub-time-slot transfers with other sub-time-slot enabled port circuits, whereby it increases the transfer throughput of the TDM switching fabric.

Abstract: A method or apparatus for offering multiple switch access to selected lines and trunks of a multiple telecommunications switch complex. The selected lines and trunks are connected to peripheral units whose outputs are distributed by a network to a group of switches. The switches are interconnected by a second network. Advantageously, the selected lines can be served by several switches so that the failure of one switch does not deprive these lines of service. Advantageously, the two networks and the group of switches form a giant switch having high reliability.

Abstract: A universal tributary interface group approach for SONET multiplex equipment in which the shelf is partitioned into regions and each region can be provisioned to support different service types. The universal tributary group system includes an equipment shelf having a backplane. The equipment shelf is partitioned into regions called tributary groups which are each capable of accepting tributary units having compatible bus widths and clock rates. Removable card guides may be inserted into the tributary group spaces so that tributary interface units of different heights and widths may be placed in the tributary group spaces. Additionally, a plurality of bus segments run along the backplane to electrically connect a time slot interchange unit to card slots in the tributary groups. Each of the bus segments is capable of being provisioned to use a bus rate compatible with the data requirements of the tributary group it services.

Abstract: A data multiplexing system which includes a plurality of data multiplexing buses through which a plurality of low-speed digital signals are collected into, and distributed from, a multiplexer/demultiplxer. In a data multiplexing mode, the low-speed digital signals entered from a plurality of low-speed transmission lines have their signal format converted by respectively corresponding low-speed interface circuits, and the resulting signals are multiplexed in time slots designated within a multiplexed signal of primary level on the up bus line of the corresponding data multiplexing bus. The high-speed multiplexer multiplexes the collected signals up to a predetermined signal level and sends the resulting secondary multiplexed signal to a high-speed interface module having a high-speed transmission line interface. The high-speed interface module converts the received secondary multiplexed signal and sends the resulting signal to the high-speed transmission line.

Abstract: A terminal for interconnecting a large number of subscriber telephone circuits with a large bandwidth fiber optic transmission system. A system backplane includes a large number of connectors that each can receive a subscriber printed circuit card which is connectable to subscriber telephone equipment. Each connector is connected to several separate communication buses that each carry a number of communication channels from the fiber optic system, but a primary bus position of each connector is connected to a single, unique bus. This allows each card to have a dedicated bus for up to the number of communication channels of the bus, with additional channel capacity available from primary buses of other connectors, if necessary.

Abstract: To reduce memory space of a speech path memory in a switching circuit for a multi-slot time division signal, only data in effective time slots of an input signal are stored one after another in a speech path memory to be switched into different time slot of an output signal in the present invention. Recording relations between time slot number of the input signal where data to be switched are carried and an address of the speech path memory where the data are stored, a conversion table converts switching control data indicating each time slot number of the input signal of data to be switched into each time slots of the output signal to address data of the speech path memory where the data to be switched are stored, and generates an idle bit pattern inserting signal when the data to be switched are not stored.

Abstract: A high-speed signal input to and output from a high-speed optical interface part connected to an optical fiber transmission line is switched to different lines such that the switching is conducted by cross connect parts on an arbitrary basis. The high-speed signal is separated so as to obtain the low-speed signal. The low-speed signal output from the cross connect parts is separated so as to obtain the subscriber signal by signal terminal parts. Call connections are conducted for each subscriber by a time slot interchange part, whereupon a subscriber interface part performs analog-to-digital and digital-to-analog conversion so as to serve as an interface for a subscriber.

Abstract: A plurality of data streams time-division multiplexed into a single stream are concurrently processed. State vectors characteristic of each data stream are stored in unique read-write memory locations having known addresses. During an initial clock cycle the next sequential data word is received from the single data stream and an input state vector characteristic of the data stream in which the received data originated is retrieved from the memory. The data word and the input state vector are passed to state machine logic which, during one or more intermediate clock cycles, processes the data word and the input state vector to produce an output data word and an output state vector. During a final clock cycle the output data word is transferred to an outgoing data stream and the output state vector is stored in the memory location from which the input state vector was retrieved.

Abstract: A time-slot interchanger includes first and second time switches and a space switch installed between the first and second time switches. The first time switch includes a first part for supplying data, which is produced by adding a blank region to input data supplied to the first time switch, in n systems (n is an integer), in parallel to the space switch. And the second time switch includes a second part for supplying output data, which is produced by removing the blank region from data received in the n systems and in parallel from the space switch.

Abstract: A user-programmable telephone switch which resides within a commercially available personal computer. The switch is controllable by either the personal computer's microprocessor or a separate, external host connected to an interface provided within the switch. The switch includes a CPU/matrix card that contains a time slot interchange and a CPU running under a real time operating system. The CPU/matrix card controls the overall operation of the switch in accordance with messages received from the operative host. In general, those tasks or functions which must be performed in real time are the responsibility of the switch, as opposed to the internal or external host. Within the switch, certain tasks or functions may be delegated by the CPU/matrix card to intelligent line cards which contain their own microprocessors having substantial call processing capability.

Abstract: An arrangement for controlling a large time slot interchange (TSI) unit. The TSI unit is a single stage unit for interconnecting any incoming time slot with any outgoing time slot. No blockage is incurred in such a single stage switch. A plurality of module processors is used each for controlling a group of TSI slices, the size of the group being selected to match the capabilities of the module processor. The module processors communicate with each other in order to cooperate in setting up connections through the TSI unit. Each module processor processes terminating, originating, incoming or outgoing processes for calls connected to the terminals served by the module processor. Advantageously, a large non-blocking TSI unit is made available for serving a large switching system without incurring blockage.

Abstract: An add-drop multiplexer having a plurality of OC--N and OC--M (M <N) interfaces and a drop and insertion unit. The drop and insertion unit includes a plurality of switch units corresponding to the second stage switch and a plurality of first and third stage time slot interchange circuits provided on the side of a plurality of low speed side interfaces. A multiplexing signal can be linked between low speed side transmission lines by using simple circuits.

Abstract: A communications network, having an SDH transmission line with four main channels, is provided, at four different tributary connection nodes, with respective add/drop multiplexer units for permitting interchange of information signals between the main channels and tributary channels of the network connected to respective tributary ports. Each add/drop multiplexer unit includes a time slot interchange unit through which a pair of the main channels pass but which bypass the other two main channels. Because different pairs of the main channels pass through the different time slot interchange units, signal interchange is possible between any one of the main channels and any one of the tributary channels, even though the time slot interchange unit at each node need not have an interchange capability sufficient to enable signal interchange between each tributary channel at the node concerned and any one of the main channels. The add/drop multiplexer units can be located together at a single node, if required.