Time Slot Interchange, Per Se Patents (Class 370/376)
  • Patent number: 6870839
    Abstract: A cross-connect is provided which uses “mask” and “rotate” parameters, rather than “source” and “destination” parameters. In a first step (1300), a word representing a full time slot of data is read from a desired source time slot. In a following step (1302), the aforementioned word is masked to enable only the desired bits which are to be output. Thereafter, in a step (1304), the masked word is rotated to ensure that the target bits are in the correct bit positions for a target time slot, to which the masked and rotated word is written in a step (1306). This cross-connection method supports efficient use of cross-connection control memory, and of buffer RAM memory.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: March 22, 2005
    Assignee: Nokia Corporation
    Inventor: Pasi Vaisanen
  • Patent number: 6865398
    Abstract: A method and system for selectively reducing call-setup latency. The method and system provides for selectively increasing the paging frequency used for paging certain mobile stations, so as to decrease the time that it takes to establish radio-link connectivity with those mobile stations. The method and system is particularly useful when establishing real-time communication sessions, such as instant chat sessions, but may be useful in other scenarios as well.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: March 8, 2005
    Assignee: Sprint Spectrum L.P.
    Inventors: Manish Mangal, Pawan Chaturvedi, Mark L. Yarkosky, Tong Zhou
  • Patent number: 6856681
    Abstract: The connection device connects a telecommunications system to a data processing device which provides telecommunications applications. The telecommunications system and the data processing device in each case have a switching network for through-connecting the relevant telecommunications application. The connection device is a switching device directly connected between the respective switching networks.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: February 15, 2005
    Assignee: Siemens Aktiengesellschaft
    Inventor: Manfred Janson
  • Patent number: 6850501
    Abstract: A method is presented for enhancing pre-synchronization reliability in a cellular radio system. At least one base station in the cellular radio system is arranged to transmit at least two such transmissions (350, 351; 360, 361; 370, 371; 380, 381) that are usable for mobile stations in pre-synchronization. Said two transmissions are relatively close to each other in succession and they are timed to occur approximately at a time when there is a temporary idle period in an active communication connection between a mobile station and a base station.
    Type: Grant
    Filed: May 15, 2000
    Date of Patent: February 1, 2005
    Assignee: Nokia Mobile Phones Ltd.
    Inventor: Benoist Sebire
  • Patent number: 6781985
    Abstract: Disclosed is a time-division multiplexer for demultiplexing, into individual time slots, time-division multiplexed data in a receive direction received from a network via a trunk unit, and sending the data to a prescribed tributary unit, and for multiplexing, to a prescribed time slot, data in a transmit direction which enters from tributary units and sending the data to the network via the trunk unit. The time-division multiplexer has a trunk bus to which a trunk unit is connected and a tributary bus to which tributary units are connected, and a time-slot interchange unit provided between these buses, wherein interchange of cross-connected time slots on the trunk side and time slots on the tributary side is performed dynamically by the time-slot interchange unit.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: August 24, 2004
    Assignee: Fujitsu Limited
    Inventors: Peter James Feder, Shoichi Sageshima, Takashi Nagato
  • Patent number: 6782000
    Abstract: A user interface for managing connections in a communication network cross connect. The user interface provides for creation, viewing and removing connections in the cross connect. When displaying connections, a slice value and granularity may be adjusted to allow for effective viewing of connections having high data rates. The user interface may include a search tool for locating connections and/or a protection setup routine to facilitate establish protection connections.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: August 24, 2004
    Assignee: CIENA Corporation
    Inventors: Mahesh Subramanian, Suresh Muthu, Kuga P. Visagamani
  • Patent number: 6771654
    Abstract: Multiple network switches are configured having memory interfaces that transfer segmented packet data to each other via a unidirectional data bus ring connecting the network switches in a single ring or “daisy chain” arrangement. The memory interfaces are also configured for transferring the segmented packet data to respective local buffer memories for temporary storage. The memory interfaces transfer the data units according to a prescribed sequence, optimizing memory bandwidth by requiring only one read and one write operation to and from the local buffer memory for each segmented packet data being received and transmitted through the switches.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: August 3, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jinqlih (Charlie) Sang, Shashank Merchant
  • Patent number: 6768745
    Abstract: A SONET network interface for interconnecting at least one high speed unit (HSU) with at least two low speed interface units (LSUs) to enable transmission of signals therebetween. The interface having: a common bus of predetermined bit width for interfacing the HSU unit with each of the LSU units to enable transmission of signals from each of the LSUs to the HSU, and reception of the signals from the HSU to each of the LSUs; a first partition bus of the predetermined bit width for interfacing the HSU to a predetermined number of the LSUs, the first partition bus being partitioned into a first bus for interfacing the HSU to a first subset of the LSUs and a second bus for interfacing the HSU to a second subset of the LSUs; and a second partition bus of the predetermined bit width for interfacing the HSU to a predetermined number of the LSU units.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: July 27, 2004
    Assignee: Zhone Technologies, Inc.
    Inventors: Steven Scott Gorshe, Robert Wesley Brooks
  • Patent number: 6741588
    Abstract: This invention relates to arrangements for eliminating loop-around trunks for operational calls. Such trunks are used when a single switch performs two distinct functions, such as local service and operator assistant service. In order to simplify software, the software for each of these functions is designed separately; in the prior art, if both functions are needed, two separate connections are established and are joined by the use of a loop-around trunk. In accordance with Applicant's invention, the loop-around trunk is eliminated by initially establishing a connection from a real time-slot to a virtual time-slot for the first function and from a virtual time-slot to a real time-slot for the second function; the real time-slots for receiving the call and for transmitting the call to an inter-office trunk are then connected in the switch without requiring the use of a separate loop-around trunk.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: May 25, 2004
    Assignee: Lucent Technologies, Inc.
    Inventor: Gilbert Mark Stewart
  • Patent number: 6704308
    Abstract: An apparatus and method for data processing in a flexible multiple-DSP architecture that can be readily adapted to changing customer demands and changes in DSP processing capability is described. The apparatus comprises of two or more processors, two or more dedicated serial data buses, and a shared data bus. Each processor processes data received via the dedicated data bus in a first type of processing task. Each processor processes data received via the shared data bus in a second type of processing task.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: March 9, 2004
    Assignee: Cisco Technology, Inc.
    Inventors: Kirk Sanders, Madhu Grandhi
  • Patent number: 6690665
    Abstract: A receiving device for a mobile station receives signals transmitted from a base station having a time-switched transmission diversity (TSTD) function. In the receiving device, a despreader despreads channel signals which have been transmitted in a TSTD mode of operation. A pilot separator separates a pilot signal from the despread channel signals. A channel estimator generates a channel estimation signal by selecting pilot signals transmitted from a same antenna of a transmitter according to a TSTD pattern of the transmitter. A compensator compensates the channel signals with the channel estimation signal.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: February 10, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Woo Choi, Soon-Young Yoon, Jong-Han Kim, Su-Won Park, Jae-Heung Yeom
  • Publication number: 20040001454
    Abstract: A timeslot interchange switch has a three stage pipelined construction. A cross-connect stage identifies egress timeslots for which there is a corresponding data source. The cross connect stage has a set of flags which indicate whether or not there is a data source for each of a plurality of egress timeslots. The cross connect stage takes the flags in groups. If one or more flags in a group indicates an egress timeslot has a corresponding data source then information identifying the egress timeslot is passed to a connection scheduler via a FIFO. The connection scheduler looks up the data source for each the egress timeslot.
    Type: Application
    Filed: June 27, 2002
    Publication date: January 1, 2004
    Inventor: Patrick Boily
  • Patent number: 6667973
    Abstract: A SONET network interface for interconnecting a high speed unit (HSU) with low speed interface units (LSUs) to enable transmission of signals therebetween. The interface including: a bus for interfacing the HSU with each of the LSU units to enable transmission of signals from each of LSUs to the HSU, and reception of the signals from the HSU to each of the LSUs; and a backplane connected to the bus and having at least two time slots for performing full time slot interchange between the at least two LSUs, wherein any of the at least two LSUs can read received data directly from one of the at least two time slots and can place its transmit data into any other of the at least two time slots for communication with another of the at least two LSUs without exchanging the received and/or transmit data with the at least one HSU.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: December 23, 2003
    Assignee: Zhone Technologies, Inc.
    Inventors: Steven Scott Gorshe, Robert Wesley Brooks
  • Patent number: 6654368
    Abstract: An apparatus for processing a frame structured data signal, the data signal comprising at least one data frame comprising a plurality of data elements arranged in accordance with a frame structure. The apparatus is arranged to generate a tag element for each data element, the configuration of the tag element corresponding to the position of the respective data element within the detected data frame. The apparatus further includes a data processor, arranged to perform one or more respective processing operations on one or more of the data elements, wherein the or each processing operation is determined by the configuration of the respective tag element. The apparatus enjoys the flexibility afforded by a data processor while having relatively low processing power requirements.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: November 25, 2003
    Assignee: Nortel Networks Limited
    Inventors: William Smith, Christopher Clotworthy
  • Patent number: 6621828
    Abstract: A switch card for telecommunications node includes a shared memory operable to store traffic channels. A time slot interchanger (TSI) is coupled to a first bus and to the shared memory. The TSI is operable based on predefined switching instructions to access the shared memory to stored traffic channels received from the first bus and to retrieve traffic channels for transmission on the first bus. An asynchronous transfer mode (ATM) switch is operable to switch a traffic cell based on header information in the traffic cell. A traffic converter is operable to convert traffic channels retrieved from the shared memory to traffic cells for processing by a bus fuser and to convert traffic cells to traffic channels for storage in the shared memory. The bus fuser is coupled to the shared memory through the traffic converter, the ATM switch, and a second bus.
    Type: Grant
    Filed: December 1, 1999
    Date of Patent: September 16, 2003
    Assignee: Cisco Technology, Inc.
    Inventors: Barry W. Field, Kenneth M. Buckland, Charles R. Dyer, Riccardo G. Dorbolo, Danny Thom, Jan C. Hobbel, Soren B. Pedersen, Thomas A. Potter
  • Patent number: 6611526
    Abstract: A meshed backplane has dedicated pairs of connections for high-speed serial connection in each direction between each of multiple application modules and each other application module. A management/control bus is provided for out-of-band signaling. The mesh of serial differential pairs may be used for management/control bus signals when necessary. A time division multiplexing fabric is also provided for telephony applications. A star interconnect region is provided for distribution of signals from redundant clocks.
    Type: Grant
    Filed: May 8, 2000
    Date of Patent: August 26, 2003
    Assignee: ADC Broadband Access Systems, Inc.
    Inventors: Kumar Chinnaswamy, Paul H. Dormitzer
  • Patent number: 6600742
    Abstract: In an SDH transmission unit, a tributary block includes a plurality of routing blocks for accommodating low speed line signals of a predetermined capacity and performing line selection processing of the low speed line signals to be interfaced with a high speed block in accordance with a form of a tributary network. The form of the tributary network includes various line speeds and network configurations. At least one of the routing blocks serves, when the low speed line signals accommodated therein do not fully occupy the predetermined capacity, as a master block which accommodates at least one of the other routing blocks as a slave block in order to accommodate the low speed line signals accommodated in the other routing block.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: July 29, 2003
    Assignee: Fujitsu Limited
    Inventors: Masaki Hiromori, Seiji Matsuzaki, Hiroyuki Matsuo, Hirokazu Ito
  • Patent number: 6597690
    Abstract: A method for employing an associative memory to implement a switch is disclosed. The method comprises the step of receiving data in a first time slot. The method also comprises the step of examining the associative memory to determine if the data should be stored. Additionally, the method comprises the step of storing the data in a memory location and transmitting the data in a second time slot.
    Type: Grant
    Filed: January 22, 1999
    Date of Patent: July 22, 2003
    Assignee: Intel Corporation
    Inventors: Kalpesh D. Mehta, Krishna Shetty
  • Patent number: 6587823
    Abstract: The present invention relates to a data CODEC system for computer. The data CODEC system for computer comprises a system control software, a multichannel audio/speech and multimedia data signal processor, and a multichannel audio/speech and multimedia data input-output unit. The system control software communicates multichannel audio/speech and multimedia data with the multichannel audio/speech and multimedia data signal processor according to control of various application programs. The multichannel audio/speech and multimedia data signal processor processes multichannel audio/speech and multimedia data. The multichannel audio/speech and multimedia data input-output means inputs/outputs multichannel audio/speech and multimedia data from/to an external system.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: July 1, 2003
    Assignee: Electronics and Telecommunication Research & Fraunhofer-Gesellschaft
    Inventors: Kyeong Ok Kang, Dae Young Jang, Jin Suk Kwak, Jin Woo Hong, Sung Han Kim, Young Kwon Lim, Jin Woong Kim, Harald Popp, Stefan Geyersberger, Wolfgang Fiesel
  • Patent number: 6587461
    Abstract: In one embodiment, in a switching system, an ASIC device on a card coupled to a backplane communicates switched data to an outgoing network interface for the card without using the backplane, and remaining ASIC devices on the card communicate switched data, to other cards using the backplane for communication to outgoing network interfaces for the other cards. In another embodiment, an ASIC device includes a RAM storing a code for each first slot to combine with corresponding data from a first bus to specify an operation, a RAM applying the operation to generate modified data for each first slot, a RAM communicating as an address information specifying a second slot to correspond to each first slot, and a RAM locating the modified data for each first slot of a previous frame according to the address and communicating this modified data to a second bus in the corresponding second slot while the modified data for a current frame is being stored.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: July 1, 2003
    Assignee: Cisco Technology, Inc.
    Inventors: Brent K. Parrish, Werner E. Niebel
  • Patent number: 6587459
    Abstract: A TSA circuit which receives as input upper side incoming transmission data from a super high speed ring network and lower side incoming transmission data from a high speed ring network and outputs upper side outgoing transmission data to the super high speed ring network and lower side outgoing transmission data to the high speed ring network, provided with a time slot assignment function block which has a time switch and a space switch and produces outgoing transmission data obtained by switching channels for the incoming transmission data in units of bits, whereby high speed and large volume incoming transmission data can be processed for time slot assignment (TSA), interchanged in channels, and sent out as outgoing transmission data by a relatively small sized circuit configuration.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: July 1, 2003
    Assignee: Fujitsu Limited
    Inventors: Yukio Suda, Satoshi Nemoto, Masahiro Shioda, Takashi Kuwabara
  • Patent number: 6584119
    Abstract: A communications device and method for effectively managing bandwidth within a telecommunications network carrying both time division multiplexed signals as well as data signals. The communications device having dialable TDM/cell and/or packet-based bandwidth management capability so that a network operator can select to manage bandwidth for any particular signal on in STS, VT, or cell or packet basis.
    Type: Grant
    Filed: September 18, 2001
    Date of Patent: June 24, 2003
    Assignee: Fujitsu Network Communications, Inc.
    Inventors: Hamid Rezaie, Samuel Lisle, Masahiro Shinbashi, Kazuhiko Taniquchi, David Chen, Edward Sullivan, Mark Barratt, Richard DeBoer
  • Publication number: 20030112831
    Abstract: A synchronous cross-connect switch for routing data samples from a source node to a destination node comprises a mesh architecture including a plurality of inputs for receiving one or more of the data samples presented to the cross-connect switch. The mesh architecture includes a plurality of nodes operatively interconnected with one another using one or more half-duplex links. Each of the nodes further includes a receiver and a transmitter. Each node further includes an input time-slot-interchanger (TSI) operatively coupled to a first half-duplex link and to the receiver, the input TSI being configurable to selectively reorder one or more data samples received by the receiver, and an output TSI operatively coupled to a second half-duplex link and to the transmitter, the output TSI being configurable to selectively reorder one or more data samples to be transmitted by the transmitter.
    Type: Application
    Filed: December 17, 2001
    Publication date: June 19, 2003
    Inventor: Joseph Williams
  • Patent number: 6580709
    Abstract: A SONET network interface for interconnecting a high speed unit (HSU) with low speed interface units (LSUs) is provided for enabling transmission of signals therebetween. The interface includes: a bus for interfacing the HSU with each of the LSUs to enable transmission of signals from each of the LSUs to the HSU, and reception of the signals from the HSU to each of the LSUs, wherein the HSU, LSUs, and the bus are contained in a primary shelf. The network interface also has secondary shelves, each containing secondary LSUs and an intershelf ring interconnection (IRI) bus connecting the primary shelf and each of the secondary shelves in series for exchanging data between the HSU of the primary shelf and each of the secondary shelves.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: June 17, 2003
    Assignee: NEC America, Inc.
    Inventors: Steven Scott Gorshe, Robert Wesley Brooks
  • Patent number: 6556566
    Abstract: The invention provides a time-division switch and a time-division switching method by which a multi-frame signal of an arbitrary bit length can be outputted to or inputted from an arbitrary time slot. The time-division switching method is applied to weitchably connect time slots between different highways in time-division multiplex communication. The switch includes an external memory to which data from input time slots may be dropped, and from which data may be inserted into output time slots. Fixed data such as tone data may also be inserted into time slots. Dropping and insertion may be performed to replace existing time slot data or to fill new time slots.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: April 29, 2003
    Assignee: NEC Corporation
    Inventor: Saburou Ikeda
  • Patent number: 6553026
    Abstract: The present invention increases the communication path switching control speed. A demultiplexing circuit 2a is provided at an input side of a time division switch 1 and converts a serial signal of an input high 20a of multiplexed 32 Kbps sub rate channels into serial signals of the input highway 21a and 22a of multiplexed 64 Kbps full rate channels. A multiplexing circuit 2b is provided at an output side of the time division switch and converts serial signals of the output highways 21b and 22b of multiplexed 64 Kbps full rate channels into a serial signal of the output highway 20b of multiplexed 32 Kbps sub rate channels.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: April 22, 2003
    Assignee: NEC Corporation
    Inventor: Makoto Aihara
  • Patent number: 6546007
    Abstract: A time-slot interchanger (TSI 100) is used to control both time-slot access and distribution of signals to physical or virtual signal-processing circuits (106-116). The TSI includes a control table (200) with an entry (202) for each time slot, that specifies the source (204, 205) and destination (230, 231) of signals received during the corresponding time-slot interval and the processing (208-228) of those signals. The TSI is coupled to the signal processing circuits, and sends the received signals to the signal processing circuits for processing along with control signals to effect the processing specified by the corresponding control-table entries. For conferencing, the TSI sends all signals for each conference in sequence to the conferencing circuit (108) before starting and sending any signals for any other conference, thereby allowing a single conference accumulator to support any number of conferences of any size.
    Type: Grant
    Filed: March 31, 1999
    Date of Patent: April 8, 2003
    Assignee: Avaya Technology Corp.
    Inventor: Norman W. Petty
  • Patent number: 6539013
    Abstract: The time slot interchange capabilities of modern digital loop carriers are utilized to provide direct connectivity from the calling modem's line to an internet access modem bank through the digital loop carrier, thereby bypassing the local central end office. A call which is to a telephone number of an internet access provider's modem is routed to a bypass initiator. If the bypass initiator detects that the call is from a number which is serviced by a digital loop carrier having a local central end office bypass capability, then the bypass initiator issues a bypass command. The digital loop carrier establishes the bypass connection, but does not break the signaling connection on the initial call which was routed from the digital loop carrier through the local central end office to the bypass initiator. Once the bypass connection has been established, the bypass initiator sends a disconnect signal through the signaling connection of the initial call.
    Type: Grant
    Filed: September 2, 1997
    Date of Patent: March 25, 2003
    Assignee: Alcatel USA Sourcing, L.P.
    Inventor: K. Martin Stevenson, III
  • Patent number: 6535508
    Abstract: Multiple connections of subscriber access systems are controlled by means of V5 interfaces in a switched system accommodating interface prescribed by V5 protocol according to ETSI standards by using one B-channel as communication channel C2 with an access network that accommodates subscribers of another network service provider apart from communication channel C1 prescribed by normal V5 protocol between the local exchange and an access network operated by the service provider of the local exchange when connecting access networks accommodating subscribers of another network service providers to an access network operated by the service provider of the local exchange.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: March 18, 2003
    Assignee: NEC Corporation
    Inventor: Masato Aoyagi
  • Publication number: 20030048776
    Abstract: A method of the grooming traffic signals through a composite switch is disclosed that enables a traffic signal that is being transmitted between any two constituent switches to be re-routed through the composite switch without a hit (i.e., the dropping, replacing, inserting, or repeating of at least one bit in the traffic signal). This applies whether the constituent switches are adjacent in the composite switch or not. The composite switch in accordance with the illustrative embodiment comprises multiple routes between adjacent constituent switches and incorporates a mechanism that compensates for differential propagation delays along the routes. And still furthermore, the composite switch in accordance with the illustrative embodiment comprises alternative routes through different constituent switches and incorporates a mechanism that compensates for differential propagation delays through the constituent switches.
    Type: Application
    Filed: August 28, 2001
    Publication date: March 13, 2003
    Inventor: Christoph Dominique Loeffler-Lejeune
  • Patent number: 6519336
    Abstract: An interworking unit (14) for providing an interface between a digital communication network (12) and a public switched telephone network (PSTN) (16) includes a de-vocoder (30), a protocol termination unit (32), and a signal combiner (34) for processing signals being transferred from the digital network (12) to the PSTN (16). A digital communication signal received by the interworking unit (14) from the digital network (12) is processed by both the de-vocoder (30) and the protocol termination unit (32). The outputs of the de-vocoder (30) and the protocol termination unit (32) are then combined into a uniquely formatted signal that is then delivered into the PSTN (12). Similar functionality is also provided for processing signals in the reverse direction. The interworking unit 14 is capable of processing signals traversing the interface between the networks (12, 16) without a priori knowledge of the signal type being processed.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: February 11, 2003
    Assignee: General Dynamics Decision Systems, Inc.
    Inventors: Dean Paul Vanden Heuvel, Scott David Blanchard
  • Patent number: 6504786
    Abstract: An asymmetrical switching element including a random access memory element, a first port selectively coupled to the memory element by first control signal and a plurality of second ports, each independently coupled to the memory element by corresponding one of a plurality of second control signals.
    Type: Grant
    Filed: November 7, 2000
    Date of Patent: January 7, 2003
    Inventor: Gautam Nag Kavipurapu
  • Patent number: 6504852
    Abstract: A gateway between a first data network and a second data network enables translation of messages in accordance with a first protocol specific to the first data network into messages conforming to a second protocol specific to the second data network. The second data network includes software applications and the gateway includes a registration software entity. Messages coming from or going to a particular one of the software applications are processed by a representative software entity contained in the gateway and each new software application made available on the second data network causes the determination of the representative software entity at the registration software entity.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: January 7, 2003
    Assignee: Alcatel
    Inventors: Alban Couturier, Laurent-Philippe Anquetil
  • Patent number: 6498792
    Abstract: A telecommunications switching apparatus (10) includes optical paths (16-19) coupled to interface cards (26-29), which in turn are coupled to a switching circuit (41-42). The switching circuit is coupled to a plurality of universal connectors (71-74), each of which is coupled to an auxiliary connector (77-78). The universal connectors can each removably receive any one of several types of switching circuit cards (101-104), which each utilize a respective one of several different communication protocols. An auxiliary circuit card (107-108) may be provided in the associated auxiliary connector, in order to support switching circuit cards that use certain communication protocols. The optically transmitted information includes segments formatted according to respective communication protocols, and is converted from optical to electrical form by the interface cards.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: December 24, 2002
    Assignee: Fujitsu Network Communications, Inc.
    Inventors: Gary P. Johnson, Roland J. Moubarak, Masahiro Shimbashi, Katsuya Shirota, David X. Chen
  • Publication number: 20020181451
    Abstract: The time slot interchange capabilities of modern digital loop carriers are utilized to provide direct connectivity from the calling modem's line to an internet access modem bank through the digital loop carrier, thereby bypassing the local central end office. A call which is to a telephone number of an internet access provider's modem is routed to a bypass initiator. If the bypass initiator detects that the call is from a number which is serviced by a digital loop carrier having a local central end office bypass capability, then the bypass initiator issues a bypass command. The digital loop carrier establishes the bypass connection, but does not break the signaling connection on the initial call which was routed from the digital loop carrier through the local central end office to the bypass initiator. Once the bypass connection has been established, the bypass initiator sends a disconnect signal through the signaling connection of the initial call.
    Type: Application
    Filed: September 2, 1997
    Publication date: December 5, 2002
    Inventor: K. MARTIN STEVENSON
  • Publication number: 20020176410
    Abstract: Time-slot interchange switches include measurement circuits that automatically measure frame alignment associated with a plurality of multi-frame data streams received by the switch. Internal programming circuits are also provided to convert the frame alignment measurements into frame offsets. Unacceptable frame offsets are also automatically identified using error control circuitry. These measurement and programming circuits streamline frame offset measurement techniques and enable on-chip measurement and conversion of frame delays to frame offsets and programming of frame offset registers (FORs).
    Type: Application
    Filed: May 16, 2001
    Publication date: November 28, 2002
    Inventors: Dave MacAdam, Alex Goldhammer
  • Patent number: 6470006
    Abstract: A method of controlling the timing of a transmission time slot within a time frame comprises transmitting information over a channel in an allocated time slot at an allocated channel frequency, measuring a received interference level at the channel frequency around the start and around the end of the time slot, analysing the measured interference levels to detect the presence or absence of interferers at the channel frequency around the start and around the end of the time slot, and, if required, adjusting the timing of subsequent time slots for the channel to reduce interference from the detected interferers. Transmission slot timing of the invention enables dynamic avoidance of interference, which can therefore avoid both intermittent and continuous interferers, and can result in synchronisation of different systems to avoid sliding interferers. This method also enables the throughput of the communication system to be largely unaffected.
    Type: Grant
    Filed: March 8, 1999
    Date of Patent: October 22, 2002
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Timothy J. Moulsley
  • Patent number: 6400714
    Abstract: A three stage method and apparatus for performing dynamic time slot assignment on both 2-bit and 8-bit information is disclosed. In the first stage, 2-bit packets undergo a 2-bit time slot assignment prior to being sent to a conventional time slot interchanger. 8-bit information, however, is passed to the time slot interchanger without undergoing the 2-bit time slot assignment. The time slot interchanger performs time slot assignment on the 8-bit information to place the information in the appropriate outgoing DS0 time slots. In the second stage, the time slot interchanger places the 2-bit information into a fixed sequence of 8-bit time slots and passes these time slots to a packer. The prescribed time slots are established such that each time slot represents an assigned 2-bit location within a specific 8-bit time slot. The packer then combines the assigned time slots to create a serial stream of 8-bit time slots where each time slot contains up to four dynamically assigned 2-bit packets.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: June 4, 2002
    Assignee: Lucent Technologies Inc.
    Inventors: Scott D. Motyka, Kenneth C. Seiter
  • Patent number: 6396847
    Abstract: A communications device and method for effectively managing bandwidth within a telecommunications network carrying both time division multiplexed signals as well as data signals. The communications device having dialable TDM/cell and/or packet-based bandwidth management capability so that a network operator can select to manage bandwidth for any particular signal on in STS, VT, or cell or packet basis.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: May 28, 2002
    Assignee: Fujitsu Networks Communications, Inc.
    Inventors: Hamid Rezaie, Samuel Lisle, Masahiro Shinbashi, Kazuhiko Taniguchi, David Chen, Edward Sullivan, Mark Barratt, Richard DeBoer
  • Patent number: 6389015
    Abstract: A method of and system for managing a SONET ring computes an optimally balanced demand loading for the SONET ring and generates an updated time slot assignment map for each node of the SONET ring based upon the optimally balanced demand loading. The method causes each node of the SONET ring to switch substantially simultaneously to its updated time slot assignment map, thereby reconfiguring the SONET ring.
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: May 14, 2002
    Assignee: MCI Communications Corporation
    Inventors: Jennifer Huang, Anis Khalil, Sridhar Nathan
  • Patent number: 6389014
    Abstract: An ATM switching device and method for providing voice call service. In the ATM switching device, input time switch modules are connected to an input PSTN interface to switch channel data received over sub-highways to voice stream data grouped in accordance with destinations by sorting the received channel data according to time slots corresponding to numbers of destination time switch modules. Input cell assembly and disassembly modules are connected to the input time switch modules to assemble a group of voice data headed for the same destination into an identical ATM cell. An ATM switch is connected to the input cell assembly and disassembly modules and to an ATM interface to self-route the ATM cell, to switch the ATM cell, and to output the switched ATM cell to a corresponding destination. Destination cell assembly and disassembly modules disassemble the ATM cell received from the ATM switch into voice stream data.
    Type: Grant
    Filed: June 11, 1998
    Date of Patent: May 14, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Doug-Young Song
  • Publication number: 20020024930
    Abstract: A method of managing the change of time slot allocation in classical MS-SP ring networks. In two-fiber rings, the criterion for choosing the low priority AU-4 to be used for the protection in case of simple failure can be summarized as follows: given an STM-n ring line signal, where “n” is the overall number of the handled channels, there results that LP AU-4#XLP=AU-4#(XHP+n/2), where X is the HP AU-4 index in the failured span. In four-fiber rings, AU-4 LP=AU-4#X HP. Should two or more failures occur, criteria are provided for selecting one of the failured spans and tracing the problem back to the case of single two/four fiber ring failure.
    Type: Application
    Filed: August 1, 2001
    Publication date: February 28, 2002
    Applicant: ALCATEL
    Inventor: Vincenzo Sestito
  • Publication number: 20020024939
    Abstract: A private base station (231) provides communication directly between a cellular mobile telephone (201) operable within a cellular network and a public switched terrestrial network (116). The base station is configurable to establish communication to a mobile telephone while minimizing interference with similar base stations. The base stations may transmit on similar frequencies but within different time division multiplexed time slots.
    Type: Application
    Filed: November 27, 1998
    Publication date: February 28, 2002
    Inventors: MARKO SILVENTOINEN, PEKKA RANTA
  • Patent number: 6330236
    Abstract: This invention describes a method for transmitting and forwarding packets over a switching network using time information. The network switches maintain a common time reference, which is obtained either from an external source (such as GPS—Global Positioning System) or is generated and distributed internally. The time intervals are arranged in simple periodicity and complex periodicity (like seconds and minutes of a clock). A data packet that arrives to an input port is switched to an output port based on its order or time position in the time interval in which it arrives at the switch. The time interval duration can be longer than the time duration required for transmitting a data packet, in which case the exact position of a data packet in its forwarding time interval is predetermined. This invention provides congestion-free data packet switching for data packets for which capacity in their corresponding forwarding links and time intervals is reserved in advance.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: December 11, 2001
    Assignee: Synchrodyne Networks, Inc.
    Inventors: Yoram Ofek, Nachum Shacham
  • Patent number: 6324176
    Abstract: Apparatus and a method for interfacing between the Internet and the Telephone Network. A time slot interchange is enhanced by the addition of a supplementary memory for storing data for accumulating Internet packets. When a packet has been accumulated, the appropriate header is inserted into the packet under the control of a routing processor, and the packet can then be sent as a group of adjacent PCM samples over a connection to the Internet. In other embodiments, information is sent to the Internet over a direct data pipe for transmitting ATM cells or Ethernet packets. A Vocoder signal processor can be inserted between the TSI memory, and the supplementary memory to convert PCM voice samples into vocoded voice samples for transmission over the Internet. A modem signal processor can be interposed between the TSI memory and the supplementary memory to convert between analog data (representing for example, shift key analog signals) and binary data for transmission within packets over the Internet.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: November 27, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Bohdan Lew Bodnar, James Patrick Dunn, Conrad Martin Herse, Enn Tammaru
  • Patent number: 6310878
    Abstract: A large router for routing datagrams. The large router comprises a plurality of router slices, each of which receives switches and transmits datagrams. Each router slice has a routing memory for routing the packets. If a packet is received whose destination address is not known to the receiving packet slice, the packet slice broadcasts a request for routing information for that datagram to the other packet slices of the large router and routes the packet in accordance with the received responses. Groups of slices are interconnected by a time slot interchange (TSI) unit, and groups of TSIs are interconnected by a time multiplexed switch. The router can consist of more than one switch; the switches being interconnected by high speed data links. Advantageously, the router, though composed of small slices, acts as if it were a single large high capacity entity.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: October 30, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Bohdan Lew Bodnar, James Patrick Dunn, Conrad Martin Herse, Enn Tammaru
  • Publication number: 20010033584
    Abstract: A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized data frame. Both the configuration data and a frame clock may be propagated through the plural stages from a master switch. First and last stages of the digital cross connect may be implemented on common chips having two framing time bases. Data may be aligned to a global frame clock and interchanged using a single random access memory in a time slot interchanger. The write address to the random access memory is generated from a local frame counter keyed to the input data frame while a read address is transformed from a global frame counter.
    Type: Application
    Filed: January 16, 2001
    Publication date: October 25, 2001
    Applicant: Velio Communications, Inc. San Jose, CA
    Inventor: William J. Dally
  • Publication number: 20010024439
    Abstract: A telecommunications gateway allows packets to be sent over a TDM system and allows TDM traffic to be sent over a packet switched network. The gateway is a universal port that includes a plurality of Digital Signal Processors (DSPs) that are controlled by software. The controlling software determines what single function the DSP will perform over multiple channels. Each DSP handles multiple channels, however, each DSP is restricted such that all of its multiple channels are permitted to handle the telecommunications traffic according to one signaling protocol.
    Type: Application
    Filed: May 29, 2001
    Publication date: September 27, 2001
    Inventors: Edward Morgan, William Witowski, Joseph Crupi
  • Patent number: 6269103
    Abstract: A split-architecture audio codec providing an interface to a high speed broad band modem or other data source device capable of multi-megabit data rates. A plurality of time slots are utilized by the broad band modem in a time division multiplexed (TDM) data bus between the controller and analog sub-systems of the audio codec. Current examples of such high speed broad band modems include HDSL, SDSL, and ADSL, collectively referred to as xDSL. An interleaver in the analog sub-system rate adapts between the data rate of the broad band modem and the fixed rate of the TDM data bus between the sub-systems based on the number of time slots assigned to the broad band modem interface. Interface capability is provided for broad band modems having data rates up to 6.72 Mb/s for split-architecture audio codecs which conform to the AC '97 specification, and higher if non-conformance is acceptable.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: July 31, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventor: Donald Raymond Laturell
  • Patent number: 6243400
    Abstract: Apparatus for switching full rate (e.g., 64 kilobit per second) signals and composite signals comprising a plurality of subrate signals (e.g., 32 kilobit per second subrate signal). The apparatus includes a unit for compressing selected ones of a plurality of full-rate signals into a smaller plurality of full-rate single and composite signals, and apparatus for decompressing composite signals into a plurality of full-rate signals. The main elements of the switching fabric of the switch continue to switch full-rate signals. Advantageously, during periods of heavy load, the switching network fabric of a switching system can carry more calls, and more traffic can be carried between switches equipped for subrate switching.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: June 5, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Douglas Anthony Deutsch, David B. Smith