Multistage Switch Patents (Class 370/388)
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Patent number: 7684389Abstract: An N-dimensional lattice network that scales to capacities of the order of a Yotta bits per second (1024 bits per second) includes a plurality of sub-nets of edge module switches interconnected by an agile switching core. The agile core may be distributed. In the N-dimensional lattice network, each edge module 408 is connected to N core stages, each core stage having an associated dimensional indicator. The input/output ports of each edge module are divided into (N+1) port groups. One of the port groups serves local sources/sinks while the remaining port groups are respectively connected to core stages in each of the N dimensions. This structure permits virtually unlimited capacity growth and significantly simplifies the routing and forwarding functions. The edge modules are addressed using logical coordinates, one coordinate being assigned for each of the N dimensions. This simplifies routing and permits each edge module to compute its own routing tables.Type: GrantFiled: October 20, 2004Date of Patent: March 23, 2010Assignee: Nortel Networks LimitedInventor: Maged E. Beshai
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Publication number: 20100061242Abstract: In one embodiment, edge devices can be configured to be coupled to a multi-stage switch fabric and peripheral processing devices. The edge devices and the multi-stage switch fabric can collectively define a single logical entity. A first edge device from the edge devices can be configured to be coupled to a first peripheral processing device from the peripheral processing devices. The second edge device from the edge devices can be configured to be coupled to a second peripheral processing device from the peripheral processing devices. The first edge device can be configured such that virtual resources including a first virtual resource can be defined at the first peripheral processing device. A network management module coupled to the edge devices and configured to provision the virtual resources such that the first virtual resource can be migrated from the first peripheral processing device to the second peripheral processing device.Type: ApplicationFiled: September 11, 2009Publication date: March 11, 2010Inventors: Pradeep Sindhu, Gunes Aybay, Jean-Marc Frailong, Anjan Venkatramani, Quaizar Vohra
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Patent number: 7675909Abstract: A method and apparatus are provided for horizontally slicing a multi-stage switching fabric having transmission inputs and transmission outputs to and from the switch fabric. The switching fabric includes switch elements arranged in at least first and second stages, each switch element having element inputs and outputs with each switch element being configured to join one of the element inputs with an associated one of the element outputs. The switch fabric includes a first logic device that contains a stage-1subset of the switch elements that is arranged within, and configured to operate as part of, the first stage. The first logic device also contains a stage-2 subset of the switch elements arranged within, and configured to operate as part of, the second stage. The switch fabric includes a second logic device that contains a stage-1 subset of the switch elements that is arranged within, and configured to operate as part of, the first stage.Type: GrantFiled: December 15, 2004Date of Patent: March 9, 2010Assignee: Tellabs Operations, Inc.Inventors: Thomas E. Ryan, Mark E. Boduch, John B. Kenney
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Patent number: 7675870Abstract: An Internet Protocol Television (IP-TV) broadcasting service system and method using a physical layer multicast switch are provided. The system comprises: a head end which converts an Ethernet signal to a virtual concatenation group (VCG) signal of a synchronous digital hierarchy/synchronous optical network (SDH/SONET); a multicast switch which multicasts the VCG signal in a physical layer; and a tail end which receives the multicasted VCG signal through a Synchronous Transmission Module level n (STM-N) optical link and restores the VCG signal to the Ethernet signal. Therefore, high quality TV broadcasting can be provided in an IP multicast network.Type: GrantFiled: February 26, 2007Date of Patent: March 9, 2010Assignee: Electronics and Telecommunications Research InstituteInventors: Kyung Gyu Chun, Soon Seok Lee
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Patent number: 7672301Abstract: A distribution stage is disclosed comprising a plurality of inputs coupled to a plurality of first stage switching devices, a plurality of outputs coupled to a plurality of second stage switching devices, and a distribution configuration. The distribution configuration is configured to receive a plurality of bandwidth units (BU's) from each first stage switching device, and to distribute at least one BU from each first stage switching device to each second stage switching device, such that each second stage switching device is assured of receiving at least one BU from each first stage switching device. In effect, the distribution stage ensures that each first stage switching device has a logical link to each second stage switching device. In one embodiment, the distribution stage is configured in accordance with a distribution configuration that is static.Type: GrantFiled: May 2, 2003Date of Patent: March 2, 2010Assignee: Ciena CorporationInventors: Daniel E. Klausmeier, Edward Sprague
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Patent number: 7660239Abstract: Transferring data via a switch fabric comprises: for each unit of data to be transferred, selecting one of a plurality of links from a fabric access node to the switch fabric to transfer the unit of data, and in the event that one or more of the plurality of links become unavailable, such that one or more remaining links remain available for transferring data, transferring a subsequently received unit of data via one of the remaining links.Type: GrantFiled: April 23, 2004Date of Patent: February 9, 2010Assignee: Alcatel-Lucent USA Inc.Inventors: Nelson Willhite, Mike Noll, Robert Steven Martin, Akhil Duggal, Craig Lindberg, Thomas Carleton Jones, Srinivas Komidi
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Publication number: 20100027535Abstract: A conventional technology does not show that the number of middle stage switches is minimized on a non-blocking condition of a multisource and possible multicast Clos type network, and it becomes a high cost system. Further, no addition or deletion of a connection can be done without a data loss. It is an object to provide, as a means for solving the problems, a multisource and multicast possible Clos type network based on such a technology that the number of middle stage switches is minimized on a non-blocking condition and that addition/deletion of a connection to a existing multicast tree can be carried out without a data loss, so that the network can be operated at low cost without a data loss.Type: ApplicationFiled: November 6, 2007Publication date: February 4, 2010Applicant: MEDIA GLOBAL LINKS CO., LTD.Inventors: Yuanyuan Yang, Takashi Oguma
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Patent number: 7653069Abstract: In a node to forward data on a switch fabric, a method that includes scheduling the forwarding of data associated with one of a plurality of traffic classes. The data is to be transmitted through one of a plurality of ports coupled to the switch fabric, each port to be associated with a queue to store data to be forwarded from that port. The scheduling is to include a two stage arbitration scheme. The first stage is to select one queue associated for each traffic class. The second stage is to select one queue from among the queues selected for each traffic class selected in the first stage.Type: GrantFiled: December 30, 2005Date of Patent: January 26, 2010Assignee: Intel CorporationInventors: Sridhar Lakshmanamurthy, Hugh Wilkinson
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Patent number: 7639679Abstract: To selectively route stand-by packets in input modules to destination output modules via a switching matrix, distributed arbitration functions are executable by successive arbitration cycles. Each cycle comprises: a first phase executable by each input controller to send each output controller requests representative of the quantities of required stand-by packets; a second phase executable by each output controller to determine the quantity of admissible packets depending on the requests; a third phase executable by a central arbitration unit to determine allowed aggregate quantities depending on all the admissible quantities; and a fourth phase executable by each input controller to determine the allowed packet quantities depending on the admissible quantities and of the allowed aggregate quantities.Type: GrantFiled: September 29, 2006Date of Patent: December 29, 2009Assignee: AlcatelInventors: Ludovic Noirie, Georg Post, Silvio Cucchi, Fabio Valente
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Patent number: 7634418Abstract: Usage status in a facility is comprehended so that service information such as user waiting times is quickly offered to users and others. This is configured to comprise detection units (antennas) detecting unique information of tickets carried by visitors in areas for keeping the visitors waiting, and a calculation unit (control PC, information management center) calculating visitor information representative of congestion status of the visitors in the areas.Type: GrantFiled: March 25, 2005Date of Patent: December 15, 2009Assignee: Fujitsu LimitedInventor: Mitsugu Kato
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Patent number: 7620033Abstract: Reduction of administrative overhead in maintaining network information, rapid convergence on an optimal routing path through the data network, and utilization of only required network resources are realized by a novel method for establishing a call path between network users. The method is based upon deployment of a network information server that stores network topology information and that is addressable by each end user. In this method, the network information server receives a request to establish a call path. The request identifies at least the calling party. In response to the request, the network information server determines a network traversal between the calling party and a root network wherein the network traversal includes call path information about the sub-networks between the calling party and the root network. The request for establishing a call path can also identify the called party.Type: GrantFiled: May 21, 2004Date of Patent: November 17, 2009Assignee: Alcatel-Lucent USA Inc.Inventors: Thomas P. Chu, Tao Jin, Francis Robert Magee, Steven H. Richman, Benjamin Y. C. Tang
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Patent number: 7616631Abstract: A method, apparatus, and computer instructions for a storage subsystem. This subsystem includes controller devices, storage devices, and a communications network. The communications network connects the controller devices and the storage devices. The communications network also includes a set of diagnostic outputs. The set of diagnostic outputs is configured to output data sent between two devices from the controller devices and the storage devices for monitoring.Type: GrantFiled: August 14, 2002Date of Patent: November 10, 2009Assignee: LSI CorporationInventors: William A. Hetrick, Jeremy Dean Stover, Matt Tiemeyer
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Patent number: 7613177Abstract: Extra stages can be added to a switching network to provide pathwise redundancy for fault tolerance and to alleviate traffic blocking. Also, the addition of extra stages can alleviate the loss of pathwise redundancy when the width of switching networks is increased. An in-service method of upgrading a switching network by adding stages allows the addition of redundancy to an existing network without the need to take the network out of service. From an operational point of view, it is often desirable for the upgrade process to be performed by a plurality of sequential steps. However, it is also desirable to minimize the number of steps performed. Because the insertion of extra stages into an existing network calls. for the rewiring of interconnection networks above and below the insertion point, the number of steps can be minimized while also minimizing the impact to network traffic by concurrently rewiring those interconnection networks through a plurality of disconnection and connection steps.Type: GrantFiled: May 31, 2005Date of Patent: November 3, 2009Inventor: Haw-minn Lu
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Patent number: 7609695Abstract: New coding scheme to minimize the total local delay in the switching elements. Under the new coding scheme, the switching element can be optimized such that it can start to produce the first output bits of the output packets without having to wait for the complete arrival of all of the local routing bits, and hence reduces the local buffering delay. In practical switching applications, each switching element in a multistage switching network supporting multicasting is a bicast cell, and the concomitant new coding scheme can even achieve a minimum delay in each bicast cell. Hence the total latency of the overall switching network is minimized.Type: GrantFiled: February 23, 2002Date of Patent: October 27, 2009Assignee: Industrial Technology Research InstituteInventors: Jian Zhu, Shuo-Yen Robert Li
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Patent number: 7602745Abstract: Embodiments of multiple input multiple output wireless communication systems, associated methods and data structures are generally described herein.Type: GrantFiled: December 20, 2005Date of Patent: October 13, 2009Assignee: Intel CorporationInventors: Xintian E. Lin, Qinghua Li, Keith A. Holt, Raymond Blackham
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Patent number: 7602771Abstract: A one-dimensional circulating switch may be defined by connections between several switch modules and one or more temporal cyclic rotators. Where a switch module that is part of a first one-dimensional circulating switch is also connected one or more temporal cyclic rotators that define a second one-dimensional circulating switch, a two-dimensional circulating switch is formed. A two-dimensional circulating switch is flexible and may scale to capacities ranging from a few gigabits per second to multiple Petabits per second.Type: GrantFiled: December 30, 2004Date of Patent: October 13, 2009Assignee: Nortel Networks LimitedInventor: Maged E. Beshai
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Patent number: 7596135Abstract: Methods and apparatus for routing mixed cast requests through a Clos-like network are disclosed. According to one aspect of the present invention, a method for processing a routing request within a network system includes computing costs associated with input links between a center stage and an input stage and computing costs associated with output links between the center stage and an output stage. The method also includes comparing the costs associated with the input links and the costs associated with the output links to identify a first input link, a first output link, and a second output link. The first output link is associated with a first center stage node and the second output link is associated with a second center stage node. The request is routed using the first input link, the first output link, and the second output link.Type: GrantFiled: May 23, 2003Date of Patent: September 29, 2009Assignee: Cisco Technology, Inc.Inventors: Ronald Iovine, Weiqing Cai
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Patent number: 7590110Abstract: A high capacity switching node comprises a lattice structure of low-latency switch units and a plurality of balanced connectors interfacing electronic edge nodes to diagonal subsets of said switch units. The edge nodes may be collocated with the switch units or remotely located. The switch units may be bufferless, having optical switch-fabrics for example, thus requiring a compound vacancy-matching process. Using switch units each of dimension 64×64, a fast switching node having a dimension of the order of 10,000×10,000 can be constructed. With a typical wavelength-channel capacity of 10 Gb/s, the fast-switching node would scale to a capacity of 100 terabits per second, which is orders of magnitude higher than the capacity of known fast optical switches. A fast-switching optical switch of such scalability significantly reduces network complexity and cost.Type: GrantFiled: December 22, 2005Date of Patent: September 15, 2009Assignee: Nortel Networks LimitedInventors: Maged E. Beshai, Lindsay McGuinness
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Patent number: 7587516Abstract: Class network routing is implemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With class network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast. Class network routing is also applied to dense matrix inversion algorithms on distributed memory parallel supercomputers with hardware class function (multicast) capability. This is achieved by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware class functions, which results in faster execution times.Type: GrantFiled: February 25, 2002Date of Patent: September 8, 2009Assignee: International Business Machines CorporationInventors: Gyan Bhanot, Matthias A. Blumrich, Dong Chen, Paul W. Coteus, Alan G. Gara, Mark E. Giampapa, Philip Heidelberger, Burkhard D. Steinmacher-Burow, Todd E. Takken, Pavlos M. Vranas
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Patent number: 7586909Abstract: A striping algorithm selects a route on which to transmit each next data segment, in dependence upon relative channel loading so far, taking account of multicast. Input modules can keep a channel loading history for each route it has, and can update its history for each route that a data segment follows through the fabric. In an embodiment, the input module transmits each data segment toward an i'th intermediate stage module, where i minimizes q(i,a(G),c)+q(i,b(G),c)+ . . . +q(i,k(G),c), where q(i, j, c) indicates the number of bytes of data sent, during a given prior time period, from the input module to each j'th one of the output modules via each i'th one of the intermediate stage modules, and a(G), b(G), . . . , and k(G) are the output module(s) in the multicast group G to which the data segment is destined.Type: GrantFiled: October 11, 2002Date of Patent: September 8, 2009Assignee: Agere Systems Inc.Inventors: Jean Walrand, John T. Musacchio, Roy T. Myers, Chung Kuang Chin
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Publication number: 20090201923Abstract: Embodiments of the present invention relate to portions of a switch fabric having a single logical stage and at least one physical stage. In addition, the data paths and the control paths of the switch fabric can be decoupled thereby allowing additional processing to be performed than would otherwise be the case with control rates that matched the high data rates. In other words, data cells received on high speed links can be spread over many lower speed links; consequently, the data cells can transit the switch fabric at that high speed while the control information associated with the data can be processed at that lower speed. Because the control information can be processed at a lower speed (associated with the control path), the control information can be processed over a greater period of time.Type: ApplicationFiled: February 9, 2009Publication date: August 13, 2009Applicant: TELLABS SAN JOSE, INC.Inventors: RAGHAVAN MENON, ADAM GOLDSTEIN, MARK D. GRISWOLD, MITRI I. HALABI, MOHAMMAD K. ISSA, AMIR LEHAVOT, SHAHAM PARVIN, XIAOYANG ZHENG
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Patent number: 7557613Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.Type: GrantFiled: July 16, 2008Date of Patent: July 7, 2009Assignee: Advantage Logic, Inc.Inventors: Peter M. Pani, Benjamin S. Ting
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Patent number: 7554959Abstract: A group of network devices, such as Ethernet switches, are logically configured as a single cluster, with one commander device and one or more member devices. Each network device capable of belonging to a cluster transmits data packets containing cluster capability information to its neighbors. Each network device capable of belonging to a cluster that receives data packets containing cluster capability information maintains a database containing information about its cluster-capable neighbor devices. The commander device of a cluster is the point-of-contact through which the cluster is managed. The commander device maintains a database of neighbors of the entire cluster. Upon user request, the commander device displays a list of cluster neighbors and notes which ones may be added to the cluster. When the user adds a device to the cluster, that device immediately sends its database of discovered neighbors to the commander device.Type: GrantFiled: October 15, 2003Date of Patent: June 30, 2009Assignee: Cisco Technology, Inc.Inventor: Mary G. Dowling
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Publication number: 20090141711Abstract: An interleaved multistage switching fabric includes Y multistage switching fabric panels, where Y is an integer greater than one. Each panel has primary inputs for receiving cells to be routed, local outputs for outputting routed cells, primary outputs for outputting non-routed cells, and reentry points for introducing non-routed cells into the panel. The switching fabric additionally includes at least one demultiplexer subsystem communicatively coupled to primary inputs of each panel, for interfacing the switching fabric with input lines. The switching fabric further includes at least one multiplexer subsystem communicatively coupled to local outputs of each panel, for interfacing the switching fabric with destination queues. The switching fabric additionally includes Y recirculation connections, where each recirculation connection communicatively couples primary outputs of one panel to reentry points of another panel.Type: ApplicationFiled: November 26, 2008Publication date: June 4, 2009Applicant: WASHINGTON STATE UNIVERSITY RESEARCH FOUNDATIONInventors: Rongsen He, Jose G. Delgado-Frias
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Patent number: 7542464Abstract: A large high capacity switch is provided for a communication network which is constructed from a network of smaller switches. Data is fragmented into fixed sized cells and the cells of a traffic flow are aggregated by grouping cells to form larger yet uniform units of information transfer. The groups are transmitted synchronously and in parallel to increase the effective bandwidth of information transfer.Type: GrantFiled: May 14, 2004Date of Patent: June 2, 2009Inventor: Alexander G. Fraser
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Reconfigurable interconnect/switch for selectably coupling network devices, media, and switch fabric
Patent number: 7539184Abstract: A reconfigurable interconnect/switch for selectably coupling network devices, media, and switch fabric. The reconfigurable interconnect/switch enables network devices, such as network processor units (NPUs) to selectively communicate with other NPUs, media (via a media interface), and switch fabric (via a switch fabric interface), thus providing flexibility in the use of network line cards and the like. Embodiments of the switching/routing scheme may be employed to support network devices having separate media and/or switch fabric interfaces, as well as network devices having selectable media switch fabric (MSF) interfaces that share signal lines.Type: GrantFiled: December 30, 2004Date of Patent: May 26, 2009Assignee: Intel CorporationInventors: Edoardo Campini, Douglas Lee Stahl, David R. Formisano -
Patent number: 7529221Abstract: A system for sending multimedia information from at least one base station to one or more mobile stations via at least one wireless communication link includes at least one multimedia source for generating the multimedia information. At least one processor is coupled to the multimedia source for generating a number of data streams derived from the multimedia information on a media control access (MAC) layer. At least one data channel modulator is coupled to the processor for mapping the data streams into a number of data packets on a forward packet data channel between the base station and the mobile station, using a physical layer signaling based on a code-division multiple access (CDMA) or orthogonal frequency division modulation (OFDM) technology.Type: GrantFiled: November 17, 2005Date of Patent: May 5, 2009Assignee: Taiwan Semicondutor Manufacturing Co., Ltd.Inventors: Stash Czaja, Feng Qian
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Patent number: 7519053Abstract: A multi-grained high-performance rotorswitch scaling to high capacities is disclosed. In one embodiment, the rotorswitch comprises common-memory switch modules each of which cyclically accessing each other switch module for an access interval of a predefined value and transmitting, during the access interval, a number of data segments collectively having a duration not exceeding the access interval. The data segments transmitted to a given switch module during an access interval may be destined to several other switch modules. The switch modules may cyclically connect to each other using a plurality of rotators of the same rotational speed. In another embodiment, the rotorswitch uses rotators of different speeds connecting common-memory switch modules so that each of the switch modules has parallel cyclic access, possibly at different cyclic rates, to each other switch module.Type: GrantFiled: August 24, 2005Date of Patent: April 14, 2009Assignee: Nortel Networks LimitedInventor: Maged E. Beshai
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Patent number: 7519054Abstract: In general, in one aspect, the disclosure describes a multi-stage switch having at least one ingress switch module to receive data and to generate frames that are transmitted as a wavelength division multiplexed signal. The multi-stage switch further includes a core switch module operatively connected to receive the wavelength division multiplexed signal from the at least one ingress switch module and to switch the frames. The multi-stage switch additionally includes at least one egress switch module to receive the wavelength division multiplexed signal from the core switch module and to transmit data. The at least one ingress switching module and the at least one egress switching module are capable of replicating multicast data packets.Type: GrantFiled: January 27, 2005Date of Patent: April 14, 2009Assignee: Intel CorporationInventor: Anujan Varma
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Patent number: 7496100Abstract: A method and apparatus for synchronous frame communication first communicates a frame signal having communication data and first control information having a bit length and an SDH frame structure in a part of frame time interval and a control information processing method based on an SDH-frame-overhead-process for processing the first control information that includes bytes indicative of each of a relay node's section overhead, an end terminal section overhead, and at least a part of a byte of higher path's overhead. In the frame time interval a signal is communicated by a different second communicating method having the communication data and second control information having a bit length capable of including a significantly higher amount of information than that of the first control information and which corresponds to the first control information byte communicated in the frame time interval.Type: GrantFiled: April 17, 2001Date of Patent: February 24, 2009Assignee: Nippon Telegraph & Telephone CorporationInventors: Kenji Kawai, Osamu Ishida, Haruhiko Ichino
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Patent number: 7486669Abstract: A method and system for enabling a multi-stage switch to be adapted for single-stage switch applications. An interface manager manages the hardware interface for the multi-stage switch. The multi-stage switch includes input ports and output ports, and an input signal can be broadcast to one or more output ports. The interface manager limits the broadcasting of each input signal to avoid a blocking condition within the multi-stage switch which causes the blocking of one or more of the broadcast signals.Type: GrantFiled: June 1, 2004Date of Patent: February 3, 2009Assignee: Nortel Networks LimitedInventor: Christopher Brown
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Publication number: 20090028140Abstract: A switching device includes an input stage switch group 1-1 including a plurality of input lines, an output stage switch group 1-3 including a plurality of output lines, an intermediate stage switch group 1-2 arranged between the input stage switch group and the output stage switch group, and a scheduler 1-22 deciding a signal path of each of intermediate stage switches 1-21 in the intermediate stage switch group based on information input to the respective input lines. The intermediate stage switch group is divided into a plurality of groups, a plurality of the schedulers is arranged in a distributed fashion to correspond to the plurality of groups, respectively and the schedulers operate independently of one another.Type: ApplicationFiled: June 2, 2006Publication date: January 29, 2009Applicant: NEC CorporationInventors: Junichi Higuchi, Youichi Hidaka, Mikiharu Yamashita, Yukihiro Hara
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Publication number: 20090016332Abstract: To exchange data between adjacent nodes at high speed while using an existing network including a fat tree and a multistage crossbar switch. This invention provides a parallel computer system including: a plurality of nodes each of which includes a processor and a communication unit; a switch for connecting the plurality of nodes with each other; a first network for connecting each of the plurality of nodes and the switch; and a second network for partially connecting the plurality of nodes with each other. Further, the first network is comprised of one of a fat tree and a multistage crossbar network. Further, the second network partially connects predetermined nodes among the plurality of nodes directly with each other.Type: ApplicationFiled: January 29, 2008Publication date: January 15, 2009Inventors: Hidetaka Aoki, Yoshiko Nagasaka
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Patent number: 7468974Abstract: A Forward Propagation Architecture is a novel switch architecture based on well-known unicast switching architectures, and provides two desirable properties: (1) no rearrangement of established calls is ever required and (2) the architecture is strictly non-blocking for multicast, even when multicast destinations are dynamically added to existing calls. These properties (excluding dynamic multicast destination addition) can be provided by standard architectures or Time:Space:Time architectures with speedup proportional to the width of the widest multicast to be supported. The speedup required by the FPA is constant and practical (approximately 4× speedup) and at significantly less hardware cost than n2 architectures. The key to the FPA's capability is a sequentially doubled fabric with a feedback loop. The FPA requires a routing algorithm for connection setting. The connection-setting algorithm is sufficiently simple to be implemented in hardware.Type: GrantFiled: September 22, 2004Date of Patent: December 23, 2008Assignee: PMC-Sierra, Inc.Inventors: Larrie Simon Carr, Winston Ki-Cheong Mok, Kenneth Evert Sailor
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Patent number: 7463626Abstract: Methods and apparatus for phase and frequency drift and jitter compensation in a distributed switch which carries both TDM and packet data are disclosed. The methods include the insertion of programmable fill times at different stages of the switch to allow buffers to fill, driving service processors (line cards) with different clocks and synchronizing the service processors (line cards) to the switch fabric, providing redundant switch fabric clocks and methods for automatically substituting one of the redundant clocks for a clock which fails, providing redundant switch fabrics each having a different clock and methods for automatically substituting one switch fabric for the other when one fails. The apparatus of the invention includes a plurality of service processors (line cards), switch elements and clock generators. An exemplary clock generator based on an FPGA is also disclosed.Type: GrantFiled: May 24, 2002Date of Patent: December 9, 2008Inventors: Subhash C. Roy, David K. Toebes, Michael M. Renault, Steven E. Benoit, Igor Zhovnirovsky
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Patent number: 7460529Abstract: An interconnection fabric using switching networks hierarchically to allow interconnections of large number of a first plurality of conductors to a large number of k plurality of conductors is described. The resulting interconnection fabric can be used in switching networks, routers and programmable logic circuits.Type: GrantFiled: July 29, 2004Date of Patent: December 2, 2008Assignee: Advantage Logic, Inc.Inventors: Peter M. Pani, Benjamin S. Ting
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Patent number: 7447198Abstract: In a communication network system having a multi-switch Fiber Channel fabric, adjacent switches are communicatively coupled together by a plurality of links. The links are selectively determined to join a trunked group for enabling frames received at one switch to be routed over the links in the trunked group to the adjacent switch in an evenly distributed manner. In one embodiment, a link within the trunked group is coupled to a pair of ports residing on adjacent switches each having a designated trunking master port. The traffic load at one switch is routed through the trunking master port which distributes the load across multiple links and guarantees that the load is received at the adjacent switch with “in-order” delivery.Type: GrantFiled: June 1, 2001Date of Patent: November 4, 2008Assignee: Brocade Communications Systems, Inc.Inventors: David C. Banks, Kreg A. Martin, Shunjia Yu, Jieming Zhu, Kevan K. Kwong
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Patent number: 7443843Abstract: An apparatus has a cross connection circuit, first switching sections located on the input side of the cross connection circuit to switch a presently-used transmission path and a reserve transmission path, and second switching sections located on the output side of the cross connection circuit to switch the presently-used transmission path and the reserve transmission path and comprises slot sections, first selecting section selectively connecting any one of the slot sections to the input side of the first switching section, second selecting section connecting the output side of the first switching section to the input side of the cross connection circuit, third selecting section selectively connecting the output side of the cross connection circuit to the input side of any of the second switching sections, and fourth selecting section connecting the output side of the second switching section to any one of the slot sections.Type: GrantFiled: April 6, 2005Date of Patent: October 28, 2008Assignee: Fujitsu LimitedInventors: Hiroyuki Matsuo, Mitsuhiro Kawaguchi, Shosaku Yamasaki, Takashi Umegaki, Koji Komatsu, Yoshimasa Itsuki
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Patent number: 7443844Abstract: A switched fabric mezzanine storage module (560) includes a storage module (562) and a switched fabric connector (563) coupled to the storage module. The storage module is coupled to directly communicate with a switched fabric (506), where the switched fabric storage mezzanine module is coupled to a payload module (502) having one of a 3U form factor, a 6U form factor and a 9U form factor. The payload module can include at least one multi-gigabit connector (518) coupled to a rear edge (519) of the payload module, where the at least one multi-gigabit connector is coupled to communicatively interface with a backplane (504).Type: GrantFiled: September 23, 2004Date of Patent: October 28, 2008Assignee: Emerson Network Power - Embedded Computing, Inc.Inventors: Douglas L. Sandy, Jeffrey M. Harris, Robert C. Tufford
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Publication number: 20080259914Abstract: An apparatus and method for providing a primary and a secondary protection to a load in a power switching application uses an electronic circuit breaker to selectively permit a flow of current from an input to a load. The circuit breaker comprises a plurality of first switches coupled in parallel, and a plurality of fuses coupled to the plurality of first switches. In a disclosed embodiment, each first switch is coupled to a first fuse and to a second fuse. A controller opens and closes the plurality of first switches by commanding a driver current ON and OFF. The controller is operable to detect a fault condition and to open the plurality of first switches in response to the fault condition by commanding the driver current OFF. If the controller fails to open one of the first switches, one of the fuses coupled to the switch is operable to blow.Type: ApplicationFiled: April 17, 2007Publication date: October 23, 2008Inventors: Norbert J. Simper, Martin Bach
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Patent number: 7440449Abstract: A compact multi-stage switching network (100), and a router (510) incorporating such multi-stage switching network, adapted for simultaneously routing a plurality of data packets from a first plurality of input ports (110) to selected ones of a second plurality of output ports (190) comprising: a first stack (140) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer containing at least one switching element circuit (142); a second stack (160) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer (113) containing at least one switching element circuit (162); and interconnecting circuitry (150) that connects the first stack (140) of IC layers to the second stack (160) of IC layers to form the compact multi-stage switching network. The stacks (140, 160) are preferably mated to one another in a transverse fashion in order to achieve a natural full-mesh connection.Type: GrantFiled: October 6, 2004Date of Patent: October 21, 2008Assignee: Irvine Sensors Corp.Inventors: John C. Carson, Volkan H. Ozguz
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Patent number: 7440450Abstract: A multi-service platform system, includes a backplane (104), a switched fabric (106) on the backplane, and at least one of a VMEbus network and a PCI network coincident with the switched fabric on the backplane. A payload module (102) has one of a 3U form factor, a 6U form factor and a 9U form factor, where the payload module is communicatively coupled with the backplane using the switched fabric and at least one of the VMEbus network and the PCI network. At least one multi-gigabit connector (118) is coupled to a rear edge (119) of the payload module, where the at least one multi-gigabit connector is coupled to communicatively interface the payload module to the backplane, and where the switched fabric and at least one of the VMEbus network and the PCI network are communicatively coupled with the payload module through the at least one multi-gigabit connector.Type: GrantFiled: September 23, 2004Date of Patent: October 21, 2008Assignee: Emerson Network Power-Embedded Computing, Inc.Inventors: Jeffrey M. Harris, Douglas L. Sandy, Robert C. Tufford
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Patent number: 7426205Abstract: An Ethernet switch has a header device with a crossbar device and a number of downstream interface modules with a first number of a series of ports and a second number of a series of ports, respectively, such that in each case the same one in the series of the first number of ports is connected to a switching control unit coupled to an interface device, and the further ports in the series of the first number of ports are connected to a port in the second number of the series of ports via respective data lines routed in cascade form.Type: GrantFiled: October 16, 2003Date of Patent: September 16, 2008Assignee: Phoenix Contact GmbH & Co. KGInventors: Kai Fechner, Jürgen Jasperneite, Martin Müller
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Patent number: 7424010Abstract: In one embodiment, a controller is configured to establish a new multicast connection within a network without changing a path of an existing multicast connection within the network. The network can have an input stage having a total of at least n1*r1 inlet links, an output stage including r2 output switches, and n2 outlet links for each of said r2 output switches for a total of at least n2*r2 outlet links, and a middle stage including m middle switches, where m?s*Min(n1,n2) and where s=2 when r2=[9,11], s=3 when r2=[25,48], s=4 when r2=[49,99, s=5 when r2=[100,154], s=6 when r2=155,224], and s=7 when r2=[225,278 ]. The new multicast connection from an inlet link from the n1*r1 inlet links passes through at most s middle switches.Type: GrantFiled: September 5, 2004Date of Patent: September 9, 2008Assignee: TEAK Technologies, Inc.Inventor: Venkat Konda
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Patent number: 7424011Abstract: A rearrangeably nonblocking multicast network includes an input stage having r1 switches and n1 inlet links for each of r1 switches, an output stage having r2 switches and n2 outlet links for each of r2 switches. The network also has a middle stage of m switches, and each middle switch has at least one link connected to each input switch for a total of at least r1 first internal links and at least one link connected to each output switch for a total of at least r2 second internal links, where m?n1+n2. The network has all multicast connections set up such that each multicast connection passes through at most two middle switches to be connected to the destination outlet links.Type: GrantFiled: November 27, 2004Date of Patent: September 9, 2008Assignee: Teak Technologies, Inc.Inventor: Venkat Konda
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Publication number: 20080212577Abstract: A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.Type: ApplicationFiled: February 19, 2008Publication date: September 4, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Francois Abel, Gottfried Andreas Goldrian, Ingemar Holm, Helmut Kohler, Norbert Schunacher
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Patent number: 7420968Abstract: A system of switch modules contains input demultiplexers connected to ports on each of the modules and output multiplexers connected to each of the modules. Each module has output and input interfaces for mesh links and at least one output interface is looped back to an input interface on the same module. The arrangement reduces module-to-module traffic and corresponding increases the transmit bandwidth of a module.Type: GrantFiled: June 6, 2003Date of Patent: September 2, 2008Assignee: 3Com CorporationInventors: Bryan J. Donoghue, Richard A. Gahan, Kam Choi, Edele O'Malley, Eugene O'Neill
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Patent number: 7420970Abstract: A read port for selectively coupling one of a plurality of inputs to an output is disclosed. The read port comprises: a plurality of inputs; an output; a plurality of multiplexers operable to selectively couple a selected input to said output; and a multiplexer control signal input for inputting a multiplexer control signal, the multiplexer control signal comprising a plurality of control parameters and being operable to control switching of the plurality of multiplexers. The plurality of multiplexers are arranged in a plurality of layers, the layers being arranged between the inputs and output, such that a selected input is operable to be coupled to the output via a multiplexer from each of the different layers.Type: GrantFiled: June 16, 2003Date of Patent: September 2, 2008Assignee: ARM LimitedInventor: Andrew Christopher Rose
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Patent number: 7420969Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.Type: GrantFiled: August 24, 2001Date of Patent: September 2, 2008Assignee: RMI CorporationInventors: Kai-Yeung (Sunny) Siu, Brain Hang Wai Yang, Mizanur M. Rahman
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Patent number: 7406075Abstract: A small cost-effective crossbar switch is provided. A switch circuit is disposed in each of a plurality of nodes which are cascade connected with each other in a plurality of stages. Each switch circuit receives from a node of a previous stage a designated address to specify directly or indirectly the relative position in which a target switch circuit is present, determines whether the designated address represents a specific value “0”. When it is determined that the specific value is represented, each switch circuit allows data output to a node-out line, decrements the received designated address by “1” to generate a new designated address, and supplies this new designated address to a node of the subsequent stage.Type: GrantFiled: March 22, 2004Date of Patent: July 29, 2008Assignee: Sony Computer Entertainment Inc.Inventors: Junichi Naoi, Tomohiro Ohto