Abstract: Accelerated protection switching in a multi-platform network switch may be achieved by allocating connectivity slots from the port cards to the switch cards for all states of a connection through the switch and forming maps of the allocations for use by the port cards and switch cards. By allocating connectivity slots to all states of the connection, the connection will not be blocked in connection with a state change. By storing the slot allocation in maps a connection state change may be implemented by the switch by causing traffic on the connection to be transported using the allocated slots. Various protection modes can use the same connectivity slots with collision avoidance via prepared maps Thus, having predefined paths via allocated slots provisioned through the network element enables the network element to switch very quickly from working to protection to comply with applicable standards and minimize disruption of network traffic.

Abstract: A switching device includes multiple interfaces and a switch fabric. The switch fabric includes switch integrated circuits arranged in a number of stages. Multiple virtual switch planes may be implemented in the switch fabric. Data traffic received at the interfaces is selectively assigned to different ones of the virtual switch planes.

Abstract: Multiplexer to transmitter interface protocol. A method for a data interface protocol is provided that includes receiving a first packet stream having at least one overhead information symbol (OIS) group and at least one multicast logical channel (MLC) group, and mapping each OIS group to an OIS descriptor packet and at least one OIS payload packet. The method also includes mapping each MLC group to an MLC descriptor packet and at least one MLC payload packet, and outputting the OIS descriptor, OIS payload, MLC descriptor, and MLC payload packets in a second packet stream. An apparatus includes input logic to receive the first packet stream, processing logic to map each OIS group to an OIS descriptor packet an OIS payload packet, and each MLC group to an MLC descriptor packet and an MLC payload packet, and output logic to output the mapped packets in a second packet stream.

Abstract: A network structure configures a blocking network having constraint against such a combination of said network input terminal and network output terminal as to make it unfeasible to further connect, when connecting first network input terminals to first network output terminals, second network input terminals to any one of the second network output terminals, and operation elements and the network output terminals are connected so as to minimize a constraint strength between the plurality of network output terminals inputting to the same operation element with respect to the constraint strength defined as the number of network input terminals contained in tuples of network input terminals to which the two network output terminals in the network output terminals can not be simultaneously connected.

Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.

Abstract: A cross-point switch fabric slice (100) includes multistage gated buffer tree (135) incorporating at least first and second serially connected gated buffer stages (136, 138). N inputs (102-116) connect to preselected gated buffers (146-160) in the first gated buffer stage (136). The multistage gated buffer tree provides a signal path from any of the N inputs (102-116) to at least one switch output (118) in response to gated buffer stage control signals for the first gated buffer stage (136) and gated buffer stage control signals for the second gated buffer stage (138). Generally, the number of gated buffers decreases from that of the previous stage. As an input signal propagates through the cross-point switch fabric slice (100), longer internal connections are driven by more capable buffers.

Abstract: A three-stage network is operated in strictly nonblocking manner and includes an input stage having r1 switches and n1 inlet links for each of r1 switches, an output stage having r2 switches and n2 outlet links for each of r2 switches. The network also has a middle stage of m switches, and each middle switch has at least one link connected to each input switch for a total of at least r1 first internal links and at least one link connected to each output switch for a total of at least r2 second internal links, where m?2*n1+n2?1. In one embodiment, each multicast connection is set up through such a three-stage network by use of at most two switches in the middle stage.

Abstract: A k-source N1×N2 nonblocking multicast switching network has N1 input ports and N2 output ports with each port having k independent channels, in which each input channel can perform a multicast connection, i.e. send data simultaneously to multiple output channels, without interrupting existing multicast connections from other input channels. We provide the construction and the routing algorithm of a multi-source nonblocking multicast three-stage switching network. A k-source N1×N2 such a switching network consists of three stages of switch modules (which are k-source multicast switching networks with smaller sizes). It has r1 k-source n1×m switch modules in the input stage, m k-source r1×r2 switch modules in the middle stage, and r2 k-source m×n2 switch modules in the output stage with N1=n1r1 and N2=n2r2. There are exactly k channels (corresponding to one port of k-source switch module) between every two switch modules in two consecutive stages.

Abstract: A technique for provisioning cross-connects in network switching environment includes receiving a portion of the an input data stream including having header data and the payload data, the payload data occurring at a first offset relative to the header data and generating a delayed version of the portion of the input data stream. The technique also includes generating a portion of a retimed data stream by selecting between the portion of the input data stream and the delayed version of the portion of the input data stream, the retimed data stream including the header data and the payload data, the payload data occurring at a second offset relative to the header data.

Abstract: An apparatus for switching data between a first set of bitstreams and a second set of bitstreams, each of said bitstreams being divided into recurring frames and each of said recurring frames being divided into time slots, is disclosed. The switch comprises a first set of switching elements, at least one intermediate set of switching elements, and a last set of switching elements. Each switching element comprises a number of input ports and a number of output ports. The input ports of the first set of switching elements are arranged to receive the first set of bitstreams and the output ports of the last set of switching elements are arranged to provide said second set of bitstreams. Furthermore the switching elements are arranged so that there are more than one path from a switching element in the first stage to a switching element in the last stage.

Abstract: The present invention relates to a buffered crossbar switch and its method of operation which provides a step of changing the size and/or number of queuing buffer entries to ensure optimum buffer memory usage independent of the size of data packets processed.

Abstract: A scheduling algorithm is provided that may be implemented in a multi-stage switch requiring less switching elements than known switching architectures in order to increase bandwidth and to retain the non-blocking properties of the constituent switching elements for incoming traffic, including multicast traffic. A scheduling algorithm is also provided for incremental scheduling of connections being added or removed from the switch.

Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.

Abstract: A method and system of assigning paths through an interconnection network (100) consisting of a plurality of switching elements (102:165) and a plurality of links coupling the switching elements (102:165) are provided. Physical restrictions of the interconnection network (100) are used to arrive at a logical representation of an architecture of the interconnection network (100). Traffic patterns of the interconnection network (100) are determined to balance the data traffic through the links coupling the switching elements (102:165). The logical representation and traffic patterns of the interconnection network (100) are used to setup virtual channel identifiers that determine paths through the switching elements and links so that data traffic is more evenly distributed through the interconnection network (100).

Abstract: A method and apparatus for processing a data signal for transmission to a remote device transmits at least two synchronized copies of the data signal, in optical form, in different directions. To that end, the data signal first is synchronized to a clock signal to produce a composite signal. The composite signal then is converted to an optical signal, which is referred to as an “outgoing signal.” A plurality of copies of the outgoing signal then are transmitted. At least two copies of the outgoing signal are transmitted in different directions.

Abstract: A method for maintaining a quality of service in a wireless communication network is introduced. A reservation is created in a first data path between a home agent and a first foreign agent for data flow between the home agent and a wireless terminal. When the wireless terminal associates with a second foreign agent, a quality of service supportive second data path may be created between the first foreign agent and the second foreign agent. The data flow may be routed over the first and second data paths to maintain the quality of service for the data flow. A wireless communication network may include first downstream and reverse tunnels coupling a home agent and a first foreign agent, each tunnel having a reservation to maintain a quality of service. Second downstream and reverse tunnels may couple a home agent and a second foreign agent.

Abstract: Roughly described, a striping algorithm selects a route on which to transmit each next data segment, pseudorandomly from among a subset of eligible routes, the subset being chosen in dependence upon relative channel loading so far. Preferably each ingress node to a switching system chooses an outgoing route for each given next data segment, according to a pseudorandom algorithm, from among a respective given subset containing only those routes via which the amount of data sent from the ingress node during a respective prior time period is no greater than an average of the amount of data sent from the ingress node via any of its outgoing routes during the same prior time period.

Abstract: A method of modeling or constructing a switch element uses an ingress stage with input sorters and input routers; an egress stage with output routers and output sorters; and a center stage interconnecting the ingress and egress stages. Routers are partitioned such that each partition is assigned to only one data line. A switch controller and method may use such modeling to advantage. For example, during initial configuration of the switch element, a subset of connections are excluded from a control algorithm that initially configures the switch with the subset being subjected to post processing. Furthermore, a fast rearrangement of the switch rearranges only part of the existing connections and then adds/deletes cross connects as necessary to complete the connections.

Abstract: Topology discovery and identification of switches enables a user to determine the topology of a three-stage switch network. The method includes ascertaining an intended topology of the three-stage switch network, creating a list of switch boards that are present in the three-stage switch network, and determining a switch board connection pattern by obtaining information indicating how each switch board is connected to neighboring switch boards. The method further includes classifying each of the switch boards on the list of switch boards as a node switch board, an intermediate switch board, or a jump switch board, and creating a list for each type of switch board. The method further includes grouping the intermediate and node switch boards into sectors, and numbering each type of switch board, thereby obtaining a determined topology, and validating the determined topology by comparing it to the intended topology.

Abstract: A digital cross-connect switching system that has a single-stage architecture, a scalable bandwidth, and reduced connection memory storage requirements. The scalable bandwidth digital cross-connect switching system includes a plurality of digital cross-connect building blocks. Each digital cross-connect building block includes at least one cross-connect having a plurality of input ports and a plurality of output ports, at least one connection memory communicatively coupled to the cross-connect, and at least one OR gate. Bandwidth is scaled in the digital cross-connect switching system by interconnecting predetermined numbers of the digital cross-connect building blocks. In general, the size of the digital cross-connect switching system increases as the square of the bandwidth requirement.

Abstract: A service creation switch (114) supports both tightly coupled and loosely distributed application server (AS) (126) functions, with the tightly coupled AS (126) functions residing in the switch (114), and the loosely coupled AS (126) functions carried out in a service level executable environment (SLEE) (34). The SLEE (134) utilizes DLLs to facilitate the distribution of services over a packet network.

Abstract: A method for wireless remote control of a device is provided. In one embodiment, the method includes: transmitting a current data message to the device, the current data message including at least one data bit to control movement associated with a first positional characteristic of the device; detecting and receiving the current data message at the device; in response to a first state of the at least one data bit, energizing a first positional actuator associated with the first positional characteristic; and de-energizing the first positional actuator after not detecting a next data message within a predetermined time after having received the current data message. In this embodiment, the predetermined time is greater than a minimum time between transmission and detection of consecutive data messages, but less than ten times the minimum time between transmission and detection of consecutive data messages.

Abstract: A method for determining a combination of data for transfer comprises counting the number of candidates in data for candidates of a data transfer request for each row as the number of candidates at lattice points of a lattice composed of N rows×N columns, searching for a minimum value out of count values equal to or greater than 1, selecting and storing one row showing the minimum value. Regarding the candidates in the selected row, the method also comprises counting the number of candidates in each column where candidates exist, searching for a minimum value, selecting and storing one column, deleting all candidates on the row and the column determined, and repeating these processes until no more candidates exist to determine combinations of rows and columns stored at a point of time when no more candidates exist.

Abstract: There is disclosed an QoS-oriented burstification method supporting various grades of burstification delay guarantee. For the arrival packets, the packets are sequentially inserted in a sequence of windows on weight basis, thereby forming a queue. The window size together with the weight of each flow determines a maximum number of packets of each flow in a window. For the departure packets, there is generated a burst consisting of a plurality of packets from the head of the queue when either a total number of packets reaches a maximum burst size or a burst assembly timer expires.

Abstract: A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized data frame. Both the configuration data and a frame clock may be propagated through the plural stages from a master switch. First and last stages of the digital cross connect may be implemented on common chips having two framing time bases. Data may be aligned to a global frame clock and interchanged using a single random access memory in a time slot interchanger. The write address to the random access memory is generated from a local frame counter keyed to the input data frame while a read address is transformed from a global frame counter.

Abstract: A technique for accommodating packets of different lengths at minimal cost to hardware complexity with a self-routing switch primitive with an associated switching mechanism that accommodates packets of different lengths encapsulated in a new packet format. The switch primitive, along with a new packet format, effects the self-routing such packets through a switching fabric constructed from the interconnection of the self-routing switching primitives.

Abstract: A multicast concentrator to both concentrate and multicast packets, and the concomitant self-routing control mechanism for the switching of the packets in the multicast concentrator. An m-to-n multicast concentrator always guarantees that the total number of 0-bound and bicast signals routed to its 0-output group and the total number of 1-bound and bicast signals routed to its 1-output group are both the maximum possible. An m-to-n multicast concentrator can be easily adapted from an m-to-n concentrator by replacing each of the sorting cells in the concentrator by a bicast cell.

Abstract: A router has N1 local signal input terminals for connection to respective local signal sources for supplying respective local input signals, a local output interface including M1 local signal output terminals, and an input expansion terminal. A signal received at any one of the N1 local signal input terminals can be routed selectively to any one or more of the M1 local signal output terminals and a signal received at the input expansion terminal can be routed selectively to any one or more of the M1 local signal output terminals. An input signal received at a local signal input terminal is delayed relative to an input signal received at the input expansion terminal by a selectively adjustable amount to achieve a predetermined time relationship between the input signals at the local output interface.

Abstract: A cross connect switch has a plurality of stages. Each stage has a plurality of packers, a plurality of memory portions and a plurality of multiplexers. Each packer receives input data and provides the input data as a set of contiguous valid data. The multiplexers divide the valid data from one of the packers into a plurality of data subsets and route each data subset to a respective memory portion of that stage. Each stage except the final stage provides the data in the memory portions of that stage as a respective set of inputs to a next one of the stages. The final stage includes a plurality of multiplexers for selecting a respective subset of the data from each of the memory portions of the final stage and provides the selected data at a plurality of respective selected output ports.

Abstract: A content addressable merged queue (camQ) architecture for high-speed switch fabrics reduces the memory requirement for crossbar switch input and output queues using memory cells and age tag comparators. CamQ emulates VOQ FIFO for each supporting priority, eliminating HOL blocking. Multiple QoS levels are supported cost effectively at higher traffic bandwidth limits. Content addressable memory (CAM) cells store payload destinations, which can be addressed by cell priorities. Once a priority for QoS is decided, all the cells with the selected priority in the payload can make connection requests to destination ports directly through the CAM structure. An age tag is assigned to incoming cells and fast age tag comparators provide FCFS features by selecting the oldest cell. Small memory sizes prevent the bottlenecking in ingress and egress queues. A CIOQ crossbar has a fast switching speed, emulating a FIFO output queue switch. Age and priority are interleaved to schedule switching.

Abstract: An analog Ethernet detector determines if an IEEE 1394b long haul application using Category 5 (CAT 5 UTP) cable, is connected to an Ethernet which share certain pins of the RJ45 connector used to connect devices to the CAT 5 cable. The detector does not require a processor core or clocking and can be built as a completely analog device.

Abstract: A channel data extracting circuit for extracting data for each channel from a frame in which byte data of channels are multiplexed includes a Banyan unit and data control unit. The Banyan unit distributes data for respective channels by Banyan switches of planes corresponding to the channels, and sequentially aligns word data. The data control unit transmits to the Banyan unit a control signal representing a channel to which data belongs, and controls the operations of the Banyan switches. A channel data extracting method is also disclosed.

Abstract: A system for switching packets in a high-speed switching environment includes one or more memory structures, multiple input structures that can each write to each of the one or more memory structures, and a first switching structure that couples the input structures to the one or more memory structures. The system also includes multiple output structures that can each read from each of the one or more memory structures and communicate a first portion of a packet to a first component of a communications network before an input structure has received a second portion of the packet from a second component of the communications network. The system also includes a second switching structure that couples the plurality of output structures to the one or more memory structures.

Abstract: An intelligent routing and switching system includes an interface for coupling said system to an external network and a switch fabric for selectively routing bits of data being exchanged with an external network through the interface. The switch fabric includes an array of multiport switching elements each including switches and memory elements for introducing programmable delays in selected ones of the bits being routed. The routing and switching system further includes a first controller for implementing a routing table and scheduler in accordance with a sequencing graph to route bits of data through the switch fabric and a second controller for generating the sequencing graph and for allocating input and output slots for inputting and outputting data through the interface.

Abstract: A network or interconnect structure which includes a plurality of nodes which are interconnected within a hierarchical multiple level structure. The level of each node is determined by the position of the node within the structure and data messages move from node to node from a source level to a destination level. Each node within the interconnect structure is capable of receiving simultaneous data messages at its input ports from any other node and the receiving node is able to transmit each of the received data messages through its output ports to separate nodes in the interconnect structure to one or more levels below the level of the receiving node.

Abstract: An architecture for a high bandwidth digital cross-connect switching system that is internally non-blocking, has a simpler layout, and employs a reduced number of logic gates. The high bandwidth digital cross-connect switching architecture comprises a Time Division Multiplexing (TDM) cross-connect including M space/time switches. Each space/time switch includes an input bus, an output bus, N×W Flip-Flops (FFs) for storing input data, W N-by-N switches for sorting the data according to predetermined cross-connection requirements, and N×W FFs for storing output data, in which “N” corresponds to the number of input ports and the number of output ports in the N-by-N switch, and “W” corresponds to the width of each data word. Each N-by-N switch includes N×W N-to-1 selectors, and the M space/time switches include N×W M-to-1 selectors, thereby allowing an effective N×M-to-1 selection to be performed on the data words.

Abstract: The present invention provides an apparatus, system and method of increasing port availability for a communication switch. First, second and third M port crossbars are arranged to provide a crossbar with a increased number of ports available for the communication switch. K ports of a first M port crossbar are individually coupled to K ports of a second and a third M port crossbar via interconnect buses. Further, K ports of the second and third M port crossbars are individually coupled via interconnect buses resulting in L available ports on each the M port crossbars in which M>L>K.

Abstract: A switch is provided that receives user information through a plurality of framer circuits, which group the user information into frames. The frames are fed to a switch fabric including an array of switch elements, each having a switch matrix for routing each frame to a desired output in accordance with configuration data stored in a first table coupled to the switch matrix. If different outputs are desired, i.e., the switch matrix is to be reconfigured, a switch control circuit supplies additional switch configuration data to the frames through the inputs along with additional user information to be routed through the switch. While the additional switch configuration data is stored in a second table, data flow remains uninterrupted through the switch matrix.

Abstract: A switch with tandem ports and an outlet assembly permit individual segments of cable to be used with multiple data link protocol standards. The multiple data link protocols can be used either one at a time, with each group of wires in the cable carrying the same data link protocol in different communication sessions, or can be used in tandem, with each group of wires in the cable simultaneously carrying a different data link protocol.

Abstract: A method of constructing a permuting network. A configuration for layers of a permuting network is selected based on a set of integer factors of N, the number of signals to be permuted, and on pre-selected types of switches. The permuting network is constructed in layers by using the pre-selected types of switches based on the selected configuration.

Abstract: A multiple phase cell dispatch scheme, in which each phase uses a simple and fair (e.g., round robin) arbitration methods, is described. VOQs of an input module and outgoing links of the input module are matched in a first phase. An outgoing link of an input module is matched with an outgoing link of a central module in a second phase. The arbiters become desynchronized under stable conditions which contributes to the switch's high throughput characteristic. Using this dispatch scheme, a scalable multiple-stage switch able to operate at high throughput, without needing to resort to speeding up the switching fabric and without needing to use buffers in the second stage, is possible. The cost of speed-up and the cell out-of-sequence problems that may occur when buffers are used in the second stage are therefore avoided.

Abstract: A switch fabric for routing data has a switching stage configured between an input stage and an output stage. The input stage forwards the received data to the switching stage, which routes the data to the output stage, which transmits the data towards destinations. In one aspect, at least one input port can be programmably configured to store data in two or more input routing queues that are associated with a single output port, and at least one output port can be programmably configured to receive data from two or more output routing queues that are associated with a single input port. In another aspect, the output stage transmits status information about the output stage to the input stage, which uses the status information to generate bids to request connections through the switching stage.

Abstract: A grooming switch comprises plural input ports for receiving multi-time-slot input signals and plural output ports for forwarding multi-time-slot output signals. At least five switching stages alternate between time switching and space switching. The first stage is connected to the input ports, and the last stage is connected to the output ports. Each intermediate stage is connected to two other stages. Collectively, these stages perform compact superconcentration of the input signals, copying and distribution of the compact superconcentrated signals, and unicast switching of the distributed signals to form the output signals, resulting in a grooming switch that is rearrangeably non-blocking for arbitrary multicast traffic.

Abstract: Optical equalization across N (an integer, N>1) channels of a multi-channel link of a communications network, is accomplished by averaging effects of optical performance variations within each of the M (an integer, M>1) parallel data signals. At a transmitting end node of the link, each one of the M data signals are distributed across the N channels of the link. Thus a substantially equal portion of each data signal is conveyed through the link in each one of the N channels. At a receiving end node of the link, respective bit-streams received over the N channels to are processed recover the M data signals. As a result, bit error rates of the bit-streams received through each channel are averaged across the M data signals, all of which therefore have a substantially equal aggregate bit error rate.

Abstract: Equivalence among bit-permuting networks and the mechanisms for the conversion between equivalent networks. Multistage switching networks in the bit-permuting type and banyan-type can be classified into equivalence classes. One network can usually be replaced by another equivalent network in certain applications. This widens the choices of networks in meeting different requirements in applications.

Abstract: A method and apparatus for the transmission of data through multiple clock domains using synchronous and asynchronous FIFOs are described. In an embodiment, a method includes receiving data at a first data transfer rate. Additionally, the method includes storing the data at the first data transfer rate in a synchronous storage device having a first storage area. The data at the first data transfer rate stored in the synchronous storage device is processed. The processing includes removing the data from the synchronous storage device. The processing also includes storing the data at the first data transfer rate in an asynchronous storage device having a second storage area. Additionally, the processing includes transmitting the data out from the asynchronous storage device at a second data transfer rate, wherein the storage area of the synchronous storage device is larger than the second storage area of the asynchronous storage device.

Abstract: An apparatus comprising a distributed multiplexer configured to receive a distributed input group of signals. The distributed multiplexer may be configured to evenly load the distributed input groups.

Abstract: Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.

Abstract: A multicast connection scheduling method for a 3-stage switch fabric with n1 first stage, n2 second stage and n3 third stage interconnected switching devices. The first and third stage devices are non-blocking for unicast connections. The center stage devices are non-blocking for multicast connections. Load tables are provided for each center stage device, with one row per first and/or third stage device. Each row represents the number of connections being serviced between the first and/or third stage devices, through the center stage device corresponding to the table. By monitoring and updating the tables, the invention derives an approximately optimal connection schedule for an input list of connection requests, such that no input connection load exceeds any center stage device's maximum input connection load capacity and no output connection load exceeds any center stage device's maximum output connection load capacity.

Abstract: A redundant multistage network can be expanded by width in a non-stop manner, involving an insertion, a reconfiguring and an activation section. The insertion section involves adding a router to each row of routers in a position dictated by the specific upgrade procedure. The reconfiguring section involves the selection of a port and disconnecting any connections necessary to connect that port with its proper corresponding port as derived from the final desired topology. This section can further include the optional permutation of port address to minimize traffic disruption. The activation section involves attaching any new external ports desired to external sources and putting those new connections into service.