Abstract: In a butterfly network, a number of switches are set to provide two paths that are independent of each other, from a first switch to a second switch, and from the first switch to a third switch respectively. Identification of switches to be set from among all switches in the butterfly network depends on the locations of the first switch, the second switch and the third switch relative to one another. The to-be-set switches are determined by starting with the first switch as a preceding switch, identifying the next switch for a path by simply changing the level number (e.g. incrementing the level number) of a preceding switch in the path, and by changing a bit of the row number of the preceding switch (e.g. by replacing the ?-th bit with a corresponding bit from the destination switch's row number), and repeating such acts with the just-identified switch as a preceding switch. The direction of the path is reversed on reaching a last level or a last row of the network.

Abstract: A switching device comprises at least two base racks, each base rack including a switch card in communication with a line card across a backplane, the line card having at least an external port. The at least two base racks are coupled such that the switch cards of each are linked. A method for switching a packet comprises introducing the packet into an external port on a first base rack, transmitting the packet from a first cascade port on the first base rack to a second cascade port on a second base rack, and sending the packet out of the second base rack through a second external port.

Abstract: A switch element is configured to extend communications between data lines. The switch element includes a set of ingress devices, a set of center stage devices, and a set of egress devices. Each center stage device is connectable to each ingress device and to each egress device. Each ingress device connects to a corresponding egress device across one of the center stage devices. The center stage switch can be selectively actuated to accommodate a new ingress or egress device across the center stage switch.

Abstract: The present invention overcomes drawbacks with on-site, manual configuration of IP addresses for network nodes (like newly-installed base stations) with a method to automatically assign an identifier like a packet data address to a new node. In general., the automatic assignment of such an identifier to a network entity, node, or host includes two steps. First, an initial message is transmitted by the entity which specifies or indicates in some way geographical location information for the entity. Second, using the geographical location information in that message, an identifier is assigned and provided to that entity. In other words, a relationship is established between the geographical location of an entity identifier and its associated identifier. The geographical location information uniquely identifies the entity in the automatic identifier assignment process.

Abstract: A multiple phase cell dispatch scheme, in which each phase uses a simple and fair (e.g., round robin) arbitration methods, is described. VOQs of an input module and outgoing links of the input module are matched in a first phase. An outgoing link of an input module is matched with an outgoing link of a central module in a second phase. The arbiters become desynchronized under stable conditions which contributes to the switch's high throughput characteristic. Using this dispatch scheme, a scalable multiple-stage switch able to operate at high throughput, without needing to resort to speeding up the switching fabric and without needing to use buffers in the second stage, is possible. The cost of speed-up and the cell out-of-sequence problems that may occur when buffers are used in the second stage are therefore avoided. A hierarchical arbitration scheme used in the input modules reduces the time needed for scheduling and reduces connection lines.

Abstract: Multiple network processors (201, 202, 203) are connected in a pipeline via control (206) and data (205) ports of the network processors. The network processors (201, 202, 203) communicate with neighboring network processors through the control and data ports. Through these ports, the network processors can implement a variety of data flow control protocols.

Abstract: Application of the technique of statistical line grouping to banyan-type networks to practically alleviate the problems of output contention, traffic fluctuation, burstiness, and so forth without incurring additional preprocessing and buffering on the input traffic by introducing alternate-routing ingredient to the unique-routing banyan-type network, but without complicating the switching control too much through alternate routing. The multicast concentrator, a concentrator with the capability of multicasting, composed of interconnected bicast cells is employed to fill in each of the dilated nodes of the banyan-type network to give a hybrid network. An extremely simple self-routing control mechanism over the hybrid network which is the natural melting of the self-routing control inside the multicast concentrators and the self-routing control over the banyan-type network is presented.

Abstract: Physical implementation of the switching fabric of a massive broadband switching network constructed from recursive 2-stage interconnection. The recursive 2-stage construction is realized through a hierarchical levels of implementation, including inside-chip implementation, PCB implementation, orthogonal packaging, interface-board packaging and fiber-array packaging. Smaller switches resulted from lower levels can be employed as the switching elements in the construction of a larger switch at a higher level of implementation. Such a hierarchical levels of implementation provides great flexibility and scalability in the physical realization of switching fabric and hence yields indefinitely large-scaled switches.

Abstract: An embodiment of the present invention is disclosed to include a three stage scalable switching network that can be built from a common module. Further disclosed are methods for building switching network v(k, n, m) from a common module comprising a (n×k) input switch, a (k?×k?) middle switch, and a (k×n) output switch.

Abstract: The present invention is directed to a network switch that determines when specific content is hot and directs flow to one or more cache servers. The architecture can include a tag generator to generate unique tags corresponding to a server in a plurality of servers, a content pre-fetching algorithm to retrieve information before the information is requested by determining the hotness of the information, and a cache server in which stored information is configured based upon the relative degrees of hotness of the stored information.

Abstract: A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12×12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned.

Abstract: A packet processing device capable of restraining overhead and processing packets at high speed. Packet input section is input a packet, and internal information handover section hands over internal information of a packet processor. Packet computing section computes the input packet in accordance with the internal information, and packet output section outputs the computed packet. A communication line connects such packet processors in series.

Abstract: Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.

Abstract: A pipeline-based matching scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with matching schemes, such as CRRD and CMSD. In the new approach, arbitration may operate in a pipelined manner. Each sub-scheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides a matching result(s). The sub-scheduler can use a matching scheme such as CRRD and CMSD.

Abstract: Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.

Abstract: The present invention reduces the cost of a minimally configured network device by providing a network device with a distributed switch fabric. Such a network device locates a portion of the switch fabric functionality on each forwarding card allowing the minimal network device configuration to include less than the entire switch fabric functionality. The cost of the minimal configuration is, therefore, reduced allowing network service providers to more quickly recover the initial cost of the network device. As new services are requested, additional functionality, including both forwarding cards and universal port cards may be added to the network device to handle the new requests, and the fees for the new services may be applied to the cost of the additional functionality. Consequently, the cost of the network device more closely tracks the service fees received by network providers.

Abstract: Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.

Abstract: Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.

Abstract: A switch fabric includes a first plurality of data switches each having a plurality of input ports and a plurality of output ports the plurality of switches capable of switching any of its input ports to any of its output ports with the plurality of data switches having inputs coupled to a plurality of input buses so that a first byte of a first one of the input buses is coupled to a first one of the plurality of switches, and a succeeding byte of the first input bus is coupled to a succeeding one of the plurality of switches.

Abstract: A scheduling system for IP routers is provided. A programmable scheduler for IP routers can support single stage and multistage scheduling. This allows flexible combinations of scheduling and widens dramatically the available QoS solutions to operators. With this kind of scheduling the router can be configured to support almost any known scheduling method or combination. Priority Queuing (PQ) and Deficit Round Robin (DRR) scheduling is scheduling is used according to one embodiment of the invention.

Abstract: One aspect of the invention provides an apparatus for modelling a plurality of switching operations arranged in a plurality of switching stages. The apparatus comprises a respective switch stage component for each switching stage, and each switch stage component comprises a respective addressable switch state indicator for each switching operation associated with the respective switching stage. The values of the switch state indicators in a given switch stage component identify a respective switch state indicator in another switch stage component. The switch stage components are interconnected such that addressing a switch state indicator in one switch stage component causes the respective identified switch state indicator in another switch stage component to be addressed. In the preferred embodiment, each switch stage component comprises a respective Look-Up Table.

Abstract: A switch fabric for routing data has a switching stage configured between an input stage and an output stage. The input stage forwards the received data to the switching stage, which routes the data to the output stage, which transmits the data towards destinations. Each input device of the input stage transmits bids to the crossbar devices of the switching stage to request connections through the switching stage for routing the data to the output devices of the output stage. In one aspect, each crossbar device has (1) a bid arbitrator that determines whether to accept or reject each received bid, wherein, in response to a collision between multiple bids, the bid arbitrator accepts two or more of the colliding bids in a single time slot; and (2) memory for storing one or more accepted cells for the same output device, wherein the crossbar device can transmit grant signals for two or more accepted bids for the same output device in a single time slot.

Abstract: A switch is provided that includes three stages. The first stages has a plurality of switch circuits. The second stage has a plurality of switch circuits equal to N, where N is any integer other than a power of 2 and where the switch circuits can be logically configured into a logical configuration of a power of 2. The third stages includes a plurality of switch circuits.

Abstract: A cross-connect switch (12) uses a matrix (40) for providing connection paths. The matrix (40) includes prioritization logic (42) for receiving connection requests from restoration state machines (50) (for changing connections responsive to line conditions) and an administrative processor (for changing connections responsive to operator commands). Connection requests from both the restoration state machines (50) and the administrative processor (52) are cached in FIFO memories (54). When a FIFO memory (54) stores one or more connection requests, the switching control circuitry is notified by a data ready signal. Logic (56) inhibits passing of the data ready signal from the FIFO memory (54) to the switching control (26) until all restoration connection requests have been serviced.

Abstract: Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.

Abstract: A packet-switched network system comprises a multiplicity of multi-port network units each of which has first and second ports and other ports and transmission links coupling the first and second ports of said unit in a closed ring. The first and second ports and transmission links support duplex transmission of Ethernet data packets. Each unit transmits from said first and second ports packets including selected information enabling on reception of a packet at any of the units a determination of a number of hops from unit to unit around said ring said packet has made. Each unit has a forwarding database and in response to the said selected information controls the transmission of said packets in two directions around said ring, and each unit causes discard of packets which have according to said selected information circumnavigated the ring.

Abstract: An m-to-n concentrator constructed from smaller concentrator/sorters wherein m is not necessarily equal to 2n. For instance, the m-to-n concentrator can be implemented from an ?m/2?-to-n concentrator/sorter, an ?m12?-to-n concentrator/sorter, and n sorting cells to thereby produce the desired arrangement of outputs required of the m-to-n concentrator.

Abstract: Methods and apparatus are disclosed for distributing fault indications and maintaining and using a data structure indicating faults to route traffic in a packet switching system. In one embodiment, a packet switching system detects faults and propagates indications of these faults to the input interfaces of a packet switch, so the packet switch can adapt the selection of a route over which to send a particular packet. Faults are identified by various components of the packet switching system and relayed to one or more switching components to generate a broadcast packet destined for all input ports (i.e., to each I/O interface in a packet switch having folded input and output interfaces). Other embodiments, generate one or more multicast or unicast packets. The I/O interface maintains one or more data structures indicating the state of various portions of the packet switching system.

Abstract: In a packet switch structured by connecting unit switches in multi-stages which is capable of transmitting packets without delay and accommodating high-speed lines, unit switches at the first stage assign, to an input packet, a sequence number according to a destination of the packet and distribute and send out the packet to a unit switch at the succeeding stage and unit switches at the final stage sequence and output packets according to sequence numbers assigned to packets received from a unit switch at the preceding stage.

Abstract: Disclosed a method of increasing the whole switch capacity by utilizing the presently used switch network as it is. The present invention, the method of increasing a switch capacity in a switch network system in which three or more switch stages including a plurality of switching elements are connected in serial by using a predetermined logical circuit, the method comprising the steps of: adding switch stage including a plurality of switching elements to correspond to the each switch stage; grouping switching elements of a first switch stage and last switch stage in the switch stage and the added switch stage by a predetermined unit, respectively; and connecting the grouped switching elements of the first stage with corresponding switching elements of an intermediate switch stage which is placed between the first stage and last stage, respectively, and connecting the grouped switching elements of the last switch stage with the corresponding switching elements of the intermediate switch stage, respectively.

Abstract: A system is disclosed for routing data cells from at least one of a plurality of source port processors to at least one destination port processor. Such a system contemplates each cell comprising a plurality of cell frame portions. In a preferred embodiment of the system of the present invention, each cell generated by the at least one source port processor is separated into its constituent frame portions. Each frame portion has associated therewith a first characteristic and a second characteristic. The cell portions are transmitted to at least one port associated with at least one crossbar chip. The at least one port is in communication with at least two of the plurality of source port processors. Each cell portion is selectively transmitted according to its first characteristic to a corresponding one of the crossbar chips. Each cell portion is selectively transmitted according to its second characteristic to a corresponding one of the ports of the corresponding one of the crossbar chips.

Abstract: Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.

Abstract: Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.

Abstract: A pipeline-based matching scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with matching schemes, such as CRRD and CMSD. In the new approach, arbitration may operate in a pipelined manner. Each sub-scheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides a matching result(s). The sub-scheduler can use a matching scheme such as CRRD and CMSD.

Abstract: A shaping control method and apparatus performing a shaping for a large amount of connections with high accuracy, the apparatus including a theoretical transfer time calculator, a theoretical transfer time holding section, first and second time managing sections, a theoretical transfer time acquisition section, and a transfer determining section. The second time managing section holds information relating to connections in waiting transfer, by dividing into standardized time slots. A portion of connection information stored in the second time managing section is stored in the first time managing section. The information relating to connections in waiting is stored in the first time managing section or the second time managing section. Thereby, a shaping in stages for the same shaping subject and a shaping of a large amount of connections with high accuracy can be performed. Also, an optimum shaping for a plurality of shaping subjects different from each other can be realized.

Abstract: A marching algorithm for the selection of middle stage switch elements in a network uses an arbitrary but settled sequence in which middle stage switch elements are sampled. The sequence is applied in the forward direction to find an appropriate middle stage switch element during connection and in a reverse direction during disconnection to find an appropriate middle stage switch element for rearrangement. All of the input switch elements use the same marching sequence. The marching algorithm is applicable to both single rate and multi-rate connections. In the case of multi-rate connections, multiple rearrangements may occur at disconnect to match the capacity of the terminated connection.

Abstract: Methods and apparatus for forwarding packets in a multistage interconnection network are provided which timestamp packets using a substantially system-wide timing reference and a merge sorting variant to restore packets to the proper order, using the timestamp information carried in the packets. One implementation determines when packets passing along different paths in the network can be safely forwarded, even when no packets have recently been received on some of the paths, by forwarding status messages along otherwise idle paths. The status messages provide information that can be used by downstream components to allow them to determine when packets passing over other paths can safely be forwarded. One implementation simultaneously resequences packets being delivered to all n outputs of the multistage interconnection network. The resequencing operations are distributed among a plurality of switching elements making up the interconnection network.

Abstract: A redundant multi-stage network can be upgraded in a non-stop manner via a bypass and a rewiring phase. The bypass phase involves selecting two adjacent rows as close to the middle of the network as possible thus maximizing the path redundancy and maximizing the number of paths around an upgrade induced fault; creating a bypass and original section by stretching the connections between these two rows, breaking a connection in the bypass section; inserting new nodes into the bypass section by connecting the top and bottom ports of each node in an alternating manner to minimize the node's input and output traffic imbalance; and repeating for all the connections in the bypass section.

Abstract: A method and apparatus for reallocating switching circuitry in a switching fabric are disclosed. The switching fabric is used to permit data transfer among a plurality of interface units each having a plurality of data ports. The switching fabric is partitionable into a plurality of switch planes such that each switch plane can be assigned to transfer data associated with like data ports of the interface units. Each switch plane includes multiple switching channels each assignable to transfer data associated with one data port of one of the interface units, in a full implementation. The number of interface units is less than the number of switching channels in a switch plane, then the reallocation is performed such that multiple channels of at least one switch plane can be assigned to transfer data of multiple ports of at least one of the interface units. This results in switch plane channels that would otherwise be unused being utilized to transfer data.

Abstract: A method and apparatus for sharing storage in a cross-connect. According to one embodiment of the invention, a cross-connect includes a number of sets of data input lines and a number of matrices. Each of the sets of data input lines is to be coupled to a different line card. Each of the matrices is coupled to every one of the sets of data input lines. In addition, each of the matrices has a set of data output lines, where the set of data input lines of each of the matrices is to be coupled to a different one of the line cards.

Abstract: For achieving elimination of unfairness between ports, reserved output port information transferred between respective modules is input to switch out of the module to vary destination of output. The module and the switch operate in synchronism with the frame for which the connection grant process of a plurality of time slot is performed to vary connection topology so that all connection topology appear. By variation of connection topology, variation combination of adjacent port appear to shuffle preference for the input port which is otherwise held fixed for resolving unfairness relating to reservation chance of the input port.

Abstract: A method is described that involves presenting packet header information from a packet and packet size information for the packet to a pipeline that comprises multiple stages. One of the stages identifies, with the packet header information, where input flow information for the packet is located. The input flow information is then fetched. The input flow information identifies where input capacity information for the packet is located and the input capacity information is then fetched. Another of the stages compares an input capacity for the packet with the packet's size and indicates whether the packet is conforming or non-conforming based upon the comparison. The input capacity is calculated from the input capacity information.

Abstract: A method of adding a new connection (c, d) to a time:space:time switch fabric. The fabric has a set I of k input elements, a set M of m switch elements, and a set O of l output elements. Each input element contributes one input to each switch element, and each output element receives one output from each switch element. A state Sm characterizes the switch elements as a set of ordered pairs (i, j), where (i, j) ? Sm if and only if the jth output element is coupled to the ith input element through one of the switch elements. The range of Sm is the set of outputs of Sm such that if j ? range(Sm) then (i, j) ? Sm for some i ? I. The domain of Sm is the set of inputs of Sm such that if i ? domain(Sm) then (i, j) ? Sm for some j ? O.

Abstract: A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized data frame. Both the configuration data and a frame clock may be propagated through the plural stages from a master switch. First and last stages of the digital cross connect may be implemented on common chips having two framing time bases. Data may be aligned to a global frame clock and interchanged using a single random access memory in a time slot interchanger. The write address to the random access memory is generated from a local frame counter keyed to the input data frame while a read address is transformed from a global frame counter.

Abstract: A matrix of routing cells forming a cross-bar decoder (70). Signal triplets (84, 86, 88) coupled to the cross-bar decoder (70) are assigned a priority. A register (50) provide outputs to the cross-bar decoder (70) to either activate or deactivate routing of the triplet signals (84, 86,88) through the cross-bar decoder (70). The routing cells (72-82) are arranged in a matrix of columns and rows, where the triplet signals are applied to the row routing cells (72, 74, 76) and are extracted at the column routing cells (76, 80, 82). When a routing cell in a row is enabled to couple signals to an output, it disables all other lower priority routing cells in its column so that they cannot route signals to that output. Based on the automatic disabling of routing cells by others, the signals ripple through the cross-bar decoder (70) until all high priority I/O pins are used.

Abstract: A retransmission control method is provided. In the method, all base stations perform error judgment for a signal sent from a mobile station 1. Then, first and second base stations send results of error judgment to a third base station which is a communication partner of the mobile station 1. The third base station sends NACK for requesting retransmission to the mobile station 1 only when every result of error judgment of the first and second base stations indicates that there is an error.

Abstract: Methods and apparatuses for laying out an integrated circuit include a first plurality of I/O ports that are positioned along the first side, a plurality of queues that are coupled to the first plurality of I/O ports, a first bus that is positioned extending from the plurality of queues toward the second side to couple a control circuit to the plurality of queues, second plurality of I/O ports that are positioned along the third side and the fourth side, and a second bus that is positioned between the control circuit and the second plurality of I/O ports to couple the control circuit to the second plurality of I/O ports, wherein the first bus and the second bus are positioned such that the respective bus lines do not cross over each other. A time and space switching apparatus and component cell permit a bit within a data line to be selected.

Abstract: A compact multi-stage switching network (100), and a router (510) incorporating such multi-stage switching network, adapted for simultaneously routing a plurality of data packets from a first plurality of input ports (110) to selected ones of a second plurality of output ports (190) comprising: a first stack (140) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer containing at least one switching element circuit (142); a second stack (160) of IC switching layers (113) that are stacked in physical contact with one another, each IC switching layer (113) containing at least one switching element circuit (162); and interconnecting circuitry (150) that connects the first stack (140) of IC layers to the second stack (160) of IC layers to form the compact multi-stage switching network. The stacks (140, 160) are preferably mated to one another in a transverse fashion in order to achieve a natural full-mesh connection.

Abstract: A high bandwidth connection is mapped through a multi-stage switch between an ingress node and an egress node via a center stage comprising M (an integer) center stage nodes. Each center stage node is connected to the ingress and egress nodes by respective links adapted to support m (an integer) respective connections. An m×M connection matrix of connections between the ingress node and the center stage is provided. Each column of the connection matrix contains 1≦j≦m connections between the ingress node and a respective one of the center stage nodes, and each row of the connection matrix contains 1≦k≦M connections between the ingress node and the center stage nodes. The high bandwidth connection is mapped through the multi-stage switch by layering the high bandwidth connection within the connection matrix. Thus the high bandwidth connection is divided into N segments.

Abstract: In a connection comprising N channels for transmitting a high data rate, a first channel is provided in a control unit which takes over coordination of the further N−1 channels. The individual channels of the connection comprising N channels furthermore appear in the exchange according to the use of their resources; however, only the first channel is responsible for controlling the connection, so that only one single N-fold connection is set up through the switching system.