Detail Of Clock Recovery Or Synchronization Patents (Class 370/395.62)
  • Patent number: 10390116
    Abstract: An optical modem includes client interface circuitry; line interface circuitry configured to interface a client signal with the client interface circuitry and interface a line signal in a transmit direction and a receive direction, wherein the line signal terminates at a second optical modem; and a clock connected to the line interface circuitry, wherein the clock includes a selector configured to select one of a local reference clock and a recovered clock from the receive direction based on whether the optical modem is a master or slave and based on whether there is a fault in the receive direction, wherein the optical modem and the second optical modem form a timing island separate from a timing domain associated with the client signal and a second client signal associated with the second optical modem.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 20, 2019
    Assignee: Ciena Corporation
    Inventor: Vincent Fifer
  • Patent number: 10346329
    Abstract: A method is provided for optimized timer placement. A request to apply a new timer in a computer system is received and an interrupt time for the new timer is extracted from the new timer. A timer list is accessed for each processor in the system responsive to the received request. A range for placement of the new timer is established with respect to each of the accessed timer lists. A timer expiry delay is calculated between proximal processor interrupts and the extracted interrupt time based on the established range placement. Proximity of the extracted interrupt time within the existing processor interrupts is determined and one of the processors is selected based on the calculation and the determined proximity. The new timer is placed on the selected processor.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Juan M. Casas, Jr., Nikhil Hegde, Keerthi B. Kumar, Shailaja Mallya
  • Patent number: 10346327
    Abstract: A system and computer program product are provided for optimized timer placement. A request to apply a new timer in a computer system is received and an interrupt time for the new timer is extracted from the new timer. A timer list is accessed for each processor in the system responsive to the received request. A range for placement of the new timer is established with respect to each of the accessed timer lists. A timer expiry delay is calculated between proximal processor interrupts and the extracted interrupt time based on the established range placement. Proximity of the extracted interrupt time within the existing processor interrupts is determined and one of the processors is selected based on the calculation and the determined proximity. The new timer is placed on the selected processor.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Juan M. Casas, Jr., Nikhil Hegde, Keerthi B. Kumar, Shailaja Mallya
  • Patent number: 10320664
    Abstract: Systems, methods, and computer-readable media are provided for facilitating the implementation of an operations, administration, and management (OAM) protocol in a network overlay environment. In particular, aspects of the technology facilitating the transport of OAM communications across overlay environments of different types. Aspects of the technology can include steps for receiving a packet comprising an OAM payload, and encapsulating the packet with an OAM transport header, wherein the transport header is configured to be read by transit nodes of different overlay types.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: June 11, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Nagendra Kumar Nainar, Carlos M. Pignataro, Deepak Kumar
  • Patent number: 10298484
    Abstract: In one embodiment, a copy of an original packet of a traffic flow is created at an ingress leaf node of a cloud switch. The ingress leaf node forwards the original packet along a less-specific path through the cloud switch, the less-specific path based on a domain index of an egress domain for the original packet. The copy of the original packet is modified to create a more specific path learn request packet. The ingress leaf node forwards the more specific path learn request packet along the less-specific path through the cloud switch. The ingress leaf node received back a more specific path learn request reply packet that includes an indication of a fabric system port. The ingress leaf node then programs a forwarding table based on the indication of the fabric system port, to have subsequent packets of the traffic flow forwarded along a more-specific path.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: May 21, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Pags Krishnamoorthy, Rajagopalan Janakiraman, Chia Alex Tsai, Vinay Parameswarannair
  • Patent number: 10291446
    Abstract: A clock synchronization method, a receiver, a transmitter, and a clock synchronization system, where the method includes obtaining a common reference clock signal, determining Bt according to the common reference clock signal and Mrd(t?1), where B t = mod ? [ ? n = 0 t - 1 ? ? Mr d ? ( n ) , 2 p ] , determining that Mrd(t?1) is a target Mrd when Ct obtained by means of calculation according to Mrd(t?1) is less than or equal to a threshold, where Ct=Bt?At, At is included in a residual time stamp (RTS) packet received by a receiver last time from the transmitter, and A t = mod ? [ ? n = 0 t ? ? M d ? ( n ) , 2 p ] , performing frequency division on the common reference clock signal using the target Mrd as a frequency dividing coefficient to obtain a first clock signal, and performing frequency multiplication processing on the first clock signal to obtain a service clock signal. Hence, random phase offset may be avoided.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: May 14, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Chuan Xu, Cong Chen
  • Patent number: 9888053
    Abstract: Systems and methods for downloading data by conditionally using idle network capacity are described. In some embodiments, the systems and methods downloads into a buffer a first portion of media content in accordance with a first content streaming mode that permits downloading of media content data even when there is no idle network capacity, and upon determining that the buffer has been filled to a threshold level, downloads into the buffer a second portion of the media content in accordance with a second content streaming mode that permits downloading of media content data, e.g., only when there is idle network capacity.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: February 6, 2018
    Assignee: OPANGA NETWORKS, INC.
    Inventors: John Burnette, Ben Hadorn, Jeffrey Harrang, Giles Westerfield, David Gibbons
  • Patent number: 9800897
    Abstract: A method and a device for forming a common transport datastream from several mobile-digital television signal datastreams and a common stationary-digital television signal datastream. A constant number of data units of respectively-constant size in every successive time interval with constant cycle duration for the transmission of every individual datastream is determined. A data structure is specified for the common datastream with successive sequences in each case of a constant number of data units with respectively-identical positions for data units of the stationary-digital television signal and respectively-identical positions for data units of the mobile-digital television signal. Data units of each of the datastreams of the mobile-digital television signal are transmitted in each case in associated, identical positions of at least one successive sequence, and define the individual positions of the data structure of the common datastream with data units of the respectively associated datastreams.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: October 24, 2017
    Assignee: Rohde & Schwarz GMBH & CO. KG
    Inventors: Denis Hagemeier, Torsten Goerig
  • Patent number: 9544638
    Abstract: In conventional packet communications systems, such as MPEG-2, the data stream includes a program clock reference (PCR) so that the receiver decoder can lock on to the data stream. The invention eliminates the need to send the PCR by transferring a data transport rate explicitly in the header of the data packets so that the decoder can use the transport rate as a locking reference and adjust its phase lock loop. The transport rate is carried in the adaptation field as user private data.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: January 10, 2017
    Assignee: Broadcom Corporation
    Inventors: Jiang Fu, Zhijie Yang, Brian A. Heng, Xuemin Chen
  • Patent number: 9292036
    Abstract: A data processing apparatus and method provide communication between a master device operating from a master clock signal and a slave device operating from a slave clock signal asynchronous to the master clock signal. An interface transfers packets between the master device and the slave device. A slave clock replica generator associated with the master device generates a slave clock replica that controls timing of transmission of packets by the master device over the interface. A sync request transfer is issued over the interface and has a property identifiable by the slave device irrespective of whether the sync request transfer is synchronized with the slave clock signal. In response, the slave device issues a sync response transfer indicative of at least a frequency of the slave clock signal, and the slave clock replica generator determines at least the frequency of the slave clock replica from that sync transfer.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: March 22, 2016
    Assignee: ARM Limited
    Inventors: Thomas Christopher Grocutt, Thomas Sean Houlihane
  • Patent number: 9280507
    Abstract: A reset of a synchronization counter is synchronized to an external deterministic signal. Entry into the link transmitting state is further synchronized with the deterministic signal. A target latency is identified for a serial data link. A data sequence is received synchronized with a synchronization counter associated with the data link. Target latency can be maintained using the data sequence.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: March 8, 2016
    Assignee: INTEL CORPORATION
    Inventors: Venkatraman Iyer, Darren S. Jue, Jeff Willey, Robert G. Blankenship
  • Patent number: 9270607
    Abstract: This invention relates to packet selection techniques that can be used in conjunction with a clock recovery mechanism to mitigate the effects of packet delay variation on timing messages exchanged over a packet network, particularly when seeking to synchronize the time of a clock in a slave device to that of a master clock. The packet selection techniques can assist in reducing the noise in the recovered clock signal at the slave device, allowing recovery to a higher quality. Embodiments of the invention provide techniques based on extracting timing packets that create a constant interval between the arrival of selected packets at the slave device and on extracting timing packets which are closest to making the interval between arrival of the selected packets equal to the interval between the departure of the packets.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: February 23, 2016
    Assignees: Khalifa University of Science, Technology and Research, British Telecommunications PLC, Emirates Telecommunications Corporation
    Inventors: Zdenek Chaloupka, James Aweya
  • Patent number: 9042274
    Abstract: An electronic communication system including at least one first communication unit and one second communication unit which are connected to one another by means of at least one first data line. The communication system has a data transmission protocol according to which, in at least one first data transmission mode for synchronized data transmission, the first communication unit transmits a data request signal or a clock signal to the second communication unit via the first data line at least once and the second communication unit transmits a data signal to the first communication unit via the first data line in response to the data request signal or the clock signal.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: May 26, 2015
    Assignee: Continental Teves AG & Co. oHG
    Inventors: Thomas Peichl, Thorsten Ehrenberg, Jörn Schriefer
  • Patent number: 9036754
    Abstract: A circuit and method of operation for a circuit of a radio system in which a system time is divided into symbols, in which a system clock generator is activated in an operating mode, so that the system time is determined from an output clock signal of the system clock generator by counting, in which the system clock generator is deactivated in a sleep mode, in which an output clock signal of a sleep clock generator is blanked as a function of an output signal of a modulo divider in the sleep mode, and the system time is determined by counting, wherein an output frequency of the output clock signal of the sleep clock generator is a non-integer multiple of a symbol frequency, in which the modulo divider divides the output clock signal of the sleep clock generator by a division factor, and in which the division factor of the modulo divider is produced by changing between at least two integer divisor values.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: May 19, 2015
    Assignee: Atmel Corporation
    Inventors: Dirk Haentzschel, Lutz Dathe
  • Patent number: 9021291
    Abstract: A network node of a synchronous network, wherein said network node comprises a timing circuit which recovers a reference clock from a reception signal received by said network node from an upstream network node of said synchronous network and uses the recovered reference clock for a transmission signal transmitted by said network node to a downstream network node of said synchronous network; and a clock stability monitoring circuit which monitors internal control parameters (CP) of said timing circuit to detect an instability of the reference clock distributed within said synchronous network.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: April 28, 2015
    Assignee: ADVA Optical Networking SE
    Inventor: Anthony Magee
  • Patent number: 9020086
    Abstract: A clock data recovery circuit module including a clock recovery circuit, a frequency comparison circuit and a signal detecting circuit is provided. The clock recovery circuit is configured to output a data recovery stream and a data recovery clock based on an input signal and a clock signal. The frequency comparison circuit is coupled to the clock recovery circuit. The frequency comparison circuit is configured to compare a frequency difference between the data recovery clock and the clock signal to adjust the frequency of the clock signal based on a comparison result. The signal detecting circuit is coupled to the frequency comparison circuit. The signal detecting circuit is configured to receive and detect the input signal, and the signal detecting circuit determines whether to enable the frequency comparison circuit according to the detection result. Furthermore, a method for generating a data recovery clock is also provided.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: April 28, 2015
    Assignee: Phison Electronics Corp.
    Inventors: Chih-Ming Chen, An-Chung Chen
  • Patent number: 9007989
    Abstract: A method, apparatus, and system for time synchronization are disclosed. The method comprising: obtaining a master sending time stamp, a slave receiving time stamp, a slave sending time stamp, and a master receiving time stamp; and adjusting the time of the slave clock according to the offset calculated from the time stamps to synchronize with the clock time of the master clock. With the present invention, in passband transmission systems that transmit signals continuously in units of symbols, the time synchronization is implemented between the master clock and the slave clock.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: April 14, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Guijin Xu, Guozhu Long, Ruzhou Feng
  • Patent number: 8964762
    Abstract: In one embodiment, a battery-operated communication device “quick-samples” a frequency hopping sequence at a periodic rate corresponding to a substantially low duty cycle, and is discovered by (e.g., attached to) a main-powered communication device. During a scheduled sample, the main-powered communication device transmits a control packet to be received by the battery-operated communication device, the control packet containing timing information and transmitted to account for worst-case clock drift error between the two devices. The battery-operated communication device responds to the control packet with a link-layer acknowledgment containing timing information from the battery-operated communication device. Accordingly, the two devices may re-synchronize their timing based on the timing information in the control packet and acknowledgment, respectively.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: February 24, 2015
    Assignee: Cisco Technology, Inc.
    Inventors: Jonathan W. Hui, Lik Chuen Alec Woo, Wei Hong
  • Patent number: 8937975
    Abstract: A circuit including delay stages, gain stages, and a summer. The delay stages are configured to provide delayed versions of a first signal. The gain stages are configured to receive the delayed versions of the first signal. Each of the gain stages provides an amount of gain for a corresponding one of the delayed versions of the first signal. The delay stages and the gain stages are configured to provide pre-emphasis to the first signal. The summer is configured to output a second signal based on the delayed versions of the first signal. The second signal includes the pre-emphasis.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: January 20, 2015
    Assignee: Marvell International Ltd.
    Inventors: Lei Wu, Timothy Hu
  • Patent number: 8934491
    Abstract: A digital broadcasting system and a method of processing data are disclosed. Herein, additional encoding is performed on mobile service data, which are then transmitted, thereby providing robustness in the processed mobile service data, so that the mobile service data can respond more strongly against fast and frequent channel changes. In a transmitting system including a service multiplexer and a transmitter located in a remote site, a method of processing data of the transmitting system includes comparing an output data rate of the service multiplexer and a transmission data rate of the transmitter, when a difference occurs between the two data rates, adjusting a burst size, wherein the burst transmits mobile service data, and encoding the mobile service data, and referring to the burst size so as to multiplex main service data and the encoded mobile service data in a burst structure.
    Type: Grant
    Filed: February 6, 2008
    Date of Patent: January 13, 2015
    Assignee: LG Electronics Inc.
    Inventors: Hyoung Gon Lee, In Hwan Choi, Kook Yeon Kwak, Jong Moon Kim, Won Gyu Song, Byoung Gill Kim, Jin Woo Kim
  • Patent number: 8929405
    Abstract: There is provided a method of optimizing timing packet transport in a network node, the method comprising using a locally available stable frequency reference at the network node to provide a pre-determined network node transit time for timing packets in at least one direction into or out of the network node. There is also provided a network node comprising a locally available stable frequency reference and circuitry adapted to apply a pre-determined network node transit time, L, to all timing packets transiting the network node in at least one direction into or out of a network node dependent on the locally available stable frequency reference.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: January 6, 2015
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventors: Stefano Ruffini, Raoul Fiorone, Orazio Toscano
  • Patent number: 8923341
    Abstract: A method switches master/slave timing in a communication network without traffic disruption. The method includes a master device informing a slave of timing loss. The master device additionally begins transmitting with timing from a local reference clock and begins receive timing recovery. The slave freezes its receive timing recovery and locks its transmit clock. The master device transitions its transmit timing to use the recovered receive clock. The slave gradually switches to transmitting using its local clock signal. The method may be used in synchronous Ethernet networks.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: December 30, 2014
    Assignee: Vitesse Semiconductor Corporation
    Inventors: James D. Barnette, Mandeep S. Chadha, James A. McIntosh
  • Patent number: 8897408
    Abstract: A method for operating an automation system with a plurality of communication users linked for communication purposes via a serial connection, of which at least one functions as sender and at least one as a receiver, includes determining at a sender an offset value between an occurrence of a synchronous signal and a communication clock cycle, transmitting the determined offset value in a data transmission to the at least one receiver, waiting at the at least one receiver until a time period commensurate with the offset value has elapsed, and generating at the at least one receiver an output signal after the time period has elapsed.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: November 25, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventor: Peter Jänicke
  • Patent number: 8879448
    Abstract: An apparatus and method of controlling power of a wireless multimedia media access control (WiMedia MAC) device are provided. The method includes: determining whether a fragment of an MAC service data unit (MSDU) is lost when a fragment is received; extracting a duration field from the received fragment if it is determined that the fragment of the MSDU is lost; and converting a power mode into a low power mode during a period of time established in the duration field.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Swaminathan Sundaresan
  • Patent number: 8873689
    Abstract: A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Yuwen Swei
  • Patent number: 8842994
    Abstract: A method and system of distributing clock synchronization information within an optical communications network including a plurality of network elements, in which a first network element receives an ingress clock synchronization message, the ingress clock synchronization message including a clock synchronization message identifier and a correction field. The first network element inserts the clock synchronization message identifier into an optical channel frame overhead and inserts the ingress clock synchronization message into an optical channel frame payload. The first network element transmits the optical channel frame overhead and the optical channel frame payload to a second network element, and determines a transit time of the clock synchronization message identifier across each of the network elements. The second network element updates the correction field of the ingress clock synchronization message with said transit times to form an egress clock synchronization message.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: September 23, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Sergio Lanzone, Orazio Toscano, Stefano Ruffini
  • Patent number: 8839020
    Abstract: A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: September 16, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Jingcheng Zhuang, Nam V. Dang, Xiaohua Kong, Zhi Zhu, Tirdad Sowlati, Behnam Amelifard
  • Patent number: 8831007
    Abstract: A communication system including a parent station and a plurality of child stations, the parent station and the plurality of child stations being line-connected or loop-connected in a plurality of stages, and the parent station comprises a decision unit configured to decide, based on information representing states of the plurality of child stations, which one a first data relay method of transmitting data to a subsequent station in accordance with a clock reproduced from data received from a preceding station and a second data relay method of transmitting data to the subsequent station in accordance with a local clock generated in a local station should be employed by each of the plurality of child stations.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: September 9, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hitoshi Asai, Tomoyuki Takada, Wataru Tachiwa, Naoto Takahashi, Makoto Umehara
  • Patent number: 8811410
    Abstract: A network device having a system performance measurement unit employing one or more global time stamps for measuring the device performance is disclosed. The device includes an ingress circuit, a global time counter, an egress circuit, and a processor. The ingress circuit is configured to receive a packet from an input port while the global time counter generates an arrival time stamp in accordance with the arrival time of the packet. The egress circuit is capable of forwarding the packet to other network devices via an output port. The processor, in one embodiment, is configured to calculate packet latency in response to the arrival time stamp.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: August 19, 2014
    Assignee: Tellabs, Inc.
    Inventors: Naveen K. Jain, Venkata Rangavajjhala
  • Patent number: 8811555
    Abstract: An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops).
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: August 19, 2014
    Assignee: Altera Corporation
    Inventors: Kazi Asaduzzaman, Tim Tri Hoang, Tin H. Lai, Shou-Po Shih, Sergey Shumarayev
  • Patent number: 8798076
    Abstract: A method of transporting data with embedded clock including following steps is provided. In an initial stage, a first bit length and a second bit length are determined. Original data is received. The original data is packed with every N bits as a packet, where N is at least 4. It is analyzed whether a long-run length of long-run data with consecutive same bit data in the packet is greater than N/2. The packet is coded to embed clock/toggle information with the first bit length into the packet. The clock/toggle information determines whether the long-run data is toggled. An appearance frequency of the clock/toggle information is clock information. If the long-run length is not greater than N/2, the long-run data is not toggled. If the long-run length is greater than N/2, bit with the second bit length after an Lth bit of the long-run data is toggled.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: August 5, 2014
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chia-Wei Su, Chu-Ya Hsiao
  • Patent number: 8774197
    Abstract: In a packet-based (e.g., Ethernet) network, such as the network of central offices and base stations of a wireless telephone system, a node receives one or more incoming packet-based signals from one or more other nodes of the network and recovers a clock signal from each incoming packet-based signal. The node selects one of the recovered clock signals as the node's reference clock signal. When the node is part of a base station, the node uses the selected clock to generate and transmit one or more outgoing packet-based signals to one or more central offices. The node also uses the selected clock to generate the base station's wireless transmissions. In one implementation, the base stations and central offices are connected by Ethernet facilities.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: July 8, 2014
    Assignee: Agere Systems LLC
    Inventor: P. Stephan Bedrosian
  • Patent number: 8774196
    Abstract: The present disclosure relates to an active antenna array for a mobile communications network. The active antenna comprises a base band unit coupled to a base station, a plurality of transceiver units and at least one link. The plurality of transceiver units is terminated by at least one antenna element. The at least one link couples individual ones of the plurality of transceiver units to the base band unit 10. The at least one link is a digital link and is adapted to relay an individual transmit signal concurrently and in synchronisation with a transmit clock signal. The present disclosure further teaches a method for relaying radio signals in a mobile communications network. The present disclosure further relates to a computer program enabling a computer to manufacture the active antenna array of the present disclosure and to execute the method of relaying radio signal in a mobile communications system.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: July 8, 2014
    Assignee: Kathrein-Werke KG
    Inventors: Georg Schmidt, Johannes Schlee
  • Patent number: 8774227
    Abstract: In a method of recovering timing information over packet networks, a receiver receives a plurality of packet streams over different paths from the same source. The raw delays experienced by the timing packets for each stream are filtered to provide a filtered delay for each stream. The filtered delays are weighted based on the quality of each stream, and the weighted filtered delays are then combined to form an aggregate delay estimate. Frequency adjustments for a local clock at the receiver are derived from the aggregate delay estimate.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: July 8, 2014
    Assignee: Microsemi Semiconductor ULC
    Inventor: Kamran Rahbar
  • Patent number: 8762796
    Abstract: In an embodiment, provided is a communication device connected to time servers via a network with transfer devices. In the communication device: a network controller receives a message containing time information counted by the time server and containing a network identifier, and obtains a receiving timing of the message; a network processing unit, when the network identifier in the message does not match with any network identifier, destroys the message; a protocol processing unit, when the network identifier has a match, calculates a time error by the time information in the message and the receiving timing, detects whether a first time server is malfunctioning, and when detected the first time server malfunctioning, outputs the time error calculated by a network identifier assigned to a second time server; a servo calculates an operation amount by the time error; and a clock varies a clock rate according to the operation amount.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuyuki Kozakai, Mitsuru Kanda
  • Patent number: 8737292
    Abstract: The present invention provides a method of estimating a frequency offset. The method comprises receiving a wireless signal timed according to a first frequency; generating a local signal timed according to a second frequency; and performing a plurality of synchronization searches, each search comprising obtaining a set of correlation results indicative of a correlation between the wireless signal and the local signal at different timing offsets of the wireless signal relative to the local signal. The method the no comprises finding a series of results, with a result from each of a plurality of the synchronization searches, for which the difference in; timing offset between results from adjacent searches in the series is within a maximum specified value. A frequency off set between the first and second frequencies can be determined from the series.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: May 27, 2014
    Assignee: ICERA, Inc.
    Inventor: Simon Nicholas Walker
  • Patent number: 8730868
    Abstract: In order to select a synchronization signal higher in accuracy, thereby increasing the accuracy of the time synchronization, it is provided a network node for transferring data in a network, comprising: a network interface having a plurality of ports; a transfer control module; a time synchronizing module; a fluctuation measurement module; and a clock. The time synchronization module uses a received time synchronization packet to synchronize the clock. The fluctuation measurement module determines an accuracy of a time contained in the received time synchronization packet based on a result of comparison between the time contained in the received time synchronization packet and a time of the clock.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: May 20, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Masaki Yamada, Yuji Ogata, Nobuyuki Muranaka
  • Patent number: 8693596
    Abstract: Apparatus and methods calibrate and control detector gain in a Mueller-Muller timing detector. A main signal path includes a Mueller-Muller based timing error detector (MM TED). The main signal path generates a main error signal for clock recovery. A secondary signal path that includes a secondary MM TED. Each signal path samples soft symbols from a received signal. The sampling of the secondary MM TED is deliberately offset in time. A scale factor applied to the main error signal and to a secondary error signal is adaptively adjusted based on a comparison between the main error signal and the secondary error signal.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: April 8, 2014
    Assignee: PMC-Sierra, Inc.
    Inventors: William D. Warner, Anthony Eugene Zortea
  • Patent number: 8687520
    Abstract: The invention relates to a time triggered network used in particular in an automotive network having a plurality of clusters. Each cluster (A-X) includes a plurality of nodes (11).
    Type: Grant
    Filed: August 28, 2007
    Date of Patent: April 1, 2014
    Assignee: NXP B.V.
    Inventors: Andries Van Wageningen, Joern Ungermann, Markus Baumeister, Peter Fuhrmann
  • Patent number: 8675665
    Abstract: The clock synchronization accuracy between a master node and a slave node is stably measured. The slave node synchronizes its own clock with the clock of the master node by means of the packets transmitted from the master node. It reproduces the clock of the slave node by means of the transmitted packets, accumulates information on the transmitted packets and the clock of the slave node and performs clock synchronization on the basis of the accumulated information.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: March 18, 2014
    Assignee: NEC Corporation
    Inventors: Masaki Umayabashi, Hideo Yoshimi, Zhenlong Cui, Kazuo Takagi, Atsushi Iwata
  • Patent number: 8675666
    Abstract: A method for synchronizing network elements to a global clock derived from the GPS clock acquired by a plurality of base stations. The global clock is distributed to controllers of various networks, and from there to network access devices. The network access devices further distribute the global clock to various wire-line and local wireless networks and from there, to the users served by these networks. The user equipment is enabled with a simple clock discipliner that adjusts the local clock to the global clock, resulting in a reliable synchronization across the converged communication networks.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: March 18, 2014
    Assignee: Wi-Lan, Inc
    Inventors: Shiquan Wu, Jung Yee
  • Patent number: 8660596
    Abstract: An electronic apparatus includes a processing unit. The processing unit, when detecting a frequency offset between an radio frequency (RF) module and a corresponding base station (BS), controls an oscillator to change a frequency of a first reference clock signal outputted therefrom by a first frequency variation, and controls a compensation unit to change a frequency of a second reference clock signal outputted therefrom by a second frequency variation. Wherein the compensation unit receives and adjusts the first reference clock signal from the oscillator to output the second reference clock signal, and the frequency offset substantially equals the first frequency variation plus the second frequency variation.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: February 25, 2014
    Assignee: MediaTek Inc.
    Inventors: Ming-Jie Yang, Chu-Wei Lo
  • Publication number: 20140044133
    Abstract: Systems and methods for implementing bi-directional synchronization propagation between first and second communication devices are provided. The devices are arranged in a loop-timing configuration. A method includes detecting, by the second communication device, a switching signal comprising an indication to switch a timing role of the second communication device and engaging, by the second communication device, in a synchronization handshake with the first communication device over a communication link based on the detection of the switching signal. Engaging in the synchronization handshake includes determining whether the first communication device is configured to support bi-directional synchronization propagation. The method includes switching the timing role of the second communication device based on the synchronization handshake.
    Type: Application
    Filed: December 17, 2012
    Publication date: February 13, 2014
    Applicant: Broadcom Corporation
    Inventors: Peiqing Wang, Linghsiao Wang, Mehmet Vakif Tazebay
  • Patent number: 8649366
    Abstract: A method of performing uplink synchronization in a wireless communication system includes transmitting a random access preamble which is randomly selected from a set of random access preambles, receiving a random access response, the random access response comprising a random access preamble identifier corresponding to the random access preamble and a time alignment value for uplink synchronization, starting a time alignment timer after applying the time alignment value, starting a contention resolution timer after receiving the random access response, wherein contention resolution is not successful when the contention resolution timer is expired, and stopping the time alignment timer when the contention resolution timer is expired.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: February 11, 2014
    Assignee: LG Electronics Inc.
    Inventors: Sung Jun Park, Young Dae Lee, Seung June Yi, Sung Duck Chun
  • Patent number: 8644439
    Abstract: In certain embodiments, a circuit for transferring signals from a source clock domain to a destination clock domain comprises a first pulse generation circuit, a hold flip-flop circuit, a clocked synchronizer circuit and a second pulse generation circuit. The first pulse generation circuit, operable in the source clock domain, generates a source data pulse from a source data signal. The hold flip-flop circuit, operable in the source clock domain, is configured to hold the source data pulse. The clocked synchronizer circuit, operable in the destination clock domain, samples the source data pulse received from the hold flip-flop circuit, where source data pulse held at the output of the hold flip-flop circuit is cleared when the source data pulse is sampled by the clocked synchronizer circuit. The second pulse generation circuit, operable in the destination clock domain, is configured to generate a destination data pulse from the sampled source data pulse.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: February 4, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Chirag Sureshchandra Gupta
  • Patent number: 8619755
    Abstract: Embodiments of a dual-master mode Ethernet node are provided herein. The dual-master mode Ethernet node includes a first multiplexer configured to select between a local oscillator signal and a primary reference source (PRS) signal to provide a reference clock signal, a digital phase-locked loop (DPLL) configured to generate a master clock signal based on the reference clock signal, a phase rotator configured to rotate a phase of the master clock signal based on a frequency error between the master clock signal and an extracted clock signal to generate a slave clock signal, and a second multiplexer configured to select between the master clock signal and the slave clock signal to provide a transmit clock signal. The dual-master mode Ethernet node can dynamically generate the transmit clock based on either the extracted clock or the PRS without re-performing the auto-negotiation process.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: December 31, 2013
    Assignee: Broadcom Corporation
    Inventors: Peiqing Wang, Linghsiao Wang
  • Patent number: 8619789
    Abstract: In one embodiment, a battery-operated communication device “quick-samples” a frequency hopping sequence at a periodic rate corresponding to a substantially low duty cycle, and is discovered by (e.g., attached to) a main-powered communication device. During a scheduled sample, the main-powered communication device transmits a control packet to be received by the battery-operated communication device, the control packet containing timing information and transmitted to account for worst-case clock drift error between the two devices. The battery-operated communication device responds to the control packet with a link-layer acknowledgment containing timing information from the battery-operated communication device. Accordingly, the two devices may re-synchronize their timing based on the timing information in the control packet and acknowledgment, respectively.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: December 31, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Jonathan W. Hui, Lik Chuen Alec Woo, Wei Hong
  • Patent number: 8611471
    Abstract: A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: December 17, 2013
    Assignee: Saankhya Labs Pvt. Ltd.
    Inventors: Saurabh Mishra, Parag Naik, Subrahmanya Kondageri Shankaraiah, S Harish Krishnan, Gururaj Padaki
  • Patent number: 8605759
    Abstract: A device is provided and includes a multiplexer that receives signals and generates an output signal based on a selected one of the signals. The output signal includes frequencies and has a respective signal magnitude at each of the frequencies. A control circuit determines gain values. A transmitter provides pre-emphasis to the output signal to offset a characteristic of a channel, and transmits the output signal with the pre-emphasis on the channel. The transmitter, in providing the pre-emphasis: provides delayed versions of the output signal, where each of the delayed versions of the output signal has a different amount of delay than other delayed versions of the output signal; and amplifies each of the delayed versions of the output signal based on a respective one of the gain values such that certain ones of the signal magnitudes are amplified, and other ones of the signal magnitudes are attenuated.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: December 10, 2013
    Assignee: Marvell International Ltd.
    Inventors: Lei Wu, Timothy Hu
  • Patent number: 8605636
    Abstract: Disclosed is a method capable of minimizing a period of time required for a handover network acquisition procedure when a handover occurs between communication networks which provide communication services using different mobile communication technologies. When a modem for a handover communication network performs network acquisition due to the occurrence of a handover, the modem previously extracts information about a handover channel from a Universal Handover Direction Message (UHDM), and uses the extracted channel information in a network acquisition procedure. Accordingly, the modem for a handover communication network can easily acquire a handover network even without using a preferred roaming list, and can omit an radio frequency (RF) tuning procedure by extracting a corresponding code division multiple access (CDMA) channel from the received UHDM, thereby reducing the total handover processing time period and increasing the success rate of the handover.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: December 10, 2013
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Jeong-Min Noh, Myoung-Hoon Cho