Abstract: Method and device provide for the encapsulation of control information in a real-time data stream. In one embodiment a method of encapsulating data in an information frame is provided. This information frame has a payload portion and a trailer portion wherein the trailer portion is designated for control data and the payload portion is designated for real-time data. In use control data is inserted into the payload portion of the information frame and an extension bit is used to signify the presence of control data in the payload portion of the information frame. The information frame is then transmited over a virtual circuit.

Abstract: The present invention provides a system and method for enabling the synchronization of a switch and an interface device. Based on a comparison of cell sequence numbers included in cells received from the interface device to a current cell time within the switch, cell time adjustment information can be transmitted to the interface device. The cell time adjustment information is used by the interface device to determine the cell sequence number that is included in cells transmitted to the switch.

Abstract: System and method for compensating for DS0 timing source transients, such as may occur during a switchover to a new external reference, is described. In one embodiment, an SFI control signal is monitored for embedded frame position information. When the frame position information is initially detected, a 10-bit frame clock counter is reset to zero. The counter is then incremented using an 8.192 MHz clock. From that point on, each time the SFI frame position information is detected, the value of the frame clock counter is checked. If the counter value is zero, the counter continues to run freely. If the counter value is non-zero and the most significant bit (“MSB”) thereof is zero, the count of the frame clock counter is held for one clock period. If the counter value is non-zero and the MSB thereof is one, the count of the frame clock counter is advanced by a value of two, rather than one, for one clock period.

Abstract: A receiver performing a stable operation in a burst mode is provided. The receiver transmits packet data using a preamble, and has good acquisition performance so that a synchronization part converges on a preamble interval. For the acquisition performance, the receiver senses the carrier of a received signal, detects a rough location of a burst, and in response to the result of carrier sensing, performs coarse gain control, symbol timing compensation, and frame synchronization. Then, if the frame synchronization is completed, in response to the result of frame synchronization, the receiver performs fine gain control, equalization of the signal, and carrier recovery.

Abstract: An interface apparatus has a transmitting section in which first transmission-timing information generating means generates transmission timing information XH, which constitutes timing information of a sending user clock CTU, using a network clock CN and the sending user clock CTU, second transmission-timing information generating means generates test transmission timing information XH′ having any value, a selector selects the transmission timing information XH, which is output by the first transmission-timing information generating means, during ordinary communication, and selects the test transmission timing information XH′ during a test, and cell assembling means assembles sending user data DTU and the transmission timing information XH or XH′ selected by the selector into a fixed-length cell and sends the cell to an opposite interface apparatus.

Abstract: The present invention provides an ATM cell assembling/disassembling apparatus capable of reducing power consumption. A reception VC detector 16 decides whether a reception cell is valid. A reception controller 17 performs disassembling and error check of a cell which has been decided to be valid by the reception VC detector 16 before issuing a DMA transfer request. A DMA output block 12 reads out a reception payload data from a reception data buffer 18 and DMA-transfers the data to a host memory 3. A reception clock controller 20 starts clock supply to the reception controller 17 when the reception VC detector 16 has decided that the reception cell is valid, and terminates the clock supply to the reception controller 17 upon completion of processing for one cell in the reception controller 17.

Abstract: A method for maintaining the states of a receiver during the silent line state of a network device operating in a low power link suspend mode is presented. Accordingly, a method of freezing the states of the equalizer and keeping the receiver clock locked to a frequency that is approximately equal to that of the input data while providing for rapid adjustment to the phase and thus recovery of the input data is presented. During Silent Line State (SLS), the receiver states are frozen using methods that avoid parasitic decay. Also, the receive clock phase lock loop is locked onto the local transmit clock since the local transmit clock has a frequency approximating the incoming data frequency. During the SLS, the transmitter of the remote network device may have been turned off to conserve power therefore the receiver has no way of immediately knowing the phase of an incoming data.

Abstract: A method for the clock recovery in transport in constant bit rate channels(CBR), especially suitable for implementation of the adaptation layer of the asynchronous transfer mode(AAL) which comprises: the use of means for temporarily storing data at receiving end; the use of a clock frequency, with which data are polled out from said storing means, and calculation of a series of time differences(Zk), characterized in that said difference series is sent to a control block where the instant value(Zk) of said differences is multiplied by the value of its own index(k); it is subsequently compared to the sum of the previous values(Zk) considered up to the moment(k−th value); and it is checked that the absolute value of the differences outcoming from said comparison is less of the error(err) multiplied by the index(k−1) of the previous value(Zk) and by the absolute sum value(sum). The invention refers also to an apparatus to carry out such a method.

Abstract: A packet memory system including a memory space having a multiplicity of addressable memory locations for the storage of data packets, pointer control means for generating a write pointer which progressively defines where data is to be written to the memory space and a read pointer which progressively defines where data is to be read from the memory space and an ageing clock which defines a succession of intervals. The pointer control means generates a ‘current’ pointer and a ‘discard’ pointer and for each interval is operative to cause the ‘current’ pointer to correspond to an immediately previous value of the write pointer and to cause the discard pointer to correspond to an immediately previous value of the said current pointer. In this manner the portion of the memory space between the ‘discard’ pointer and the read pointer denotes data which has been in said memory space for at least two of said intervals.

Abstract: Techniques for determining an output rate for a bit stream, the output rate being determined by applying information read from the bit stream to available bandwidths. A digital flywheel provides continuous feedback from an encoding system to a video compression engine in order to assure that the clock rates between the two remain appropriately synchronized.

Abstract: A clock data recovery system is provided for resampling a clock signal according to an incoming data signal stream. It comprises a clock generator for generating said clock signal wherein one of the frequency and phase of that clock signal is dependent upon a control signal. It is further provided a phase detector operable to detect the phase difference between said clock signal and said incoming data signal stream and is operable to generate a phase difference signal. A loop controller has a variable-gain and is operable to control said clock generator by generating said control signal. That control signal is dependent in said phase difference signal and that variable-gain. The variable-gain is dependent upon a transition rate of the incoming data signal stream. The loop controller can comprise a low-pass filter to generate from the phase difference signal a low-pass filered phase signal and to adjust the bandwidth of the clock data recovery system.

Abstract: A byte boundary information recovery mechanism locates the first bits of respective bytes of an asynchronous transfer mode (ATM)-based serial data stream, used by a frame synchronization mechanism to delineate respective cells of the ATM stream, and thereby enables transceiver equipment to successfully receive and parse ATM traffic. The invention employs a counter offset-based scheme that generates an output signal in potential alignment with the (first bit) boundary of a byte of the data stream, in response to the contents of a counter reaching a prescribed count value. It then iteratively shifts, as necessary, the bit time at which the output signal is produced relative to the counting operation of the counter, until the output signal is aligned with the boundary of a byte of the data stream.

Abstract: A phase lock loop is provided for recovering timing information from a received data signal in a 100Base-TX receiver. The phase lock loop includes a phase encoder (803) for generating a reference phase error. An output phase value on a bus (809) is subtracted from the reference phase value on line (805) with a subtraction block (813) to generate a phase error. This phase error is averaged and decimated over a predetermined number of potential symbol transitions in the received signal. The output phase error is provided from a block (815) on a line (817) to a loop filter. This output is provided only once for each decimation operation such that the loop filter can operate at a lower clock rate. The phase error output is then utilized to select one of multiple clocks that correspond to the phase error, these being incremental phase clocks referenced to a master clock. This utilizes a clock multiplexer (1427) to select one of the multiple clock inputs which are delayed in phase off of the master clock.

Abstract: A method for recovering clock signals includes generating a media sync signal to synchronize processing of digital media, and generating a transmission reference clock signal to define a duration of a transaction through a packet-based data network. The media sync and transmission clock signals may have different frequency and phase. The media is sent to a slave node of the network. The media sync and transmission clock signals are correlated to generate phase correlation information, and the phase correlation information is also sent to the slave node. Accordingly, a relatively low cost and reliable clock recovery technique suitable for synchronizing media streams across a packet-based data network is disclosed.

Abstract: An ATM network system of the present invention contains a clock synchronization source and a plurality of nodes. In this ATM network system, a plurality of clock supply routes are set, which are used in receiving clocks from the clock synchronization source by each of the nodes. When each of the nodes detects a failure occurred in the presently used route, each of the nodes supplies a failure signal to other nodes which receive the clock supplied from the own node through this route, and further changes a route under use into another route. When each of the nodes receive the failure signals from other nodes, each of these nodes changes the route under use into another route.

Abstract: In a data communication network, a system clock rate can be inferred at a receiver by measuring the data rate during successive periods. This information is used to adjust or adapt a receiver output clock to the inferred system clock. To adapt a receiver buffer output clock frequency to the buffer input clock frequency, the level of the buffer is periodically monitored. If the fill level is greater than an upper threshold, the output clock frequency is incremented. If the fill level is less than a lower threshold, the output clock frequency is decremented. A count is maintained of the number of successive adjustment operations performed while the fill level is outside the range bounded by the thresholds. When the fill level returns to the bounded range, a number of reverse frequency adjustments are performed. The number of reverse frequency adjustments are less than the number of earlier opposite frequency adjustments, preferably by a factor of two.

Abstract: In an AAL5 jitter reduction method for an image data transmission system for converting MPEG data into ATM cells and transmitting the ATM cells through an ATM line, an addition average value of system time clocks at timings for detecting starts of adjacent transport packets after AAL5 termination is obtained. A transport packet arrival time is corrected on the basis of the obtained addition average value. An AAL5 jitter reduction apparatus is also disclosed.

Abstract: A loose source routing method is provided to transfer an IP packet from a transmission source gateway to a transfer destination gateway by way of ATM nodes, which are freely designated. At the transmission source gateway, the IP packet given from a user LAN is dissolved into ATM cells containing a BOM cell whose destination address designates the transfer destination gateway. In addition, at least one pseudo BOM cell whose destination address designates an ATM node in the ATM network is added and is located at a top place of a cell stream constructed by the dissolved ATM cells. Thus, the cell stream is transferred from the transmission source gateway to the designated ATM node in accordance with the destination address of the pseudo BOM cell. The designated ATM node discards the pseudo BOM cell so that the original BOM cell is now located at the top place of the cell stream.