Bridge Between Bus Systems Patents (Class 370/402)
  • Patent number: 7061926
    Abstract: A method and a system is provided for facilitating communication throughout a master/slave network. The network topology includes a transmission cable being operably connected between the network modules. A master module includes a master terminating resistor operably connected to the transmission cable. A slave module includes a slave terminating resistor and a slave switch. The slave terminating resistor is operably connected to the slave switch. A load resistor is operably connected to the transmission cable. The slave switch is operably responsive to the load resistor to generate a terminate enable. The slave switch inserts the slave terminating resistor onto the transmission cable in response to the terminate enable.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: June 13, 2006
    Assignee: Schneider Automation Inc.
    Inventor: Richard H. Breinlinger
  • Patent number: 7061875
    Abstract: A system and method prevents the formation of loops that are not detected by the Spanning Tree Protocol (STP). An intermediate network device preferably includes a plurality of ports for receiving and forwarding network messages and a STP engine in communicating relationship with the ports. The STP engine transitions the ports among a plurality of spanning tree port states, including a discarding state, a learning state and a forwarding state. The device further includes a loop guard engine that is in communicating relationship with the STP engine and the ports. The loop guard engine monitors the receipt of configuration bridge protocol data unit (BPDU) messages by the ports. If a given port stops receiving BPDU messages, the loop guard engine prevents the STP engine from transitioning the given port to the forwarding state. Instead, the loop guard engine preferably causes the port to transition to a new state in which networks messages are explicitly blocked from being forwarded or received.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: June 13, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: Maurizio Portolani, Shyamasundar S. Kaluve, Marco E. Foschiano
  • Patent number: 7039020
    Abstract: The hybrid circuit can be used to substantially reduce near echo signals. The circuit includes a balanced 2-wire to 4-wire hybrid for interconnecting a two wire receive path and a two wire transmit path to a two wire transmission line. The two wire receive path connects the balanced hybrid to an A/D converter and the two wire transmit path connects a D/A converter to the balanced hybrid. The two wire receive path contains a filter, dimensioned to remove signals transmitted from the D/A converter. The invention is particularly adapted for use with FDD and OFDD.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: May 2, 2006
    Assignee: STMicroelectronics N.V.
    Inventors: Gunnar Bahlenberg, Daniel Bengtsson, Siwert Hakansson, Anders Isaksson, Lars-Ake Isaksson, Mikael Isaksson, Magnus Johansson, Mauritz Lahti, Lis-Marie Ljunggren, Hans Lundberg, Tomas Nordstrom, Lennart Olsson, Sven-Rune Olofsson, Tomas Stefansson, Hans Oman, Goran Okvist, Per Odling, Petra Dentgen, Franck Sjöberg
  • Patent number: 7035957
    Abstract: A PCI bridge circuit connects to first and second PCI buses and performs data transfer between PCI devices. The PCI bridge circuit has a data buffer and controller and the controller 70, prior to the establishment of a data transfer state with the first PCI device via the first PCI bus, receives data from the second PCI device via the second PCI bus into a data buffer and inserts a wait state. Consequently while reducing the capacity of the data buffer, data transfer between PCI devices can be performed without affecting the transfer performance.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: April 25, 2006
    Assignee: Fujitsu Limited
    Inventor: Yasuo Ishiwata
  • Patent number: 7027411
    Abstract: A method and system are disclosed for mapping the topology of a network having interconnected nodes by identifying changes in the network and updating a stored network topology based on the changes. The nodal connections are represented by data tuples that store information such as a host identifier, a connector interface, and a port specification for each connection. A topology database stores an existing topology of a network. A topology converter accesses the topology database and converts the existing topology into a list of current tuples. A connection calculator calculates tuples to represent connections in the new topology. The topology converter receives the new tuples, identifies changes to the topology, and updates the topology database using the new tuples. The topology converter identifies duplicate tuples that appear in both the new tuples and the existing tuples and marks the duplicate tuples to reflect that no change has occurred to these connections.
    Type: Grant
    Filed: October 31, 2000
    Date of Patent: April 11, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Eric A Pulsipher, Joseph R Hunt
  • Patent number: 7028130
    Abstract: A system having a PCI Express fabric and PCI devices connected thereto transmits data from the PCI devices having PCI Express traffic classes assigned. A PCI Express to PCI bridge assigns a predetermined address to the grant line for each PCI device coupled to the PCI bus and stores this address along with the data from the PCI device in the PCI transaction queues. When the data is transmitted along the PCI Express fabric, or when it is processed within the PCI Express to PCI bridge, the address assigned to the respective grant line becomes the PCI Express traffic class for that data. This enables the commands from one device to be processed irrespective of commands from other PCI devices on the PCI bus.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: April 11, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Andrew W. Lueck, Kevin K. Main
  • Patent number: 7027451
    Abstract: A dynamic break loop capable closed loop network having a plurality of switches and links. Each switch has two uplink ports that each have a set of dynamic break loop logic functions that may be enabled or disabled. The dynamic functions include inserting an ID number of a source switch into each frame that is transmitted from the switch, enabling a transmit function of each uplink port to monitor the ID number of each frame, and enabling a receive function of each uplink port to monitor the ID number of each frame. If the ID number is not equal to a filter ID number, then the frame will pass unchanged. If the ID number is equal to the filter ID number, then the frame will be cut off and will not be allowed to pass. The dynamic functions create a dynamic break for each switch in the network. The result is a closed loop network that operates dynamically as a plurality of open loop networks.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: April 11, 2006
    Assignee: LSI Logic Corporation
    Inventor: Mark Chiang
  • Patent number: 7024508
    Abstract: Described is a bus station (e.g., a sensor, an actuator, a gateway) which performs a primary device function and a secondary function (e.g., a bus monitor function). To perform the secondary function, the bus station is equipped with a bus monitor arrangement which allows the bus station to access, to detect and to further process telegram traffic carried on the bus system. Also described is a network equipped with a plurality of such bus stations and a method for carrying out such monitoring with the aid of the bus stations.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: April 4, 2006
    Assignee: Vega Grieshaber KG
    Inventors: Thomas Gros, Fridolin Faist
  • Patent number: 7007126
    Abstract: An I/O subsystem having a processor, a bridge unit, and an I/O messaging unit that couple a primary, secondary and tertiary bus in a computer system. The bridge unit is configurable to claim requests that access a messaging unit (MU) address range from the secondary bus, the MU itself being coupled to the primary bus. The MU interrupts the processor when an I/O request is posted, in response to which the processor reads from the MU pointers to an I/O messages and may then execute the I/O message. To promote the portability of software written for agents on either the primary or the secondary bus that wish to access the MU, the primary and secondary address translation units of the I/O subsystem are programmed to claim the same address translation window, where the MU address range is a portion of the primary ATU address translation window, and the secondary ATU is configured to not claim requests within the MU address range.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: February 28, 2006
    Assignee: Intel Corporation
    Inventors: Byron R. Gillespie, Barry R. Davis, William Futral
  • Patent number: 6996659
    Abstract: An apparatus comprising a plurality of first circuits and a second circuit. Each of the first circuits may be configured to translate attributes and data between one of a plurality of first predetermined formats and a second predetermined format. The second circuit may be configured to route the attributes and data in the second predetermined format from one of the first circuits to another of the first circuits.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: February 7, 2006
    Assignee: LSI Logic Corporation
    Inventors: Gordon F. Lupien, Jr., Dimitry Paylovsky, David C. Maslyn, Jr.
  • Patent number: 6993022
    Abstract: Within the routing method and apparatus of the present invention, a router is coupled to multiple buses, each of the buses having one or more nodes. A node on a first bus structure sending a communication to a node on a second bus structure includes an address value within the communication addressed into the address space of the router. When the packet is received, the router then preferably uses a routing value within the address value to determine the bus number and node number of the target node. The router then uses this bus number and node number to remap the address value to the target node. This remapped address value is then included within the packet and transmitted on the appropriate bus structure directed to the appropriate node. In an alternate embodiment, the address value in a packet received by the router includes a table index value and a direct offset value.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: January 31, 2006
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: David V. James, Hisato Shima, Bruce Alan Fairman
  • Patent number: 6981078
    Abstract: A fiber channel backplane configuration is capable of modular expansion, e.g., from 64 ports to 128 ports or 256 ports by a simple operation. The backplane includes connectors that provide permanent and jumper/vertical connections to support 64 user port switch in a single chassis. For a 128 port switch, two 64 port chassis are used. In the 128 port configuration, the connectors are configured to provide permanent and jumper/vertical connections to make intra-chassis and inter-chassis connections between the fabric switch and fabric input/output boards. Using jumper plugs, the jumper connectors provide vertical connections between the fiber input/output boards and fiber switch boards of two chassis. For a 256 port switch configuration, four 64 port chassis assemblies are used. The connectors are configured to provide each switch with permanent, vertical, horizontal, and diagonal connections to the fiber input/output boards of each of the four chassis.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: December 27, 2005
    Assignee: Computer Network Technology Corporation
    Inventor: Harry V. Paul
  • Patent number: 6975634
    Abstract: Integration of packet/cell networking of a wired/wireless network with ATM is achieved by application of a distributed architecture including an ATM network adapted to provide such integration. Network and protocol conversion between the wired/wireless network and the ATM network is performed by a gateway (GAGW) having capabilities to perform this function. A mobility server platform (MSP) handles routing between the gateways to other networks and the micro-mobility functions of the wireless base stations directly connected to the ATM network. A Inter-working function (IWF) element connects base stations (BS) or mobile switching centers (MSC) to ATM switch/routers and in the process provides various protocol conversions necessary to integrate various services into the ATM backbone. The integration of these networks is seamless with little apparent affect on the end point users of the ATM network on the overall system.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: December 13, 2005
    Assignee: AT&T Corp.
    Inventors: Albert T. Chow, Jinman Kim, Robert Raymond Miller, II, Wenchu Ying
  • Patent number: 6973527
    Abstract: An electrical circuit for a bus interface and/or a bus bridge is described. The electrical circuit comprises a global master being coupled with a first bus and at least one function block being coupled with the global master. An address and/or data is transmitted from the first bus to the function block. The function block comprises a application specific functionality for carrying out a function in connection with the received address and/or data.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: December 6, 2005
    Assignee: Agilent Technologies, Inc.
    Inventor: Bernhard Holzinger
  • Patent number: 6959398
    Abstract: An application specific integrated circuit (ASIC) employs various logic blocks. The blocks may include logic circuits that operate at different clock rates. Consequently, an interface logic block may be needed to efficiently transfer signals from one frequency clock domain to another. One such interface, known as a universal asynchronous boundary module (UABM) is situated between the two domains allowing communication between the logic circuits.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: October 25, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Paras A. Shah, Prashantha Kalluraya
  • Patent number: 6952421
    Abstract: A method and apparatus for discovering paths to other network devices includes a protocol and network management application that can be executed on network devices. The Ethernet protocol is used to detects paths to other network devices, knowing only the Ethernet address of the destination. A discovery protocol is extended to add hop probe and hop probe reply Type-Length-Value fields in a variable-length list. The hop probe fields contain a hop count, a destination Ethernet address, and a source Ethernet address. When a hop probe is received by a network device, the hop count field is decremented by one and the hop probe is forwarded. Packet received with a hop count of one are not forwarded and a hop probe reply is sent back to the Ethernet source address of the hop probe. The hop probe reply fields contain a destination Etherned address and a source Ethernet address.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: October 4, 2005
    Assignee: Cisco Technology, Inc.
    Inventor: Charles Slater
  • Patent number: 6950408
    Abstract: In a speed converter for an IEEE-1394 serial bus network, first and second communication device nodes are attached to first and second buses. A first transceiver node receives an inbound first packet at a first speed from the first bus and transmits an inbound second packet, which is received from the second bus by a second transceiver node at a second speed, as an outbound second packet at the first speed to the first bus. The second transceiver node transmits the inbound first packet as an outbound first packet at a second speed to the second bus. Header translation circuitry translates the destination identifier of the inbound first packet to the destination identifier of the outbound first packet according to a mapped relationship between the first transceiver node and the second communication node, and translates the destination identifier of the inbound second packet to the destination identifier of the outbound second packet.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: September 27, 2005
    Assignee: NEC Corporation
    Inventors: Wataru Domon, Jun-ichi Matsuda, Shuntaro Yamazaki
  • Patent number: 6931017
    Abstract: A “Burst Ratio” is defined for use as a measure of the burstiness of a packet-based network. One illustrative implementation of the Burst Ratio (R) is where R is equal to the ratio of the average length of observed bursts in a packet arrival sequence over the average length of bursts expected for a random loss packet-based network. Another illustrative implementation of the Burst Ratio (R) is in the context of a 2-state Markov model, wherein R=1/(1+???), and ? is the probability of losing packet n if packet n?1 was found (i.e., the probability of losing the next packet if the current packet was received) and ? represents the probability of losing packet n if packet n?1 was lost (i.e., the probability of losing the next packet if the current packet was lost).
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: August 16, 2005
    Assignee: Lucent Technologies Inc.
    Inventor: James William McGowan
  • Patent number: 6917621
    Abstract: The present invention supports a packet-based communication by emulating the functions of an enhanced mobile radio system. The communication device executes emulation software to support simplex communications, as well as other communication features such as voice mail, electronic mail, or public switched telephone network communications. Communications to and from the devices configured with emulation software can also be controlled with a presence routine.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: July 12, 2005
    Assignee: Nortel Networks Limited
    Inventor: Andrew Silver
  • Patent number: 6914895
    Abstract: A process for synchronization in a communications network comprising at least two buses interconnected by a wireless communications network, each bus being linked to the wireless communications network by a portal. The process comprises the steps of: determining a so-called cycle server portal whose own clock will serve as a reference for the other portals; transmitting, via each portal, a synchronization signal at a predetermined instant with respect to the start of a frame and characteristic of each portal, the frame being defined with respect to each portal's own internal clock, the synchronization signal being achieved via the insertion of a control window; and detecting, via each portal, the control windows of other portals and selecting one of the detected windows for the synchronization of the receiver portal's own clock with the clock of the cycle server portal, the selected window corresponding to a portal whose clock is already synchronized with that of the cycle server portal.
    Type: Grant
    Filed: April 21, 1999
    Date of Patent: July 5, 2005
    Assignee: Thomson Licensing S.A.
    Inventors: Gilles Straub, Helmut Buerklin, Vincent Demoulin, Renaud Dore, Patrick Lopez
  • Patent number: 6904043
    Abstract: A network switch configured for switching data packets across multiple ports uses an internal memory to store frame headers for processing by decision making logic. The internal memory stores frame headers in a queue configured to store a number of the frame headers for each of the receive ports. A scheduler is included for facilitating the transfer the data from the queues to the decision making logic according to a predetermined priority. The scheduler is also able allocate the time slots in accordance with data traffic at the corresponding receive ports to maximize data throughput.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: June 7, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shashank Merchant, Ching Yu
  • Patent number: 6901465
    Abstract: A data transfer control device using USB (a first bus), the end of a data phase (data transport: transfer of all the data) during an OUT transaction is determined on condition that data transmission (DMA transfer) through EBUS (a second bus) has ended, and the end of a data phase during an IN transaction is determined on condition that data reception through EBUS has ended and also an Empty signal has gone active, indicating that a data storage area has become empty. A counter that counts the data size is provided on the EBUS side. If data reception through EBUS ends and the size of data remaining in the data storage area is less than the maximum packet size, a short packet in the data storage area is transmitted automatically through USB and an interrupt is used to notify the firmware of the presence of the short packet.
    Type: Grant
    Filed: April 29, 2002
    Date of Patent: May 31, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Yoshiyuki Kamihara, Takuya Ishida
  • Patent number: 6901076
    Abstract: A network device dynamically switches between layer 2 (data link) operation and layer 3 (network) operation. When enabled, bridging logic functions as a data link bridge, receiving data link messages from communications links forming part of a single network-layer segment and forwarding the messages to another communications link using layer-2 addresses in the messages. When enabled, routing logic functions as a network router, receiving network layer messages from different network-layer segments and forwarding the messages to other links based on a routing algorithm and the network layer addresses. Selection logic dynamically selects the desired function under different operating conditions. For a transition from router to bridge, multiple network-layer segments are merged into a single bridged network-layer segment, freeing up link numbers for use in configuring addresses for other segments.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: May 31, 2005
    Assignee: Sun Microsystems, Inc.
    Inventors: Radia J. Perlman, Eric A. Guttman
  • Patent number: 6895462
    Abstract: An integrated circuit includes a processor and at least one module and provides registers required for the modules as well as access to these registers. By concentrating the required registers according to the invention in a central register bank, which like the processor and the modules is connected to a fast AMBA-AHB bus, several advantages are achieved: for one, faster access is possible to each register. For another, the placement of the registers and the routing for the registers is simplified. This in particular allows chip area to be saved, which leads to cost savings in manufacture and enables higher component density. Furthermore, a slow AMBA-APB bus has now become optional.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: May 17, 2005
    Assignee: Alcatel
    Inventors: Carl Roger Pertry, Heiko Meyer, Thomas Schulz
  • Patent number: 6885670
    Abstract: The disclosure relates to apparatus and methods that provide a system interconnect for transporting cells between nodes on a dual counter-rotating ring network, including a link selection register for selecting the shortest path to a destination node, use of a fault tolerant frequency reference to synchronize node clocks, interconnect initialization, multi-ring topologies along with an addressing schema and ring-to-ring couplers. The disclosure also discusses flow control of cells leaving nodes, coupling cells from one ring to another, and use of such an interconnect as a bus replacement.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: April 26, 2005
    Assignee: PLX Technology, Inc.
    Inventor: Jack Regula
  • Patent number: 6885667
    Abstract: Methods and apparatus for sending a redirect packet to a host by a first router that supports a virtual router protocol are disclosed. Specifically, the redirect packet notifies the host that specific packets are to be redirected to a second router. First, the first router receives a packet from a host, where the packet includes a source address identifying the host and a destination address identifying a destination network. The first router ascertains the destination network of the packet from the destination address and obtains from a routing table an address of a next router that is coupled to the packet's destination network. The first router then determines whether to send a redirect packet to the host. In accordance with one embodiment, this is performed by determining whether the next router and the host identified by the source address of the packet are on the same network.
    Type: Grant
    Filed: December 26, 2000
    Date of Patent: April 26, 2005
    Assignee: Cisco Technology, Inc.
    Inventor: Ian Wilson
  • Patent number: 6882651
    Abstract: A method and apparatus for controlling the flow of data units across a bus bridge and an inter-bus communication system employing same is disclosed. In accordance with the method, the apparatus detects operational states of the bridge and disables load access to the bridge when a first predefined operational state exists and enables load access when a second predefined operational state exists.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: April 19, 2005
    Assignee: Nortel Networks Limited
    Inventors: Norbert Wegner, Peter Arkadjevich Bliznyuk-Kvitko
  • Patent number: 6879593
    Abstract: A connection is established between a node on a first network and at least one node on a second network lacking a valid address on the first network by receiving at a gateway a connection request from the node on the first network, sending information related to the connection request to a plurality of nodes on the second network, receiving responses to the sent information from at least one of the nodes on the second network, and establishing at least one connection between at least one of the nodes on the second network from which responses are received, and the node on the first network, according to the order of the received responses or according to priority weighting information or according to priority weighting information concerning the nodes from which the responses are received.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: April 12, 2005
    Assignee: Intel Corporation
    Inventors: Aaron R. Kunze, Jim W. Edwards, Christian Dreke
  • Patent number: 6876642
    Abstract: A wireless local area network communication system for a vehicle to provide a voice and/or data connection from a wireless wide area network to a wireless local area network and on to a vehicle wired bus is disclosed. The communication system includes a wireless electronic communication device disposed in or in proximity to the vehicle for communication with the wireless wide area network, a wireless local area network unit disposed in the vehicle in such a manner as to communicate with the wireless electronic communication device and with a wired vehicle bus disposed within the vehicle, and a plurality of electronic devices disposed in or in proximity to the vehicle and in communication with the local area network unit or the wireless electronic communication device.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: April 5, 2005
    Assignee: Delphi Technologies, Inc.
    Inventors: Jay James Adams, Ronald Kent Reger
  • Patent number: 6873849
    Abstract: This invention provides a method intended to solve Number Portability in origin for calls to ported subscribers at a destination classical network, an inter-working function intended to provide the means to support said method, and a hierarchical DNS structure able to provide a new URI indicating interworking with an external database where routing data for said ported subscribers reside. This new URI specifies the Global Title address of the external database and the access protocol to said external database. The NAPTR resolution for that URI implies the use of an Inter-working Feature (IWF) placed in the DNS-resolver part of an S-CSCF, or in a close association, in the originating network. This IWF comprises a Protocol Translator and Controller adapting between DNS format and the external database access protocol format, at least one of a plurality of Application Protocol Handling Modules, and an SS7 Protocol Stack.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: March 29, 2005
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventors: Vincente de Vega de la Red, Roberto David Carnero Ros
  • Patent number: 6871075
    Abstract: An additional parameter is added to be used in parallel or together with a generic “load” value currently proposed for communication between a first radio network controller (controller which performs the measurement) and a second radio network controller suggesting a proposed action. Because the second controller receives the proposed action, it can take the proposed or other appropriate action in order to solve the congestion situation in the first controller more effectively in a multi-vendor environment.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: March 22, 2005
    Assignee: Nokia Mobile Phones Ltd.
    Inventors: Woonhee Hwang, Mattias Wahlqvist
  • Patent number: 6868086
    Abstract: A distributed device has external ports and a configurable internal communications network interconnecting the external ports. The network is configured to transmit a data packet received from one of the ports to a second of the ports according to a communications protocol of the internal network. The second of the ports connects to a destination of the data packet.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: March 15, 2005
    Assignee: Intel Corporation
    Inventors: David M. Putzolu, Erik J. Johnson
  • Patent number: 6862646
    Abstract: The specification discloses a method and related system that allows hardware devices to participate in the coherency domain of a computer system. More particularly, hardware devices such as network interface cards, audio cards, input/output cards, and the like, are allowed to participate on at least a limited basis in the coherency domain by having cache memory that duplicates a FIFO buffer in main memory used to exchange information between software and the hardware. To exchange information, software writes to the FIFO buffer which invalidates the data in the cache-type memory of the hardware device, and the invalidation message acts to notify the hardware device of the availability of information in the FIFO buffer.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: March 1, 2005
    Inventors: Thomas J. Bonola, John E. Larson, Sompong P. Olarig
  • Patent number: 6850495
    Abstract: Limiting or controlling access to various services thereby performing a firewall function. An access router may permit or deny a packet based on at least a portion of a unique bit string (or context information) which replaced layer 2 header information (e.g., the layer 2 (e.g., MAC) address). Further, a particular quality of service may be indicated by at least a part of the unique bit string (or context information). The service provided to a group of customers, that group of customers being defined by at least a portion of the unique bit string (or context information), may be monitored. Multicast groups may be supported by checking at least a part of the unique bit string (or context information) to determine whether or not a customer associated with that port is permitted to join the multicast group.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: February 1, 2005
    Assignee: Verizon Communications Inc.
    Inventors: Robert T. Baum, Eric A. Voit
  • Patent number: 6839788
    Abstract: A network storage controller for transferring data between a host computer and a storage device, such as a redundant array of inexpensive disks (RAID), described. The network storage controller includes at least one channel interface module which is adapted to be connected to the host computer and storage device. The network storage controller also includes at least one controller memory module, attached to a passive backplane. The controller memory module communicates with the channel interface module. In applications where redundancy is required, at least two controller memory modules and at least two channel interface modules are used. The controller memory modules may mirror data between one another using the passive backplane and a shared communication path on the channel interface modules.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: January 4, 2005
    Assignee: Dot Hill Systems Corp.
    Inventor: Victor Key Pecone
  • Publication number: 20040264484
    Abstract: A method and system for administering bridge ports for a network are provided. In one embodiment, a method for administering bridge ports for a network includes retrieving information associated with a plurality of switches, the information including at least identifiers of bridging ports of the switches and propagation statuses of the bridging ports. The information for the plurality of switches is displayed through an interactive display. The interactive display is operable to receive updates through the interactive display to at least one of the propagation statuses of at least one of the bridging ports of at least one of the switches. The at least one propagation status is changed based on the updates.
    Type: Application
    Filed: January 15, 2004
    Publication date: December 30, 2004
    Inventors: Ping H. Kui, Joseph M. McAndrews, Fang Yang
  • Publication number: 20040252707
    Abstract: A system for maintaining network information. The system resides in a network comprising a plurality of sub-networks in communication with one another over a communications backbone. Each sub-network has a router for use in performing communications with other sub-networks. A directory service is linked to the communications backbone and includes a database. The database stores router attribute information that is published by each of the routers. Using a query engine associated with the directory service, meaningful information can be gathered from the database as a function of specified router attribute information.
    Type: Application
    Filed: June 24, 2004
    Publication date: December 16, 2004
    Applicant: Microsoft Corporation
    Inventors: Kenneth Lynn Crocker, Wei Jiang, Gurdeep Singh Pall, Bernard D. Aboba, Narendra C. Gidwani
  • Patent number: 6813250
    Abstract: A shared spanning tree protocol (SSTP) creates a plurality of spanning trees (i.e., loop-free paths) which are shared among one or more virtual local area network (VLAN) designations for data transmission within a computer network. Each shared spanning tree includes and is defined by a primary VLAN and may be associated with one or more secondary VLANs. In order to associate VLAN designation(s) with a single shared spanning tree, network devices exchange novel shared spanning tree protocol data units (SST-PDUs). Each SST-PDU corresponds to a given primary VLAN and preferably includes one or more fields which list the secondary VLAN designations associated with the given primary VLAN. The association of VLAN designations to shared spanning trees, moreover, preferably depends on which path traffic is to follow as well as the anticipated load characteristics of the various VLANs. The association of VLAN designations to shared spanning trees thus provides a degree of load balancing within the network.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: November 2, 2004
    Assignee: Cisco Technology, Inc.
    Inventors: Michael Fine, Silvano Gai, Keith McCloghrie
  • Patent number: 6801970
    Abstract: Support for indicating and controlling transaction priority on a PCI-X bus. Embodiments of the invention provide indicia that can be set to communicate to PCI-X-to-PCI-X bridges and Completer that a transaction should be handled specially and scheduled ahead of any other transaction not having their corresponding indicia set. A special handling instruction allows the priority transaction to be scheduled first or early. The indicia are implemented by setting a bit(s) in an unused portion of a PCI-X attribute field, or multiplexed with a used portion, to schedule the associated transaction as the priority transaction over other transactions that do not have their corresponding bit set. The present invention can be used for interrupt messaging, audio streams, video streams, isochronous transactions, or for high performance, low bandwidth control structures used for communication in a multiprocessor architecture across PCI-X.
    Type: Grant
    Filed: September 30, 2001
    Date of Patent: October 5, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Dwight D. Riley, Chris Pettey
  • Publication number: 20040179541
    Abstract: A method and system for dial-up device connection to a broadband facility by way of a home gateway. The microcomputer causes the dial-up modem in the home gateway to serve as a host modem. The microcomputer also implements the host portion of a log-in protocol that is expected by the dial up device, in this example the IRD's. Within the IRD itself, a software download causes the dial-up modem in the IRD to not go “off-hook” when starting a callback. The local office, i.e. the PSTN, will not recognize the start of a dial-up session and will not issue a dial tone. The home gateway and the IRD's will carry out a protocol that does not require the recognition of “off-hook”.
    Type: Application
    Filed: March 12, 2003
    Publication date: September 16, 2004
    Inventor: John P. Godwin
  • Patent number: 6791974
    Abstract: The universal Internet based telephony system is implemented as a process that is accessible via an Internet WEB page and executes on the WEB server that hosts the WEB page and/or a back-end Internet telephony server which is accessed and controlled by the WEB server. The customer accesses the universal Internet based telephony system via any existing Java Enabled Internet Browser software resident on the customer's personal computer, either as an adjunct process thereon, or as a dedicated Internet telephony process. When a customer accesses the Internet WEB page and clicks on the universal Internet based telephony system icon, the WEB server on which the WEB page resides executes the resident universal Internet based telephony system hyperlink script and transfers a newly opened browser session to the universal Internet based telephony system WEB site.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: September 14, 2004
    Assignee: eStara, Inc.
    Inventor: Jeffrey Douglas Greenberg
  • Patent number: 6792495
    Abstract: A method of and apparatus for communicating data using a hub. The method includes the step of buffering a single transfer request received at a hub during a transaction between the hub and a host controller, where the single transfer request is to be performed between the hub and an agent to generate a result. The method then includes the step of determining whether a transfer inquiry received at the hub from the host controller corresponds to the result.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: September 14, 2004
    Assignee: Intel Corporation
    Inventors: John I. Garney, John S. Howard
  • Publication number: 20040174890
    Abstract: A network switch chip and a method for controlling the same are proposed. A first network switch chip is cascaded with a second network switch chip. Each of the network switch chip comprises a high-speed network port and a plurality of connection ports. The two network switch chips are connected through the two high-speed network ports to form a direct link therebetween, and the network switch provides a transmission rate equal to the sum of transmission rates of the first connection ports and the second connection ports. The two network switch chips can update an operation status for each other through the direct link and whereby the first network switch chip and the second network switch can manage data exchange therebetween. Each of the network switch chips has a lookup table therein and the network switch chips can update the lookup table for each other.
    Type: Application
    Filed: March 4, 2003
    Publication date: September 9, 2004
    Inventors: Murphy Chen, Sharon Huang
  • Patent number: 6789130
    Abstract: Automatic speed adaptation system in a Local Area Network (LAN) between a hub (10) including a hub adapter (20, 24, 28) and at least a workstation (12, 14, 16) including a workstation adapter (18, 22, 26) for exchanging data over a link connected between the hub adapter and the workstation adapter at a rate based on a frequency which is inversely proportional to the length of the link. Each adapter comprises a clock generator for generating a clock having a frequency between F1 and F2 and processing means for transmitting at least a check frame from the hub adapter to the workstation adapter at a rate based on a frequency VCLK generated by the clock generator under the control of the processing means and selected as being the frequency corresponding to the length of the link, and for transmitting an acknowledge frame from the workstation adapter to the hub adapter thereby ascertaining that the selected frequency is the right frequency resulting in the best quality of transmission.
    Type: Grant
    Filed: May 16, 2000
    Date of Patent: September 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: Alain Benayoun, Jean-Francois Le Pennec, Michel Verhaeghe, Patrick Michel
  • Patent number: 6788700
    Abstract: A method and apparatus are described for interfacing between a network interface and a bus. For the network interface-to-bus side, the method comprises (a) forming a network address of a message transferred via the network interface to the bus, and (b) mapping the network address to a bus address of the bus, the bus address being within an address space occupied by a bus device coupled to the bus. For the bus-to-network interface side, the method comprises (a) forming a bus index from a bus address of the bus where the bus address is within an address space occupied by a bus device coupled to the bus; and (b) mapping the bus index to a network address of a message transferred via the network interface to the bus.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: September 7, 2004
    Assignee: Cisco Technology, Inc.
    Inventor: Harshad Nakil
  • Patent number: 6778543
    Abstract: The invention concerns a method of controlling the synchronization in a data packet communication network (10) having at least two serial communication buses (D, E) interconnected by a bridge (PDE) and each defining successive time cycles each having a duration specific to the said bus under consideration, the said method having the following steps: detection (C3, C4) of a relative drift between the respective cycles of the said at least two serial communication buses, transmission (C10, C12; C18, C17) of a command for modifying the duration of the cycle of one of the said at least two serial communication buses, characterised in that the said method includes at least one delay phase (C6, C7; C2, D1, D2) before at least one of the preceding steps.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: August 17, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Laurent Frouin, Jean-Paul Accarie, Yacine Smail El Kolli, Falk Tannhauser
  • Patent number: 6778542
    Abstract: The present invention relates to an apparatus and a method for bridging of Ethernet frames between a subscriber LAN and the ATM network. In accordance with the invention a novel (time window discovery) method is used, with coordination of the network administrator and an access management system to provision a network bridging element or bridge with a set of provisioned devices authorized to forward data packets across the bridge. The bridge is allowed within a time window to learn machine-specific MAC addresses for the provisioned table. After the window is expired, or terminated by access management system, the bridge is switched back to learning mode to learn additional MAC addresses for a learned table in the traditional manner. The devices learned during the learning phase are not authorized to forward data packets across the bridge.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: August 17, 2004
    Assignee: Alcatel
    Inventors: Mudhafar Hassan-Ali, Mark W. Cole, Kevin A. Jaeger
  • Patent number: 6771612
    Abstract: A full duplex interface apparatus for a high performance serial bus is provided. More particularly, an IEEE 1394 interface apparatus is provided which includes a port switch having two ports coupled to a source generator device and a display device and separately receiving and buffering received signal packet data streams from the physical layer and transmit signal packet data streams for transmission over the physical layer. Accordingly, by coupling the source generator unit which generates signals for transmission over the physical layer through a first port of the port switch and the display unit to a second port of the port switch, ISO signals such as video signals may be received from the physical layer and provided to the display unit at the same time as ISO signals are being transmitted from the source generator unit to the physical layer through the port switch.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: August 3, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seong-Hyun Park
  • Patent number: RE38821
    Abstract: An Ethernet controller, for use within an Ethernet network of other Ethernet controller connected together by a bus, is provided. The Ethernet controller includes a plurality of ports including at least one bus port associated with ports connected to other switching Ethernet controllers, a hash table for storing addresses of ports within the Ethernet network, a hash table address control, a storage buffer including a multiplicity of contiguous buffers in which to temporarily store said packet, an empty list including a multiplicity of single bit buffers, a packet storage manager, a packet transfer manager and a write-only bus communication unit. The hash table address control hashes the address of a packet to initial hash table location values, changes the hash table location values by a fixed jump amount if the address values stored in the initial hash table location do not match the received address, and provides at least an output port number of the port associated with the received address.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: October 11, 2005
    Assignee: Marvell Semiconductor Israel Ltd.
    Inventors: David Shemla, Avigdor Willenz
  • Patent number: RE39116
    Abstract: Support for a mixed network environment is provided which can contain multiple isochronous and/or non-isochronous LAN protocols such as Isochronous-Ethernet. Ethernet, isochronous-token ring, token ring, other isochronous-LAN or other LAN Systems. Support for a mixed environment includes a protocol detection mechanism which is embodied in a handshaking scheme. This handshaking scheme determines the signalling capability at the end points of the link and implements the correct protocol. This enables isochronous nodes and hubs to automatically detect the presence of Ethernet, token ring, or other LAN equipment at the other and of the network cable. If this detection occurs, the isochronous LAN equipment will fall-back to a LAN compliant mode of operation. Typically, only the hub will have the capability of operating at different networking modes, such as Ethernet, Token Ring isochronous modes.
    Type: Grant
    Filed: April 1, 1999
    Date of Patent: June 6, 2006
    Assignee: Negotiated Data Solutions LLC
    Inventors: Ramin Shirani, Brian C. Edem