Having Both Input And Output Queuing Patents (Class 370/413)
  • Patent number: 8837503
    Abstract: Disclosed are methods, systems, paradigms and structures for processing data packets in a communication network by a multi-core network processor. The network processor includes a plurality of multi-threaded core processors and special purpose processors for processing the data packets atomically, and in parallel. An ingress module of the network processor stores the incoming data packets in the memory and adds them to an input queue. The network processor processes a data packet by performing a set of network operations on the data packet in a single thread of a core processor. The special purpose processors perform a subset of the set of network operations on the data packet atomically. An egress module retrieves the processed data packets from a plurality of output queues based on a quality of service (QoS) associated with the output queues, and forwards the data packets towards their destination addresses.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: September 16, 2014
    Assignee: Unbound Networks, Inc.
    Inventors: Damon Finney, Ashok Mathur
  • Patent number: 8824321
    Abstract: A multi-function device capable of executing a plurality of functions, the device comprising: a first acquisition unit configured to acquire communication state information relating to a current communication state of the multi-function device; a determination unit configured to determine: a first priority order in a case of a first state indicating that the current communication state of the multi-function device is good; and a second priority order in a case of a second state indicating that the current communication state of the multi-function device is poor, wherein the second priority order is different from the first priority order, and wherein each of the priority orders indicate each of priorities of the plurality of functions; and a data transmission unit configured to execute preferentially a transmission of data for a high-priority function earlier than a transmission of data for a low-priority function, based on the determined priority order.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: September 2, 2014
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Hiroshi Shibata
  • Patent number: 8817806
    Abstract: An apparatus and a method for flow control between a Packet Data Convergence Protocol (PDCP) layer and a Radio Link Control (RLC) layer in a communication system are provided. The method includes storing Service Data Units (SDUs) to be transferred to the RLC layer, receiving information on a capacity that is currently unused in a buffer of the RLC layer from the RLC layer, and generating Packet Data Units (PDUs) from SDUs, a capacity of which corresponds to the information, among packets stored in a buffer of the PDCP layer, and then transferring the generated PDUs to the RLC layer.
    Type: Grant
    Filed: February 1, 2011
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Sook Kim, Byung-Suk Kim, Seong-Ryong Kang, Chul-Ki Lee, Hong-Kyu Jeong
  • Patent number: 8811419
    Abstract: A relay device relays between two TCP communication items of a LAN side and a WAN side. When a line bandwidth of the WAN side is smaller than a line bandwidth of the LAN side, buffer overflow in a LAN side reception buffer and a WAN side transmission buffer of the relay device is prevented, and a connection is prevented from being forced to be canceled. A value of a reception window size (rwnd) described in an ACK packet returned to a transmission terminal of the LAN side is controlled based on a transmission throughput, a discarding rate, and an RTT measured in TCP communication of the WAN side, and a total size of unarranged data and a size of arranged data in a reception buffer of the LAN side and a size of untransmitted data and ACK awaiting data in a transmission buffer of the WAN side.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: August 19, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Takashi Isobe
  • Patent number: 8811386
    Abstract: An improved packet handler for VoIP cable modems and other high-speed digital devices includes a direct communication link via hardware among internal processing components. Incoming and outgoing digital information packets are filtered into MAC packets, voice PDU packets, and non-voice PDU packets, such that priority can be given to relaying voice packets and minimizing potential voice delay within the cable network. Hardware components, including specialized logic circuitry, modify voice packets to an appropriate signal form for subsequent signal processing or signal transmission. Proprietary bus communication protocols can also be provided to facilitate relay of packets between a central processing unit (CPU) and a digital signal processor (DSP) within a VoIP cable modem. Line cards including subscriber line interface circuit (SLIC) and subscriber line audio processing circuit (SLAC) components provide analog-to-digital (A/D) and digital-to-analog (D/A) conversion functionality.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: August 19, 2014
    Assignee: Rockstar Consortium US LP
    Inventor: Russell T. Enderby
  • Patent number: 8811417
    Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: August 19, 2014
    Assignee: Mellanox Technologies Ltd.
    Inventors: Noam Bloch, Gil Bloch, Ariel Shachar, Hillel Chapman, Ishai Rabinovitz, Pavel Shamis, Gilad Shainer
  • Patent number: 8811418
    Abstract: An information processing apparatus which circulates a packet in one way among a plurality of modules connected in a ring shape, and transmits/receives the packet, each of the plurality of modules comprising a determination unit to determine whether data contained in the packet is processing-data to be processed by a processing-module of the module or configuration data for changing settings of the processing-module by an internally contained command, a discrimination unit to discriminate, when the data is determined to be the configuration data, a command type indicating the type of command contained within the configuration data as a write-mode in which the configuration data is written in the module, a read-mode in which currently set configuration data held in the module is read out, or an exchange-mode in which the currently set configuration data is read out, and then the configuration data is written, a decision unit to decide a packet transmission interval based on the command type.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: August 19, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hirowo Inoue, Hisashi Ishikawa
  • Patent number: 8804751
    Abstract: An epoch-based network processor internally segments packets for processing and aggregation in epoch payloads. FIFO buffers interact with a memory management unit to efficiently manage the segmentation and aggregation process.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: August 12, 2014
    Assignee: Force10 Networks, Inc.
    Inventors: Glenn Poole, Brad Danofsky, David Haddad, Ann Gui, Heeloo Chung, Joanna Lin
  • Patent number: 8792512
    Abstract: A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, to maintain a message buffer entry in the sender comprising the sent packets, to track acknowledgment from the receiver that sent packets have been received; to maintain a timer indicating the time since message data has been sent, and to resend packets not acknowledged upon the timer reaching a timeout state. The receiving processor node is operable to send acknowledgement to the sender that received packets have been received, to track packets using a received message table to track which packets comprising part of the message have been received and whether all packets in the message have been received, and to process packets once all packets in a message are received to reassemble the received message.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: July 29, 2014
    Assignee: Intel Corporation
    Inventors: Steven L. Scott, Dennis C. Abts, Robert Alverson, Edwin Froese
  • Patent number: 8793336
    Abstract: Information content is managed in a network-based communication system by providing a first web-based interface accessible to a first user, the first web-based interface being configured to permit the first user to designate at least one data source that is external to the first web-based interface, maintaining persistent information content on behalf of the first user including content obtained from the data source designated by the first user, and generating a second web-based interface different than the first web-based interface, wherein access to at least a portion of the persistent information content is provided to each of one or more additional users via the second web-based interface in a manner controlled by the first user via the first web-based interface to thereby facilitate interaction between the first and additional users. The first and second web-based interfaces may comprise respective content management and mobile web sites.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: July 29, 2014
    Assignee: Wireless Ink Corporation
    Inventors: David Walker Harper, Jason James Sabella, William Henry Munch
  • Patent number: 8792514
    Abstract: A packet switching system includes a plurality of switch fabrics connected in cascade and a plurality of buffers respectively connected to the plurality of switch fabrics. In the event of packet competition, the plurality of switch fabrics buffer the competing packets to the corresponding buffers through buffer connection ports, and forward the competing packets in excess of the number of buffer connection ports to an adjacent switch fabric through switch connection ports.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: July 29, 2014
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: June Koo Rhee, Chan-Kyun Lee
  • Patent number: 8789065
    Abstract: Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation.
    Type: Grant
    Filed: November 23, 2012
    Date of Patent: July 22, 2014
    Assignee: Throughputer, Inc.
    Inventor: Mark Henrik Sandstrom
  • Publication number: 20140198803
    Abstract: A memory bus connected module for scheduling services for network packet processing is disclosed. The module can include a memory bus connection, a scheduling circuit configured to reorder network packets received from the memory bus connection and place the reordered network packets into multiple input/output queues, and multiple offload processors connected to the memory bus connection, each offload processor configured to modify network packets in the multiple input/output queues.
    Type: Application
    Filed: June 22, 2013
    Publication date: July 17, 2014
    Inventors: Parin Bhadrik Dalal, Stephen Paul Belair
  • Patent number: 8774203
    Abstract: A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, and to send a message complete packet after all packets in the message are sent. The message complete packet includes an indicator of the number of packets in the message, and the message is recognized as complete in the receiver once the number of packets indicated in the message complete packet have been received for the message. The sender tracks acknowledgment from the receiver of receipt of the sent packets; and notifies the receiver when it has received all packets comprising a part of the message.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: July 8, 2014
    Assignee: Intel Corporation
    Inventors: Steven L. Scott, Dennis C. Abts, Robert Alverson, Edwin Froese
  • Patent number: 8767722
    Abstract: A switching network includes an upper tier having a master switch and a lower tier including a plurality of lower tier entities. The master switch, which has a plurality of ports each coupled to a respective lower tier entity, implements on each of the ports a plurality of virtual ports each corresponding to a respective one of a plurality of remote physical interfaces (RPIs) at the lower tier entity coupled to that port. Data traffic communicated between the master switch and RPIs is queued within virtual ports that correspond to the RPIs with which the data traffic is communicated. The master switch applies data handling to the data traffic in accordance with a control policy based at least upon the virtual port in which the data traffic is queued, such that the master switch applies different policies to data traffic queued to two virtual ports on the same port of the master switch.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Keshav Kamble, Amitabha Biswas, Dar-Ren Leu, Chandarani J. Mendon, Nilanjan Mukherjee, Vijoy Pandey
  • Patent number: 8750323
    Abstract: A method and structure for switching data is provided. An output port scheduler obtains state information of VOQs and available state information of input port data channels and output port buffers. The output port scheduler sends scheduling request information to a FIC of an input port whose input port data channel is ready in input ports corresponding to non-empty VOQs pointing to an output port. After receiving the scheduling request information sent by the output port schedulers, the FIC of the selected input port selects to respond to a scheduling request of one output port scheduler, and sends the VOQ pointing to the output port in the selected input port to the output port buffer. The output port scheduler schedules the VOQ received by the output port buffer out of a switch chip. Buffer resources are saved and the switching performance is improved.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: June 10, 2014
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Wumao Chen, Dajun Zang
  • Publication number: 20140140352
    Abstract: A relay device relays between two TCP communication items of a LAN side and a WAN side. When a line bandwidth of the WAN side is smaller than a line bandwidth of the LAN side, buffer overflow in a LAN side reception buffer and a WAN side transmission buffer of the relay device is prevented, and a connection is prevented from being forced to be canceled. A value of a reception window size (rwnd) described in an ACK packet returned to a transmission terminal of the LAN side is controlled based on a transmission throughput, a discarding rate, and an RTT measured in TCP communication of the WAN side, and a total size of unarranged data and a size of arranged data in a reception buffer of the LAN side and a size of untransmitted data and ACK awaiting data in a transmission buffer of the WAN side.
    Type: Application
    Filed: March 1, 2012
    Publication date: May 22, 2014
    Applicant: HITACHI, LTD.
    Inventor: Takashi Isobe
  • Patent number: 8730982
    Abstract: A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data and at least one egress module for transmitting the incoming data to at least one egress port. The at least one egress module includes an egress scheduling module and multiple queues per each of the at least one egress port. Each of the multiple queues serve data attributable to a class of service, and the egress scheduling module is configured to service a minimum bandwidth requirement for each of the multiple queues and then to service the multiple queues to allow for transmission of a maximum allowable bandwidth through a weighting of each of the multiple queues.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: May 20, 2014
    Assignee: Broadcom Corporation
    Inventors: Chien-Hsien Wu, Bruce Kwan, Philip Chen
  • Patent number: 8718054
    Abstract: A bridge routing module can be incorporated into a closed network fabric, such as a vehicular network. The bridge routing module includes an interface circuit to be coupled to other elements of the closed network fabric, for example other bridge routing modules or switch modules. The bridge routing module includes memory to store information associating packet content types with packet routing parameters, among other things. A processing module included in the bridge routing module analyzes packets to identify the type of content carried by the packets, and determines packet routing parameters based on the packet's content type. Ingress and egress of the packet are controlled in accordance with the packet routing parameters determined by the processing module.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: May 6, 2014
    Assignee: Broadcom Corporation
    Inventors: Nariman Yousefi, Yongbum Kim, John Walley, Sherman (Xuemin) Chen, Wael W. Diab, Nicholas Ilyadis
  • Patent number: 8718077
    Abstract: A network switch including a plurality of ports; a memory, and a queue controller. The queue controller is configured to: maintain a list of pointers to a first plurality of buffers in the memory; of the first plurality of buffers, selectively allocate a first buffer to a first port of the plurality of ports; in response to i) the first port receiving a first frame of data, ii) the first buffer being allocated to the first port, and iii) the first frame being stored in the memory, remove the pointer to the first buffer from the list of pointers; transfer, to an output queue associated with a second port of the plurality of ports, the pointer to the first buffer; and in response to the first frame of data being sent from the second port, add the pointer to the first buffer back to the list of pointers.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: May 6, 2014
    Assignee: Marvell International Ltd.
    Inventors: Hugh Walsh, Donald Pannell
  • Patent number: 8711867
    Abstract: A method includes receiving flits forwarded from an upstream router into a first input virtual channel (VC) associated with an input port. The flits are associated with packets originated from a first Intellectual Property (IP) core and forwarded to a second IP core. The flits are stored in a VC storage associated with the first input VC. The method further includes performing link width conversion based on a width of the flits being different from a width of an output port. Link width conversion includes accumulation of the flits when the width of the output port is wider and unpacking of the flits when the width of the output port is narrower. Credits are generated based on the flits being forwarded from the first input VC to the output port. The credits are sent to the upstream router to enable receiving more flits from the upstream router.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: April 29, 2014
    Assignee: Sonics, Inc.
    Inventors: Liping Guo, Doddaballapur N. Jayasimha, Jeremy Chan
  • Patent number: 8706903
    Abstract: An audio-on-demand communication system provides real-time playback of audio data transferred via telephone lines or other communication links. One or more audio servers include memory banks which store compressed audio data. At the request of a user at a subscriber PC, an audio server transmits the compressed audio data over the communication link to the subscriber PC. The subscriber PC receives and decompresses the transmitted audio data in less than real-time using only the processing power of the CPU within the subscriber PC. According to one aspect of the present invention, high quality audio data compressed according to lossless compression techniques is transmitted together with normal quality audio data. According to another aspect of the present invention, metadata, or extra data, such as text, captions, still images, etc., is transmitted with audio data and is simultaneously displayed with corresponding audio data.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: April 22, 2014
    Assignee: Intel Corporation
    Inventors: Robert D. Glaser, Mark O'Brien, Thomas B. Boutell, Randy Glen Goldberg
  • Publication number: 20140105220
    Abstract: A method and apparatus for processing message is described. In one embodiment, an application programming interface is configured for receiving and sending messages. A multiplexer receives messages from different servers. A service name is coupled to each message with the corresponding destination service. A single shared channel is formed. The messages are processed over the single shared channel.
    Type: Application
    Filed: December 17, 2013
    Publication date: April 17, 2014
    Applicant: Red Hat Inc.
    Inventors: Bela Ban, Vladimir Blagojevic
  • Patent number: 8693490
    Abstract: Disclosed are methods, systems, paradigms and structures for processing data packets in a communication network by a multi-core network processor. The network processor includes a plurality of multi-threaded core processors and special purpose processors for processing the data packets atomically, and in parallel. An ingress module of the network processor stores the incoming data packets in the memory and adds them to an input queue. The network processor processes a data packet by performing a set of network operations on the data packet in a single thread of a core processor. The special purpose processors perform a subset of the set of network operations on the data packet atomically. An egress module retrieves the processed data packets from a plurality of output queues based on a quality of service (QoS) associated with the output queues, and forwards the data packets towards their destination addresses.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: April 8, 2014
    Assignee: Unbound Networks, Inc.
    Inventors: Damon Finney, Ashok Mathur
  • Patent number: 8681796
    Abstract: A method and apparatus for switching a data packet between a source and destination in a network. The data packet includes a header portion and a data portion. The header portion includes routing information for the data packet. The method includes defining a data path in the router comprising a path through the router along which the data portion of the data packet travels and defining a control path comprising a path through the router along which routing information from the header portion travels. The method includes separating the data path and control path in the router such that the routing information can be separated from the data portion allowing for the separate processing of each in the router. The data portion can be stored in a global memory while routing decisions are made on the routing information in the control path.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: March 25, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Pradeep S. Sindhu, Kireeti Kompella, Dennis C. Ferguson, Bjorn O. Liencres, Nalini Agarwal, Hann-Hwan Ju, Raymond Marcelino Manese Lim, Rasoul Mirzazadeh Oskouy, Sreeram Veeragandham
  • Patent number: 8675486
    Abstract: An approach for providing flow control in a radio communication system is disclosed. A request from a non-satellite system specific side of a transport interface is made to a system specific side of the transport interface for a flow control allocation that specifies an amount of data to be stored in a queue of the system specific side of the transport interface. The system specific side supports a signaling function that is based on a transmission characteristic of the radio communication system. The flow control allocation is generated based upon availability of the queue, wherein the destination address is a link layer address of the satellite communication system. This arrangement has particular applicability to a satellite network (e.g., Very Small Aperture Terminal (VSAT) network) that provides data communication services.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: March 18, 2014
    Assignee: Hughes Network Systems, LLC
    Inventors: Daniel Friedman, Robert Torres, Patrick Stevens, Craig Schweinhart, Mangala Kannan, Deepak Arur, Peter Lin, Matthew Butehorn, Ken Burrell
  • Patent number: 8671138
    Abstract: A network interface adapter includes a network interface and a client interface, for coupling to a client device so as to receive from the client device work requests to send messages over the network using a plurality of transport service instances. Message processing circuitry, coupled between the network interface and the client interface, includes an execution unit, which generates the messages in response to the work requests and passes the messages to the network interface to be sent over the network. A memory stores records of the messages that have been generated by the execution unit in respective lists according to the transport service instances with which the messages are associated. A completion unit receives the records from the memory and, responsive thereto, reports to the client device upon completion of the messages.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: March 11, 2014
    Assignee: Mellanox Technologies Ltd.
    Inventors: Michael Kagan, Diego Crupnicoff, Gilad Shainer, Ariel Shahar
  • Patent number: 8670454
    Abstract: Embodiments of a system that includes a switch and a buffer-management technique for storing signals in the system are described. In this system, data cells are dynamically assigned from a host buffer to at least a subset of switch-ingress buffers in the switch based at least in part on the occupancy of the switch-ingress buffers. This buffer-management technique may reduce the number of switch-ingress buffers relative to the number of input and output ports to the switch, which in turn may overcome the limitations posed by the amount of memory available on chips, thereby facilitating large switches.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: March 11, 2014
    Assignee: Oracle America, Inc.
    Inventors: Wladyslaw Olesinski, Hans Eberle, Nils Gura
  • Patent number: 8665739
    Abstract: In general, techniques are described for measuring packet data unit (PDU) loss in a L2 virtual private network (L2VPN) service, such as a VPLS instance. In one example of the techniques, provider edge (PE) routers that participate in the L2VPN measure known unicast and multicast PDU traffic at the service endpoints for the instance to determine unicast PDU loss within the service provider network. As the routers learn the outbound service (i.e., core-facing) interfaces and outbound local (i.e., customer-facing) interfaces for L2 addresses of customer devices that issue packets to the VPLS instance, the routers establish respective unicast transmit and receipt counters for the service endpoints that serve the customer devices. In another example, PE routers that participate in the L2VPN measure multicast PDU traffic at the service endpoints for the instance and account for internal replication by intermediate service nodes to determine multicast PDU loss within the service.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: March 4, 2014
    Assignee: Juniper Networks, Inc.
    Inventors: Prabakaran Thirumali Sampath, Sri Goli
  • Patent number: 8665719
    Abstract: The present invention provides switches and routers, preferably with fully-connected mesh fabrics, that transmit data through the switch fabric in variable-size data units. Variable-size data units allow switches and routers to provide throughputs close to hardware capabilities, eliminating the need for over-capacity hardware in the switch fabric and other components. Along with variably-size data units, preferred embodiments of this invention include scheduling methods that provide fair allocation of pre-determined bandwidths to different protocols, to different classes of service within protocols, and to different resources within the switch by use of certain weighted, fair scheduling methods. The switches and routers of this invention are particularly directed to multi-protocol, high-throughput communication applications, but may have wide applicability in systems generally where data packets are switched or routed.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: March 4, 2014
    Assignee: Alcatel Lucent
    Inventors: Nabil N. Bitar, Philip To, Thomas A. Hoch
  • Patent number: 8665894
    Abstract: A mechanism for combining plurality of point-to-point data channels to provide a high-bandwidth data channel having an aggregated bandwidth equivalent to the sum of the bandwidths of the data channels used is provided. A mechanism for scattering segments of incoming data packets, called data chunks, among available point-to-point data channel interfaces is further provided. A decision as to the data channel interface over which to send a data chunk to can be made by examining a fullness status of a FIFO coupled to each interface. An identifier of a data channel on which to expect a subsequent data chunk can be provided in a control word associated with a present chunk of data. Using such information in control words, a receive-end interface can reassemble packets by looking to the control word in a currently processing data chunk to find a subsequent data chunk.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: March 4, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Yiren R. Huang, Raymond Kloth
  • Publication number: 20140050224
    Abstract: In one embodiment, the present invention includes a method for determining whether a packet received in an input/output (I/O) circuit of a node is destined for the node and if so, providing the packet to an egress queue of the I/O circuit and determining whether one or more packets are present in an ingress queue of the I/O circuit and if so, providing a selected packet to a first or second output register according to a global schedule that is independent of traffic flow. Other embodiments are described and claimed.
    Type: Application
    Filed: October 25, 2013
    Publication date: February 20, 2014
    Inventors: Michael Kauschke, Gautam B. Doshi
  • Patent number: 8649389
    Abstract: Transmitting from a mobile terminal to a telecommunication network data stored in a plurality of queues, each queue having a respective transmission priority, includes setting the data in each of the queues to be either primary data or secondary data, or a combination of primary data and secondary data. The data may be transmitted from the queues in an order in dependence upon the priority of the queue and whether the data in that queue are primary data or secondary data. Resources for data transmission may be allocated such that the primary data of each of the queues are transmitted at a minimum predetermined rate and such that the secondary data of each of the queues are transmitted at a maximum predetermined rate, greater than the minimum predetermined rate.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: February 11, 2014
    Assignee: Vodafone Group Services Limited
    Inventors: David Fox, Alessandro Goia
  • Patent number: 8638799
    Abstract: A system and method for implementing a VM to identify a data packet for transmission, the data packet including a QoS the data packet is to receive as compared to another QoS that another data packet is to receive. The system and method further includes a SNIC to pull the data packet from the VM based upon the QoS the data packet is to receive. The system and method may also include a link scheduler module to transmit the data packet based upon the QoS the data packet is to receive. The system and method may also include a receiver to receive a management instruction from a network management device, the management instruction to dictate the QoS the data packet is to receive based upon a SLA.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: January 28, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jayaram Mudigonda, Paul T Congdon, Partha Ranganathan
  • Patent number: 8630304
    Abstract: A switch includes a reserved pool of buffers in a shared memory. The reserved pool of buffers is reserved for exclusive use by an egress port. The switch includes pool select logic which selects a free buffer from the reserved pool for storing data received from an ingress port to be forwarded to the egress port. The shared memory also includes a shared pool of buffers. The shared pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the shared pool upon detecting no free buffer in the reserved pool. The shared memory may also include a multicast pool of buffers. The multicast pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the multicast pool upon detecting an IP Multicast data packet received from an ingress port.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: January 14, 2014
    Assignee: MOSAID Technologies Incorporated
    Inventor: David A. Brown
  • Patent number: 8625623
    Abstract: A method and system for allocating exchange identifications (IDs) in a fiber channel switch for fiber channel aggregation. The method included determining a number (m) of N_ports present in a back end of the switch, and distributing available exchange IDs across the number (m) of present N_ports. Each exchange ID includes (j) bits and (n) bits are used to identify each of the present backend ports, where m?2n.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: January 7, 2014
    Assignee: Broadcom Corporation
    Inventors: Bhavi Saklecha, Kean P. Hurley, Alfonso Y. Ip
  • Patent number: 8625427
    Abstract: One embodiment of the present invention provides a system that facilitates flow control of multi-path-switched data frames. During operation the system transmits from an ingress edge device data frames destined to an egress edge device across different switched paths based on queue status of a core switching device and queue status of the egress edge device. The egress edge device is separate from the core switching device.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: January 7, 2014
    Assignee: Brocade Communications Systems, Inc.
    Inventors: John M. Terry, Joseph Juh-En Cheng, Jan Bialkowski
  • Patent number: 8619800
    Abstract: Disclosed are methods, systems, paradigms and structures for processing data packets in a communication network by a multi-core network processor. The network processor includes a plurality of multi-threaded core processors and special purpose processors for processing the data packets atomically, and in parallel. An ingress module of the network processor stores the incoming data packets in the memory and adds them to an input queue. The network processor processes a data packet by performing a set of network operations on the data packet in a single thread of a core processor. The special purpose processors perform a subset of the set of network operations on the data packet atomically. An egress module retrieves the processed data packets from a plurality of output queues based on a quality of service (QoS) associated with the output queues, and forwards the data packets towards their destination addresses.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: December 31, 2013
    Assignee: Unbound Networks
    Inventors: Damon Finney, Ashok Mathur
  • Patent number: 8594082
    Abstract: A switching network includes an upper tier and a lower tier including a plurality of lower tier entities. A master switch in the upper tier, which has a plurality of ports each coupled to a respective lower tier entity, implements on each of the ports a plurality of virtual ports each corresponding to a respective one of a plurality of remote physical interfaces (RPIs) at the lower tier entity coupled to that port. Data traffic communicated between the master switch and RPIs is queued within virtual ports that correspond to the RPIs on lower tier entities with which the data traffic is communicated. The master switch enforces priority-based flow control (PFC) on data traffic of a given virtual port by transmitting, to a lower tier entity on which a corresponding RPI resides, a PFC data frame specifying priorities for at least two different classes of data traffic communicated by the particular RPI.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Keshav Kamble, Dayavanti G. Kamath, Jayakrishna Kidambi, Dar-Ren Leu, Chandarani J. Mendon, Vijoy Pandey
  • Patent number: 8593960
    Abstract: In one embodiment, the present invention includes a method for determining whether a packet received in an input/output (I/O) circuit of a node is destined for the node and if so, providing the packet to an egress queue of the I/O circuit and determining whether one or more packets are present in an ingress queue of the I/O circuit and if so, providing a selected packet to a first or second output register according to a global schedule that is independent of traffic flow. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: November 26, 2013
    Assignee: Intel Corporation
    Inventors: Michael Kauschke, Gautam B. Doshi
  • Patent number: 8588243
    Abstract: A queue scheduling method and apparatus is disclosed in the embodiments of the present invention, the method comprises: one or more queues are indexed by using a first circulation link list; one or more queues are accessed respectively by using the front pointer of the first circulation link list, and the value acquired from subtracting a value of a unit to be scheduled at the head of the queue from a weight middle value of each queue is treated as the residual weight middle value of the queue; when the weight middle value of one queue in the first circulation link list is less than the unit to be scheduled at the head of the queue, the queue is deleted from the first circulation link list and the weight middle value is updated with the sum of a set weight value and the residual weight middle value of the queue; the queue deleted from the first circulation link list is linked with a second circulation link list.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: November 19, 2013
    Assignee: ZTE Corporation
    Inventors: Yi Yang, Wei Huang, Mingshi Sun
  • Patent number: 8588244
    Abstract: An Ethernet switch has at least one ingress/egress port which is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaces each of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit modules which receive GE and FE packets from, and transmit GE and FE packets to, the interfaces.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: November 19, 2013
    Assignee: Lantiq Deutschland GmbH
    Inventors: Shridhar Mubaraq Mishra, Tina Zhang, Chunfeng Hu, Hak Keong Sim
  • Patent number: 8588224
    Abstract: A switching network includes an upper tier and a lower tier including a plurality of lower tier entities. A master switch in the upper tier, which has a plurality of ports each coupled to a respective lower tier entity, implements on each of the ports a plurality of virtual ports each corresponding to a respective one of a plurality of remote physical interfaces (RPIs) at the lower tier entity coupled to that port. Data traffic communicated between the master switch and RPIs is queued within virtual ports that correspond to the RPIs on lower tier entities with which the data traffic is communicated. The master switch enforces priority-based flow control (PFC) on data traffic of a given virtual port by transmitting, to a lower tier entity on which a corresponding RPI resides, a PFC data frame specifying priorities for at least two different classes of data traffic communicated by the particular RPI.
    Type: Grant
    Filed: May 14, 2011
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Keshav Kamble, Dayavanti G. Kamath, Jayakrishna Kidambi, Dar-Ren Leu, Chandarani J. Mendon, Vijoy Pandey
  • Patent number: 8576862
    Abstract: Described embodiments provide for arbitrating between nodes of scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. The traffic manager queues the received task in an associated queue of the scheduling hierarchy. The root scheduler performs smooth deficit weighted round robin (SDWRR) arbitration between each child node of the root scheduler. The SDWRR arbitration includes checking one or more status indicators of each child node of the given scheduler and selecting, based on the status indicators, a first active child node of the scheduler and updating the one or more status indicators corresponding to the selected child node. Thus, a task is scheduled for transmission by the traffic manager every cycle of the network processor.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: November 5, 2013
    Assignee: LSI Corporation
    Inventors: David Sonnier, Balakrishnan Sundararaman, Shashank Nemawarkar
  • Patent number: 8576863
    Abstract: A system determines a scheduling value based on a current length of a downstream queue in a network device. The system sends the scheduling value from the downstream queue to an upstream queue and schedules dequeuing of one or more data units, destined for the downstream queue, from the upstream queue based on the scheduling value.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: November 5, 2013
    Assignee: Juniper Networks, Inc.
    Inventors: Qingming Ma, Jiaxiang Su
  • Patent number: 8571051
    Abstract: A method of preparing data streams to facilitate seamless switching between such streams by a switching device to produce an output data stream without any switching artifacts. Bi-directional switching between any plurality of data streams is supported. The data streams are divided into segments, wherein the segments include synchronized starting points and end points. The data rate is increased before an end point of a segment, to create switch gaps between the segments. Increasing the data rate can include increasing a bandwidth of the plurality of data streams, for example by multiplexing, or compressing the data. The present invention can be used, for example, with MPEG or AC-3 encoded audio and MPEG encoded video segments that are multiplexed into MPEG-2 transport streams. Also included are specific methods for preparing MPEG video streams and multiplexing MPEG video with MPEG or AC-3 audio streams to allow a receiver to create seamless transitions between individually encoded segments.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: October 29, 2013
    Assignee: Visible World Inc.
    Inventors: Seth Haberman, Alex Jansen, Gerrit Niemeijer, Richard L. Booth
  • Patent number: 8571049
    Abstract: A device may include a first line card and a second line card. The first line card may include a memory including queues. In addition, the first line card may include a processor. The processor may identify, among the queues, a queue whose size is to be modified, change the size of the identified queue, receive a packet, insert a header cell associated with the packet in the identified queue, identify a second line card from which the packet is to be sent to another device in a network, remove the header cell from the identified queue, and forward the header cell to the second line card. The second line card may receive the header cell from the first line card, and send the packet to the other device in the network.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: October 29, 2013
    Assignee: Verizon Patent and Licensing, Inc.
    Inventors: Dante J. Pacella, Norman Richard Solis, Harold Jason Schiller
  • Patent number: 8559439
    Abstract: A method and apparatus for queue-ordering commands in multi-engines, multi-queues and/or multi-flows environment is provided. Commands from single/multiple queues and multi-flows are processed by multi-engines with different processing time and/or out of order, which breaks sequential order of commands from same input queue and commands are distributed across multiple engines' output buffer after processing. Processed commands are stored in dedicated command output buffer associated with each engine temporarily. The processed commands are re-ordered while writing out. Also commands can be scheduled to idle engines to achieve maximum throughput, thus utilizing the engines in an optimal manner.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: October 15, 2013
    Assignee: PMC-Sierra US, Inc.
    Inventors: Anil B. Dongare, Kuan Hua Tan
  • Publication number: 20130266021
    Abstract: The invention provides a method for adding specific hardware on both receive and transmit sides that will hide to the software most of the effort related to buffer and pointers management. At initialization, a set of pointers and buffers is provided by software, in quantity large enough to support expected traffic. A Send Queue Replenisher (SQR) and Receive Queue Replenisher (RQR) hide RQ and SQ management to software. RQR and SQR fully monitor pointers queues and perform recirculation of pointers from transmit side to receive side.
    Type: Application
    Filed: December 19, 2011
    Publication date: October 10, 2013
    Inventors: Claude Basso, Jean L. Calvignac, Chih-jen Chang, Damon Philippe, Michel L. Poret, Natarajan Vaidhyanathan, Fabrice J. Verplanken, Colin B. Verrilli
  • Patent number: 8553691
    Abstract: Embodiments of the invention are directed to multicasting packets in a system such as a data packet switch or router having a distributed architecture. A first device such as a line card receiving a packet that requires multicasting forwards the packet to a fabric switch where the packet is replicated to obtain one respective packet for each line card of the system. Each line card receives its respective packet from the fabric switch and further duplicates the packet to obtain a duplicate packet for each egress endpoint of a service associated with the packet that is eligible to receive such a duplicate packet. Replication and duplication of packets requiring multicasting performed in this manner efficiently uses bandwidth of the fabric switch and links connecting it to the line cards.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: October 8, 2013
    Assignee: Alcatel Lucent
    Inventors: Erel Ortacdag, Nirmesh Patel