Abstract: A network device receives a label-switched-path (LSP) labeled data packet, maps the LSP labeled data packet to an input queue, maps a data packet in the input queue to an output queue based on a received LSP label value and a received exp label value, and transmits the LSP labeled data packet from the output queue.

Abstract: A system for optimizing response time to events or representations thereof waiting in a queue has a first server having access to the queue; a software application running on the first server; and a second server accessible from the first server, the second server containing rules governing the optimization. In a preferred embodiment, the software application at least periodically accesses the queue and parses certain ones of events or tokens in the queue and compares the parsed results against rules accessed from the second server in order to determine a measure of disposal time for each parsed event wherein if the determined measure is sufficiently low for one or more of the parsed events, those one or more events are modified to a reflect a higher priority state than originally assigned enabling faster treatment of those events resulting in relief from those events to the queue system load.

Abstract: Data units received by a network device may be classified into traffic flow classes in which the determined traffic flow class for a data unit may be dynamically refined as the data unit is processed by the network device. A dispatch component of the network device may receive data units associated with traffic flow classes. Parallel processing engines of the network device may receive the data units from the dispatch component and may generate, for a least one of the data units, a plurality of dynamically refined indications of the traffic flow class to which the data unit belongs. Additionally, an ordering component of the network device may include a plurality of re-order queues, where the at least one data unit successively progresses through at least two of the re-order queues in an order defined by the plurality of dynamically refined indications of the traffic flow class.

Abstract: The invention relates to a switching node comprising a dynamic address table in a data network, in addition to a method for creating a dynamic address table of this type for a switching node. The method comprises the following steps: receipt of a first data message with a source address at a port of the switching node; entry of the source address, details of the port and a counter initial value in a line of the address table that is assigned to the source address as the target address, whereby the current counter value indicates the validity of the entry and the current counter value is modified, if a second data message with the source address as the target address is received and the entry is valid.

Abstract: A messaging service is described that incorporates messages into cached link lists. The messages are not yet acknowledged as having been received by one or more consumers to whom the messages were sent. A separate link list exists for each of a plurality of different message priority levels. Messages within a same link list are ordered in their link list in the same order in which they where received by the messaging service. At least one of the link lists contains an element that represents one or more messages that are persisted but are not cached in any of the cached link lists.

Abstract: A communication system that includes a packet switch having a buffered crossbar for routing data packets from input ports to output ports of the packet switch. The buffered crossbar stores a data packet received from an input port based on a clock signal of a clock domain and sends the data packet to an output port of the packet switch based on a clock signal of another clock domain. In this way, the buffered crossbar functions as a clock domain boundary between the input port and the output port. Moreover, the frequency of one or both of the clock signals may be selected to minimize power consumption in the packet switch or to select a tradeoff between power consumption and performance of the packet switch.

Abstract: Information content is managed in a network-based communication system by providing a content management site accessible to a user of the system. The content management site is configured to permit the user to designate at least one data source that is external to the content management web site. A mobile web site is generated that is accessible independently of the content management web site via one or more mobile devices over a wireless network of the communication system, with the mobile web site being configured to receive data automatically from the external data source designated by the user at the content management web site.

Abstract: A method and system for allocating exchange identifications (IDs) in a fibre channel switch for fibre channel aggregation. The method included determining a number (m) of N_ports present in a back end of the switch, and distributing available exchange IDs across the number (m) of present N_ports. Each exchange ID includes (j) bits and (n) bits are used to identify each of the present backend ports, where m?2n.

Abstract: Method and system for network communication between a first network port and at least a second network port is provided. The method includes establishing bi-directional communication between the first network port and the second network port using a first set of port setting information. After establishing bi-directional communication, a second set of port setting information is sent from the first network port to the second network port. If a response to the second set of port setting information is not received from the second network port within a given duration or if an unacceptable response is received from the second network port, then the first set of port setting information is used for communication between the first and second network ports.

Abstract: Communication traffic isolation and control systems and methods are disclosed. Communication traffic streams are received and either passed or filtered by respective controllable filtering modules. The operation of the filtering modules is controlled on a per-module and thus a per-stream basis, responsive to congestion of filtered communication traffic streams at a communication traffic processing element to which the filtering modules are connected. Per-stream filtering provides traffic control for each communication traffic stream, and maintains isolation between the streams. Statistics associated with communication traffic filtered out of each stream may be collected, and possibly aggregated.

Abstract: A network device receives a label-switched-path (LSP) labeled data packet, maps the LSP labeled data packet to an input queue, maps a data packet in the input queue to an output queue based on a received LSP label value and a received exp label value, and transmits the LSP labeled data packet from the output queue.

Abstract: A multiprocessor computer system includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each node controller, a first input/output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input/output port, a network port, and a plurality of independent processor ports. A first and a second processor port is connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. The memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips.

Abstract: A resending control circuit for controlling resending of data to be sent to a sending destination, includes: a writing unit for writing resending information generated corresponding to each of data to be resent and including the resending point-in-time of the data in memory; a reading unit for reading out the resending information from the memory; and a control unit for comparing resending point-in-time included in the oldest resending information of resending information stored in the memory with current point-in-time, and executing resending processing of data corresponding to the resending information according to the comparison result.

Abstract: A technique for improved throughput at an access point (AP) involves when frames are received for transmission by the AP, queuing the frames for a particular station. A system constructed according to the technique may include an aggregation and queuing layer. Station queues may be processed by the aggregation and queuing layer before being given to radio hardware for transmission. In an illustrative embodiment, when frames are received by the aggregation and queuing layer, the packet will be assigned a target delivery time (TDT) and an acceptable delivery time (ADT). The TDT is the “ideal” time to transmit a frame, based on its jitter and throughput requirements. Frames are mapped on to a time axis for transmission by TDT. In an illustrative embodiment, each frame is mapped by priority, so that there are separate maps for voice, video, best effort, and background frames. There will be gaps between frames for transmission that can be used for aggregation.

Abstract: A method and apparatus to perform buffer management for media processing are described.

Abstract: Modules and methods are described for buffering packets to be switched in a system, such as a programmed device. The modules can be configured for different packet lengths, protocols, applications, and/or designs in a larger system. Techniques and mechanisms are further described for implementing a central memory and a linked-list addressing scheme. Accordingly, memory blocks of the central memory can be used for variable length packets and further reused at substantially the same time as they become available, thereby improving packet switching efficiency and/or flexibility.

Abstract: Practical packet reassembly in large, multi-plane, multi-stage switches is possible by using a scheduling technique called dynamic packet interleaving. With dynamic packet interleaving scheduling, if more than one packet is contending for the same output link in a switch module, an arbiter in the switch module gives priority to a partial packet (i.e., to a packet that has had at least one cell sent to the queue). The number of reassembly queues required to ensure reassembly is dramatically reduced (e.g., to the number of paths multiplied by the number of scheduling priorities). Deadlock may be avoided by guaranteeing (e.g., reserving) at least one cell space for all partial packets.

Abstract: A system and method for routing packets from one node to another node in a system having a plurality of nodes connected by a network. A node router is provided in each node, wherein the node router includes a plurality of network ports, including a first and a second network port, wherein each network port includes a communications channel for communicating with one of the other network nodes, a plurality of virtual channel input buffers and a plurality of virtual channel staging buffers, wherein each of the virtual channel staging buffers receives data from one of the plurality of input buffers.

Abstract: Techniques are given for determining the data transmission or sending rates in a router or switch of two or more input queues in one or more input ports sharing an output port, which may optionally include an output queue. The output port receives desired or requested data from each input queue sharing the output port. The output port analyzes this data and sends feedback to each input port so that, if needed, the input port can adjust its transmission or sending rate.

Abstract: A system for processing packets is disclosed and may including a network interface card (NIC). The NIC may include a TCP enabled Ethernet controller (TEEC). The TEEC may include an internal elastic buffer. The TEEC may process received incoming TCP packets once and may temporarily buffer at least a portion of the incoming TCP packets in the internal elastic buffer. The processing may occur without reassembly or retransmission. The internal elastic buffer may include a receive internal elastic buffer and a transmit internal elastic buffer. The receive internal elastic buffer may temporarily buffer at least a portion of the received incoming TCP packets. The transmit internal elastic buffer may temporarily buffer at least a portion of TCP packets to be transmitted. The TEEC may place at least a portion of the received incoming TCP packets data into at least a portion of a host memory.

Abstract: According to an embodiment, a method includes a Delay Tolerant Network (DTN) software overlay residing in a first plane of a node of the network is used to define hierarchical forwarding behavior for data being generated in the first plane. In a second plane of the network, local buffering and data retransmission is performed in response to at least one intermittent network outage. Communication between the first and second planes is performed to manage the transmission of data between the first and second planes as needed in the event of at network outage that is longer in duration than the at least one intermittent network outage, to thus prevent the loss of data.

Abstract: In one embodiment, the present invention includes a method for receiving a first packet associated with a first network flow in a first descriptor queue associated with a first hardware thread, receiving a marker in the first descriptor queue to indicate migration of the first network flow from the first hardware thread to a second hardware thread, and processing a second packet of the first network flow following the first packet in order in the second hardware thread.

Abstract: Described embodiments provide for transfer of data between data modules. At least two crossbar switches are employed, where input nodes and output nodes of each crossbar switch are coupled to corresponding data modules. The ith crossbar switch has an Ni-input by Mi-output switch fabric, wherein Ni and Mi are positive integers greater than one. Each crossbar switch includes an input buffer at each input node, a crosspoint buffer at each crosspoint of the switch fabric, and an output buffer at each output node. The input buffer has an arbiter that reads data packets from the input buffer according to a first scheduling algorithm. An arbiter reads data packets from a crosspoint buffer queue according to a second scheduling algorithm. The output node receives segments of data packets provided from one or more corresponding crosspoint buffers.

Abstract: A packet switch includes a pointer table for mapping locations in an input data buffer to locations in an output data buffer. The processor generates an output data packet based on data portions in the input data buffer and based on the pointer table. The output data buffer stores data portions of the output data packet successively in a sequential order and can output the data portions of the output data packet successively in a sequential order. The pointer table may be configured to reduce the latency or reduce the power consumption of the packet switch.

Abstract: A multi-port serial buffer having a plurality of queues is configured to include a first set of queues assigned to store write data associated with a first port, and a second set of queues assigned to store write data associated with a second port. The available queues are user-assignable to either the first set or the second set. Write operations to the first set of queues can be performed in parallel with write operations to the second programmable set of queues. In addition, a first predetermined set of queues is assigned to the first port for read operations, and a second predetermined set of queues is assigned to the second port for read operations. Data can be read from the first predetermined set of queues to the first port at the same time that data is read from the second predetermined set of queues to the second port.

Abstract: An improved packet handler for VoIP cable modems and other high-speed digital devices includes a direct communication link via hardware among internal processing components. Incoming and outgoing digital information packets are filtered into MAC packets, voice PDU packets, and non-voice PDU packets, such that priority can be given to relaying voice packets and minimizing potential voice delay within the cable network. Hardware components, including specialized logic circuitry, modify voice packets to an appropriate signal form for subsequent signal processing or signal transmission. Proprietary bus communication protocols can also be provided to facilitate relay of packets between a central processing unit (CPU) and a digital signal processor (DSP) within a VoIP cable modem. Line cards including subscriber line interface circuit (SLIC) and subscriber line audio processing circuit (SLAC) components provide analog-to-digital (A/D) and digital-to-analog (D/A) conversion functionality.

Abstract: A network data monitoring device provides for the flexible, programmable port-to-multi-port steering of data packet traffic between network port pairs, with tap data streams being directed to any of a plurality of monitor ports. The network data monitoring device is constructed utilizing one or more switching integrated circuits programmed to disable layer-2 routing and impose port-to-multiport data packet steering. Physical layer protocol encoding/decoding circuits enable connectivity to physical network media connectors though a system of fail-safe relays. A system controller, preferably implemented by a microprocessor, is connected to all switching integrated circuits and relays for configuration, status and control. Hardware-based logic selectively in complement to the switching integrated circuits provides for the programmable filtering, modification and programmable steering of data packets through the device.

Abstract: To use the memory space more effectively, cell memory can be shared by an input link and all output links. To prevent one flow from occupying the entire memory space, a threshold may be provided for the queue. The queue threshold may accommodate the RTT delay of the link. Queue length information about a downstream switch module may be sent to an upstream switch module via cell headers in every credit update period per link. Cell and/or credit loss may be recovered from. Increasing the credit update period reduces the cell header bandwidth but doesn't degrade performance significantly. Sending a credit per link simplifies implementation and eliminates interference between other links.

Abstract: There is provided a gateway apparatus that controls a forwarding process of frame data between multiple communication channels, said gateway apparatus including a search engine that is respectively provided for each of the multiple communication channels to route the frame data between the multiple communication channels, and a first storage portion that is respectively provided for each of the multiple communication channels to temporarily stores the frame data routed.

Abstract: Variable length switch fabric for switching variable length data packets between input and output transmission paths in a communication network. In one embodiment of the invention, apparatus is provided for switching variable length data packets between input and output transmission paths in a communication network. The apparatus includes a plurality of input ports coupled to receive the plurality of variable length data packets from the input transmission paths and a plurality of output ports coupled to transmit the plurality of variable length data packets on the output transmission paths. The apparatus also includes a variable length switch fabric coupled to the plurality of input ports and the plurality of output ports, the variable length switch fabric operates to switch the plurality of variable length data packets from selected input ports to selected output ports in an unsegmented form.

Abstract: An integrated egress/replay memory structure is provided with split rate write and read ports and means for managing at least three types of data moving into, through and/or out of the integrated memory structure, namely: (1) currently egressing packet data; (2) replay data; and (3) to-be egressed data. Additionally, a shared free space (4) is managed between the storage areas of the (2) replay data and (3) the to-be egressed data. The to-be egressed data (PdBx) is allowed to enter into (to be written into) a front-end raceway portion of the integrated memory structure at a rate which can be substantially greater than that allowed for corresponding egressing packet data (PdUx). Thus, even when egressing packet data that is ahead in line is shifting out toward a slow rate egress port, this slowing factor does not slow the speed at which the to-be egressed data (PdBx) can be shifted into the front-end raceway portion.

Abstract: Method of managing priority during the transmission of a message, in an interconnections network comprising at least one transmission agent which comprises at least one input and at least one output, each input comprising a means of storage organized as a queue of messages. A message priority is assigned during the creation of the message, and a queue priority equal to the maximum of the priorities of the messages of the queue is assigned to at least one queue of messages of an input. A link priority is assigned to a link linking an output of a first transmission agent to an input of a second transmission agent, equal to the maximum of the priorities of the queues of messages of the inputs of said first agent comprising a first message destined for that output of said first agent which is coupled to said link, and the priority of the link is transmitted to that input of said second agent which is coupled to the link.

Abstract: A method for sending a frame of data from a first channel to a second channel comprises reserving q of n available buffers of m total buffers to the first channel. A frame that is received from the first channel in i of the q buffers is stored and the status is changed to unavailable. The frame is selectively assigned to the second channel based on a number of the buffers j assigned to the second channel and a number of the buffers h neither reserved nor assigned to any channel, wherein i+j?m and h+q?n. The i buffers storing the frame are assigned to the second channel if the frame is assigned to the second channel. The status of the i buffers is changed to available if the frame is subsequently sent over the second channel.

Abstract: An arbiter performs arbitration over a plurality of queues and provides data to a plurality of mutually exclusive destinations using combination logic that logically combines a plurality of mutually exclusive vectors into a combination vector. Each of the mutually exclusive vectors corresponds to one of the plurality of mutually exclusive destinations. A number of vector arbiters perform arbitration on each mutually exclusive vector to select a position within the mutually exclusive vector. A combination arbiter performs arbitration on the combination vector to determine a position within the combination vector, which corresponds to the next queue to be serviced. A comparison element compares the position within a mutually exclusive vector and the position within the combination vector to determine the destination of the data within the next queue to be serviced.

Abstract: A network processor that has multiple processing elements, each supporting multiple simultaneous program threads with access to shared resources in an interface. Packet data is received from high-speed ports in segments and each segment is assigned to one of the program threads. Each packet may be assigned to a single program thread, two program threads—one for header segment processing and the other for handling payload segment(s)—or a different program thread for segment of data in a packet. Dedicated inputs for ready status and sequence numbers provide assistance needed for receiving the packet data over a high speed port. The dedicated inputs are used to monitor ready flags from the high speed ports on a cycle-by-cycle basis. The sequence numbers are used by the assigned threads to maintain ordering of segments within a packet, as well as to order the writes of the complete packets to transmit queues.

Abstract: In particular embodiments of the present invention, a method for filtering packets in a switching environment is provided. In particular embodiments, the method includes receiving a packet at an input port of a switch, the switch comprising a memory and one or more output ports. The method also includes storing at least a portion of the packet in the memory and determining one or more output ports from which the packet is to be communicated from the switch. The method further includes, after beginning to determine one or more output ports from which the packet is to be communicated from the switch, determining whether the packet is an illegal packet. The method also includes, if the packet is an illegal packet, dropping the packet from the memory, and if the packet is a legal packet, communicating the packet from the determined one or more output ports.

Abstract: A packet switching network system for use in transferring information that is in the form of packets and including an originating device and a destination device for communicating therebetween through a packet switching network, the originating device including a sending device having a first buffer with a predetermined first buffer size, the first buffer being used to store information that is to be sent to the destination unit, the sending device for sending a request packet including the first buffer size, through the packet switching network, to the destination device, the destination device including a receiving device having a second buffer with a predetermined second buffer size, the second buffer size being used for storing information that is received from the originating device, the receiving device for receiving a request packet including the first buffer size from the originating device, determining whether or not the received first buffer size is supported by the destination device, and according

Abstract: Reducing pool starvation in a switch is disclosed. The switch includes a plurality of egress ports, and a reserved pool of buffers in a shared memory. The reserved pool of buffers is one of a number of reserved pools of buffers, and the reserved pool of buffers is reserved for one of the egress ports. A shared pool of buffers and a multicast pool of buffers are in the shared memory. The shared pool of buffers is shared by the egress ports.

Abstract: A system and method of switching packets and/or cells, which includes a switching apparatus having a plurality of input units that receive at least one packet to be transferred by the switching apparatus. A plurality of output units transfer the packet out of the switching apparatus. A switch unit transfers the packet from one of the input units to one of the output units. Each input unit includes at least one input queue that temporarily holds the packet to be transferred by the switching apparatus. Each input unit also includes a respective unicast credit count unit that allows the packet to be transferred out from the queue when a current unicast credit value determined by the unicast credit count unit is at least predetermined value. Each output unit includes at least one output queue that receives the packet as switched by the switch unit, and which is to be transferred out of the switching apparatus.

Abstract: A method includes storing video data in a disk by way of a first queue comprising a linked list of buffers. Video data are received into the first queue by way of a tail buffer. The tail buffer is at one end of the linked list of buffers in the first queue. Video data are copied from a head buffer to the disk. The head buffer is at another end of the linked list of buffers in the first queue. The video data are displayed in real-time directly from the buffers in the queue, without retrieving the displayed video data from the disk, and without interrupting the storing step.

Abstract: A method for transferring data includes connecting N ports of a crossbar to N devices, respectively, where N is an integer greater than one. Inbound data is received at one of the N ports from a respective one of the N devices. N?1 output buffers are associated with others of the N ports, respectively. At least one of the N?1 output buffers is selected to output outbound data corresponding to the inbound data. The inbound data from the input buffer of one of the N ports is selectively transferred to at least one of the N?1 output buffers of the others of the N ports.

Abstract: A prime number based pointer allocation technique. A packet-forwarding system incorporating the technique stores cells of a packet in packet memory, according to allocated pointers that have a fixed correspondence to locations in the packet memory. Each packet input interface of an ingress module has a memory parameter counter that is incremented by a different prime number each time a memory pointer is allocated to that input interface. The memory parameter counter includes a memory interface portion and a memory bank portion that correspond to the memory interfaces and memory banks of a packet memory with which the memory pointers are associated.

Abstract: An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e.g., flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, “un-escaping” the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.

Abstract: The present invention is a technique to select an input port. A database stores records of input ports for a plurality of communication channels. Each of the records includes a timestamp and a ready status. The timestamp indicates a most recent service time. A selector selects one of the input ports based on the timestamp and the ready status. A listener updates the records.

Abstract: Transactions are received through at least two input channels, each transaction comprising one or more data packets. The data packets are placed in a single data queue. When a first transaction received through one input channel comprises more than one data packet, a data packet of a second transaction received through another input channel is permitted to be placed in the single data queue between data packets of the first transaction. A block of space in a data output queue is assigned to each transaction. Each data packet is placed in the block assigned to its transaction.

Abstract: The interconnecting network for switching data packets, having data and flow control information, comprises a local packet switch element (S1) with local input buffers (I(1,1) . . . I(1,y)) for buffering the incoming data packets, a remote packet switch element (S2) with remote input buffers (I(2,1) . . . I(2,y)) for buffering the incoming data packets, and data lines (L) for interconnecting the local and the remote packet switch elements (S1, S2). The interconnecting network further comprises a local and a remote arbiter (A1, A2) which are connected via control lines (CL) to the input buffers (I(1,1) . . . I(1,y), I(2,1) . . . I(2,y)), and which are formed such that they can provide that the flow control information is transmitted via the data lines (L) and the control lines (CL).

Abstract: A method for managing data traffic in nodes in a fabric network, each node having internally-coupled ports, follows the steps of establishing a managed queuing system comprising one or more queues associated with each port, for managing incoming data traffic; and accepting or discarding data directed to a queue according to the quantity of data in the queue relative to queue capacity. In one preferred embodiment the managed system accepts all data directed to a queue less than full, and discards all data directed to a queue that is full. In some alternative embodiments the queue manager monitors quantity of data in a queue relative to queue capacity, and begins to discard data at a predetermined rate when the quantity of queued data reaches the threshold. In other cases the queue manager increases the rate of discarding as the quantity of queued data increases above the preset threshold, discarding all data traffic when the queue is full.

Abstract: A matrixed memory array device is disclosed that includes input ports and output ports. Each input port is coupled to a first data bus and each output port is coupled to a second data bus that is different and separate from the first data bus. A memory brick is placed at each cross-point between first data buses and second data buses so as to switchably couple frames of data from input ports to output ports. Each memory brick contains a plurality of eight transistor (8-T) memory cells that can be used to store, erase, read, write, and switchably couple a data bit from the input port to a corresponding output port.

Abstract: In one embodiment of the present invention, a system for memory interleaving in a high-speed switching environment includes multiple memory units that each include one or more memory devices. The system also includes multiple port modules. Each port module can receive a packet communicated from a component of a communications network, write the received packet to one or more of the memory units, and read a packet from one or more of the memory units for communication to the component of the communications network. The system also includes an interconnection network including a hierarchical structure that includes one or more switching stages.

Abstract: A low latency peripheral device sharing system has a host computer with an operating system, a kernel memory buffer, applications, device specific drivers, and a peripheral server driver. The server driver intercepts function calls invoking the local serial ports, and passes standard serial data from the application to a local area network. A device server on the local area network reads the data using a hybrid read block (semi-blocking read), and writes the data to the FIFO registers of the serial device and the remaining data to a queue for the serial device. Finally, the device server times the serial data and returns an intercharacter interval timer flag to the host computer to terminate a read operation.