Abstract: The present invention provides a preemptive priority scheduling system and method for optimal load balancing of messages and preserving the lightweight allocation resources in an intersystem communication. The invention also provides a system and method for scheduling of messages of a plurality of classes in an intersystem communication.

Abstract: A method may include receiving a packet in a network device, selecting one of a group of ingress buffers, where each ingress buffer is associated with a different one of a group of processors, distributing the packet to the selected ingress buffer; and scheduling the packet, based on a congestion state of a queue in an egress buffer associated with the packet, to be processed by the processor associated with the selected ingress buffer to provide a network service.

Abstract: A method of transforming an ordered list of nodes of a network into one of a plurality of elite ordered lists, the ordered list corresponding to a deloading sequence, the deloading sequence including a temporary capacity requirement, each of the elite ordered lists corresponding to an elite deloading sequence including an elite temporary capacity requirement by generating at least one intermediate ordered list corresponding to an intermediate deloading sequence including an intermediate temporary capacity requirement, selecting one of the intermediate ordered list and the ordered list based on a comparison of the intermediate temporary capacity requirement and the temporary capacity requirement and replacing one of the elite ordered lists with the one of the intermediate ordered list and the ordered list if a value corresponding to one of the intermediate temporary capacity requirement and the temporary capacity requirement is less than a lowest value of the elite temporary capacity requirements.

Abstract: A computer implemented method, computer product code, and data processing system are provided for transferring data between virtual partitions. A request is received to transfer a packet from a first partition to a second partition. A free buffer is identified from a buffer pool of the second partition, and a receive descriptor is written. A bit within the receive descriptor is set to identify a receive descriptor ring of second partition. A first interrupt is generated to the second partition. The packet is then copied to the free buffer, and the receive descriptor is updated.

Abstract: A method and system for reducing arbitration latency employs speculative transmission (STX) without prior arbitration in combination with routing fabric scheduled arbitration. Packets are sent from source locations to a routing fabric through scheduled arbitration, and also through speculative arbitration, to non-contentiously allocate outputs that were not previously reserved in the routing fabric to the speculatively transmitted packets.

Abstract: Information content is managed in a network-based communication system by providing a first web site accessible to a user of the system. The first web site is configured to permit the user to designate at least one data source. A second web site is generated that is accessible independently of the first web site via one or more mobile devices over a wireless network of the communication system, with the second web site being configured to receive data automatically from the data source designated by the user at the first web site. The first and second web sites may comprise respective content management and mobile web sites, or other types of web-based interfaces. Other aspects of the invention relate to permitting a first user to designate a plurality of other users that will share access to content with the first user via the second web site, in accordance with accessibility rules established by the first user via the first web site.

Abstract: An audio-on-demand communication system provides real-time playback of audio data transferred via telephone lines or other communication links. One or more audio servers include memory banks which store compressed audio data. At the request of a user at a subscriber PC, an audio server transmits the compressed audio data over the communication link to the subscriber PC. The subscriber PC receives and decompresses the transmitted audio data in less than real-time using only the processing power of the CPU within the subscriber PC. According to one aspect of the present invention, high quality audio data compressed according to lossless compression techniques is transmitted together with normal quality audio data. According to another aspect of the present invention, metadata, or extra data, such as text, captions, still images, etc., is transmitted with audio data and is simultaneously displayed with corresponding audio data.

Abstract: A method and apparatus for performing connection control in a wireless communication system is described. In one embodiment, an apparatus is used in a wireless communication system for communicating with a wireless network, and the apparatus comprises a host processor, a transceiver, a physical interface coupling the host processor and the transceiver; and a memory accessible by the host processor and the transceiver to exchange information between the host processor and the transceiver. The memory has multiple banks that include: a first bank to store information being transferred from the host processor to the transceiver, and a second bank to store information being transferred from the transceiver to the host processor, the second bank being different than the first bank, to facilitate full-duplex communication of packet data between the host processor and the transceiver.

Abstract: A method of providing switch arbitration for the passing of packets between transmitters and receivers in a switch having a plurality of transmitters and receivers, comprises globally distributing information about buffer contents and packet requests between transmitters and receivers.

Abstract: This is a computer-readable portable storage medium which is used by a computer managing a plurality of frame buffers and which stores a program enabling the computer to execute a process, and the process comprises preparing an area in which data of a valid chain indicating a connection among frame buffers storing valid image data of the plurality of frame buffers and data of a vacant chain indicating a connection among frame buffers storing no valid image data, is stored, on memory and generating/updating data of the valid chain and the vacant chain when valid image data is stored in one of the plurality of frame buffers and storing it in the memory.

Abstract: A prohibition turn determination apparatus determines an initial path so that the communication amounts of respective links connecting switches to each other are most efficiently distributed between a communication pair, that is, a pair of servers communicating with each other via a network. Then, the prohibition turn determination apparatus calculates the communication amounts of respective turns formed along the initial path based on the communication amounts set between end nodes which are the communication pair. Next, the prohibition turn determination apparatus determines prohibition turns, which are not used for packet communication, based on the communication amounts of respective turns by an Up/down method or a TP method. Finally, the prohibition turn determination apparatus determines the final routing to avoid the prohibition turns.

Abstract: A serial buffer having a parser and multiple parallel processing paths is provided. The parser receives incoming packets, determines the type of each packet, and then routes each packet to a processing path that corresponds with the determined packet type. Packet types may include blocking priority packets (which implement bus slave operations), non-blocking priority packets (which access on-chip resources of the serial buffer) and data packets (which implement bus master operations). Because the different packet types are processed on parallel processing paths, the processing of one packet type does not interfere with the processing of other packet types. As a result, blocking conditions within the serial buffer are minimized.

Abstract: A mobile communication device has a wireless transceiver and one or more processors for communicating data in a wireless communication system. The one or more processors are operative to receive a plurality of data packets of varying payload size in a queue; associate one or more of the data packets from the queue into a group, such that a total size of the group is at or near a maximum transmissible unit (MTU) size of a data frame; cause the one or more data packets associated into the group to be formatted into the data frame for data transmission via the wireless transceiver; and repeat, for a plurality of data frames, the associating and formatting, for communicating the data via the wireless transceiver in the wireless communication system. By associating the data packets into groups having the MTU size, data throughput of the data transmission is increased.

Abstract: The communication control apparatus 100 of the present invention carries out complementary communication by selecting plural wireless communication paths 10A, 10B between a wireless communication apparatus 300 and itself.

Abstract: A packet switch includes virtual output queues for mapping data units of data packets from input ports to output ports of the packet switch. The packet switch selects virtual output queues based on old age indicators of the virtual output queues and routes data units mapped at heads of the selected virtual output queues to output ports of the packet switch. Further, the packet switch may identify a data unit of a multicast data packet mapped at the head of more than one virtual output queue and contemporaneously route the data unit to more than one output port. Additionally, the packet switch may update an old age indicator to indicate a virtual output queue is old if the virtual output queue maps an unserviceable data unit of a multicast data packet and the same data unit is mapped at the head of a selected virtual output queue.

Abstract: An embodiment of the present invention reduces certain memory bandwidth requirements when sending a multicast message from a network device such as a router, bridge or switch. Separate output buffers are provided for different groups of egress ports, and incoming messages are written to some or all of the output buffers. A processing determination is made as to which egress ports will forward the message. Buffers associated with non-forwarding ports are released and the message is queued at the forwarding egress ports. When the message is forwarded, data is read from the output buffers associated with the forwarding egress ports.

Abstract: A system for processing data packets in a data packet network has at least one input port for receiving data packets, at least one output port for sending out data packets, a processor for processing packet data, and a packet predictor for predicting a future packet based on a received packet, such that at least some processing for the predicted packet may be accomplished before the predicted packet actually arrives at the system. The system is used in preferred embodiments in Internet routers.

Abstract: Sending priority of plural stages is statically assigned according to a quality class and an output connection, and the sending priority is dynamically changed according to a state of sending request stacking every sending priority and a state of ATM cell conversion processing of a frame, and ATM cell conversion request means for issuing an ATM cell conversion request is provided every output route, and the cell conversion processing of the frame is selected and performed in the order of higher sending priority every time one cell conversion.

Abstract: Methods, systems, and computer program products for controlling enqueuing of packets in an aggregated queue including a plurality of virtual queues are disclosed. According to one method, packets are received at the input side of a queuing system. Each packet is classified into a virtual queue corresponding to one of a plurality of output queues. The output queue sends backpressure messages to the enqueue controller. The enqueue controller determines whether to place the packets in the aggregated queue based on the backpressure messages.

Abstract: A method and apparatus for queue concatenation have been disclosed.

Abstract: An Ethernet switch has at least one ingress/egress port 1 which is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaces 3 each of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit modules 5, 7 which receive GE and FE packets from, and transmit GE and FE packets to, the interfaces. If there are 8 such ports in the Ethernet switch, then by switching different numbers of the ports between the two modes, the switch may operate in 9 different modes: as 8 GE ports, 7 GE ports and 8 FE ports, 2 GE ports and 48 FE ports, 1 GE port and 56 FE ports, or simply as 64 FE ports.

Abstract: An apparatus and method for UpLink (UL) radio resource allocation in a wideband wireless communication system are provided. In a method of operating a Relay Station (RS) for UpLink (UL) radio resource allocation in a wideband wireless communication system, the method includes relaying to a Base Station (BS) a resource request message of at least one or more Mobile Stations (MSs); receiving data from the at least one or more mobile stations; if the received data is non-real time traffic, queuing the data received from the mobile stations according to a traffic type; and requesting the base station to allocate necessary radio resources by checking a queue status. Accordingly, a delay can be reduced when the UL resource is allocated to an relay station for real time traffic.

Abstract: A method for debugging network connections that involves receiving a packet for a first destination by a network interface card (NIC), classifying the packet, sending the packet to a first receive ring associated with the NIC, and sending the packet from the first receive ring to a first virtual NIC, where the first virtual NIC is associated with a second destination, and where the second destination is used to debug the first destination.

Abstract: A switching device comprising a plurality of ingress ports and a plurality of egress ports. The switching device is arranged to receive data packets through the ingress ports and to forward received data packets to respective ones of the egress ports. The switching device further comprises an ingress module for each of the ingress ports, each ingress module being arranged to receive data packets from a respective single one of the ingress ports and to store the received data packets in one of a plurality of data structures provided by the ingress module, each ingress module being further configured to select a data packet from one of the plurality of data structures, and to request permission to transmit the selected data packet to an egress port.

Abstract: The embodiments balance wireless communication bandwidth capacity in a channel one or more cascading wireless communication links in a wireless communication cell, and manage the wireless communication bandwidth capacity in the channel across two or more virtual cells within the wireless communication cell.

Abstract: A method and system schedule data for dequeuing in a communication network. The communication network includes an eligible scheduling node, a scheduling context structure, and an existence of data structure. In response to determining that an eligible scheduling node does not contain at least one child identifier in the scheduling context structure, an eligible child is selected for dequeue from the existence of data structure. At least one eligible child from the existence of data structure is absorbed into the scheduling context structure. The at least one eligible child includes the child selected for dequeue. Absorbing a child includes removing the child identifier from the existence of data queue and adding the child identifier to the scheduling context structure.

Abstract: Systems and methods consistent with the present invention provide a mechanism that can efficiently manage multiple queues and maintain fairness among ports while not placing additional performance demands on the memory used to store the queue data structures. Within a port, high priority traffic is dropped only if it is consuming more than its fair share of bandwidth allocated to that port. Queue arbitration is of low performance cost and simple because it arbitrates only across queues per port, rather than across all the queues in parallel. Accordingly, fair arbitration with relatively little hardware cost.

Abstract: Systems and methods are described that provide network traffic engineering that obviate network over-provisioning by providing QoS to each traffic class. Embodiments dimension switching router LTE schedulers to ensure that each traffic class receives an appropriate QoS in terms of delay, jitter, Packet Loss Ratio and throughput. In addition to guaranteeing QoS, embodiments optimize transport cost, optimize switch-router port deployment, and work on top of IETF standards, IEEE standards, and MEF standards.

Abstract: Described herein is a method and system for directing outgoing data packets from packet engines to a transmit queue of a NIC in a multi-core system, and a method and system for directing incoming data packets from a receive queue of the NIC to the packet engines. Packet engines store outgoing traffic in logical transmit queues in the packet engines. An interface module obtains the outgoing traffic and stores it in a transmit queue of the NIC, after which the NIC transmits the traffic from the multi-core system over a network. The NIC receives incoming traffic and stores it in a NIC receive queue. The interface module obtains the incoming traffic and applies a hash to a tuple of each obtained data packet. The interface module then stores each data packet in the logical receive queue of a packet engine on the core identified by the result of the hash.

Abstract: A network interface adapter includes a network interface and a client interface, for coupling to a client device so as to receive from the client device work requests to send messages over the network using a plurality of transport service instances. Message processing circuitry, coupled between the network interface and the client interface, includes an execution unit, which generates the messages in response to the work requests and passes the messages to the network interface to be sent over the network. A memory stores records of the messages that have been generated by the execution unit in respective lists according to the transport service instances with which the messages are associated. A completion unit receives the records from the memory and, responsive thereto, reports to the client device upon completion of the messages.

Abstract: A method for sending a frame of data from a first channel to a second channel comprises reserving q of n available buffers of m total buffers to the first channel. A frame that is received from the first channel in i of the q buffers is stored and the status is changed to unavailable. The frame is selectively assigned to the second channel based on a number of the buffers j assigned to the second channel and a number of the buffers h neither reserved nor assigned to any channel, wherein i+j?m and h+q?n. The i buffers storing the frame are assigned to the second channel if the frame is assigned to the second channel. The status of the i buffers is changed to available if the frame is subsequently sent over the second channel.

Abstract: A method for transferring data includes connecting N ports of a crossbar to N devices, respectively, where N is an integer greater than one. Inbound data is received at one of the N ports from a respective one of the N devices. Dedicated connections are provided between an input buffer of one of the N ports and N?1 output buffers associated with others of the N ports, respectively. At least one of the N?1 output buffers of the others of the N ports is selected to output outbound data corresponding to the inbound data. The inbound data from the input buffer of one of the N ports is selectively transferred to at least one of the N?1 output buffers of the others of the N ports.

Abstract: An apparatus for communicating with a network comprises a queue and logic. The queue has at least one entry stored therein. The at least one entry respectively points to at least one data packet. The logic is configured to read the at least one entry from the queue and to retrieve the at least one data packet based on the at least one entry. The logic is configured to transition to a sleep state based on a determination that a new entry for reading, by the logic, from the queue is unavailable for a specified amount of time.

Abstract: Methods and devices are provided for implementing flow control coordination in a gateway between a TCP/IP network and a second network. The second network may be any type of network, including another TCP/IP network. In some implementations, the throughput of the TCP/IP network is controlled by modifying the round trip time observed by a TCP connection. In other implementations, the throughput of the TCP/IP network is controlled by modifying the size of the TCP window.

Abstract: A switch includes a reserved pool of buffers in a shared memory. The reserved pool of buffers is reserved for exclusive use by an egress port. The switch includes pool select logic which selects a free buffer from the reserved pool for storing data received from an ingress port to be forwarded to the egress port. The shared memory also includes a shared pool of buffers. The shared pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the shared pool upon detecting no free buffer in the reserved pool. The shared memory may also include a multicast pool of buffers. The multicast pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the multicast pool upon detecting an IP Multicast data packet received from an ingress port.

Abstract: Embodiments of the invention provide systems, devices and methods to schedule data transport across a fabric, e.g., prior to actual transmission of the data across the fabric. In some demonstrative embodiments, a packet switch may include an input controller to schedule transport of at least one data packet to an output controller over a fabric based on permission information received from the output controller. Other embodiments are described and claimed.

Abstract: Packets or cells of variable lengths arriving at a multitude of input ports of a crossbar switch are stored in the input buffers associated with the input ports. Each input buffer includes a number of banks defined by a ratio of a preselected size to the smallest packet size. Each bank is configured to store a packet having the smallest size. The packets so stored in the buffers are subsequently transferred and stored in a memory shared by all the input and output buffers. The packets are stored along the depth of the shared memory, therefore, during each packet transmission period, a portion of each one of the packets is transferred and stored in the same addressable storage location of the share memory. Each portion includes one or more bits carried by the packet.

Abstract: A device and method for processing information fragments, the method includes: receiving multiple information fragments from multiple communication paths; wherein the each information fragment is associated with a cyclic serial number indicating of a generation time of the information fragment; storing the multiple information fragments in multiple input queues, each input queue being associated with a communication path out of the multiple communication paths; determining whether at least one serial number associated with at least one valid information fragment positioned in a head of one of the multiple input queues is located within a pre-rollout serial number range; mapping, in response to the determination, serial numbers associated with each of the valid information fragment positioned in the heads of the multiple input queues to at least one serial number range that differs from the pre-rollout serial number range; and sending to an output queue information fragment metadata associated with a minimal v

Abstract: A hierarchical pipelined distributed scheduling traffic manager includes multiple hierarchical levels to perform hierarchical winner selection and propagation in a pipeline including selecting and propagating winner queues of a lower level to subsequent levels to determine one final winning queue. The winner selection and propagation is performed in parallel between the levels to reduce the time required in selecting the final winning queue. In some embodiments, the hierarchical traffic manager is separated into multiple separate sliced hierarchical traffic managers to distributively process the traffic.

Abstract: A scheduling apparatus for a switch includes multiple schedulers which are assigned in a variety of ways to non-intersecting control domains for establishing connections through the switch. The control domains are defined by spatial and temporal aspects. The control domains may be dynamically selected and assigned to schedulers in a manner that achieves a high throughput gain. Control domains may be considered in a cyclic and/or a pipeline discipline for accommodating connection requests. The invention enables the realization of a highly scalable controller of a switching node of fine granularity that scales to capacities of the order of hundreds of terabits per second.

Abstract: A method is described to operate a crossbar switch comprising a crossbar fabric with N sending and M receiving ports, with port cards connected to at least one sending and/or receiving port each of the crossbar fabric, said crossbar switch further comprising a control unit connected with the port cards via discrete control channel links, wherein C ports are clustered on a single receiving port card so that such a receiving port card in a single time-step can receive up to C data cells from C sending port cards simultaneously. According to said method the control channel links are used to relay up to C acknowledgements between at least one receiving port card and at least one sending port card.

Abstract: A frame transmitting apparatus transmits a frame to a frame receiving apparatus. The frame transmitting apparatus includes the following units. An accumulated-capacity-value storage unit has stored therein an accumulated capacity value calculated. A cycle and capacity storage unit has stored therein a cycle and frame read capacity at every cycle. An adding unit adds the value indicative of the capacity of the frame to the accumulated capacity value. A subtracting unit subtracts the value indicative of the frame read capacity from the accumulated capacity value. A transmission controlling unit controls frame transmission by using the accumulated capacity value.

Abstract: A buffer circuit buffers incoming signals, from a local oscillator generator to a mixing circuit and has a push-pull circuit having two inputs, a first being coupled to a first incoming signal, and a second of the inputs being coupled to one of the buffered versions of the incoming signals, having a phase related to that of the first incoming signal. By coupling a second input to a buffered version rather than to the incoming signal, the load presented to the preceding circuit can be halved, while maintaining reduced power consumption. By using as a second input, a signal which is phase related to the first incoming signal, the normal operation of the push-pull circuit can be maintained. The incoming signals from the LO generator can be differential IQ signals and the buffered version of the further incoming signal be in phase with the first incoming signal.

Abstract: A circulating switch comprises switch modules of moderate capacities interconnected by a passive rotator. Data is sent from a one switch module to another switch module either directly, traversing the rotator once, or indirectly through at least one intermediate switch module where the rotator is traversed twice. A higher capacity extended circulating switch is constructed from higher-capacity switch modules, implemented as common memory switches and having multiple ports, interconnected through a multiplicity of rotators preferably arranged in complementary groups of rotators of opposite rotation directions. A polyphase circulating switch having a low switching delay is derived from a multi-rotator circulating switch by providing programmable rotators having adjustable relative rotator-cycle phases. A low delay high-capacity switch may also be constructed from prior-art medium-capacity rotator space switches with mutually phase-shifted rotation cycles.

Abstract: A router for a network is arranged for guiding data traffic from one of a first plurality Ni of inputs (I) to one or more of a second plurality No of outputs (O). The inputs each have a third plurality m of input queues for buffering data. The third plurality m is greater than 1, but less than the second plurality No. The router includes a first selection facility for writing data received at an input to a selected input queue of the input, and a second selection facility for providing data from an input queue to a selected output. Pairs of packets having different destinations Oj and Ok are arranged in the same queue for a total number of Nj,k inputs, characterized in that Nj,k<N for each j,k.

Abstract: An improved architecture for switches and a method for transmitting data with the switching are disclosed. An increased amount of memory is utilized, operating at speeds lower than are required by Input Queued switches, and a simple scheduling algorithm. The architecture divides the input ports into groups, where each input port group has an associated set of memory elements. Incoming packets are routed to the appropriate element in the set of memory elements. The number of groups and the number of ports that are included in each group can be varied, allowing the architecture to be modified based on the system architecture, the semiconductor technology, and other design considerations.

Abstract: A terminal adapter for guaranteeing the quality of service of both voice and data packets is disclosed. When a data packet is received in a first data input queue of a terminal adapter, a determination is made whether a voice packet is present in a voice input queue. Another determination is made as to whether the sum of the size of the data packet and the size of all packets in a terminal adapter output queue would exceed a first size threshold established for the output queue. If voice packets are present in the voice input queue, or if the aforementioned sum exceeds the size threshold, the data packet is not forwarded to the output queue. If no voice packets are present in the voice input queue and if the aforementioned sum is below the first size threshold, then the data packet is forwarded to the output queue.

Abstract: A method and system for allocating exchange identifications (IDs) in a fibre channel switch for fibre channel aggregation. The method included determining a number (m) of N_ports present in a back end of the switch, and distributing available exchange IDs across the number (m) of present N_ports. Each exchange ID includes (j) bits and (n) bits are used to identify each of the present backend ports, where m?2n.

Abstract: A system determines a scheduling value based on a current length of a downstream queue in a network device. The system sends the scheduling value from the downstream queue to an upstream queue and schedules dequeuing of one or more data units, destined for the downstream queue, from the upstream queue based on the scheduling value.

Abstract: Data received from a bursty interface is received on a burst-by-burst basis. Once a burst is received, it is stored in a processing queue. A complete burst is received so long a processing queue can accommodate a data burst. The complete data burst is directed to an output and used to create a complete data burst on said output. The output burst is dispatched so long as a receiving port is able to accept the output burst.