Abstract: A Trie-type associative memory is used for an analysis of binary strings situated at defined locations of data packets. An analysis tree is established, which comprises stages associated with the locations, and paths each arriving at an action attributed on the basis of the values of the binary strings read from a data packet. The tree is then transcribed into the Trie memory.

Abstract: In a method of fair queue servicing at a queuing point in a multi-service class packet switched network, incoming packets are received in buffers and outgoing packets are scheduled by a weighted fair queue scheduler. Real-time information of buffer usage along with the minimum bandwidth requirement is used to dynamically modify the weights of the weighted fair queue scheduler.

Abstract: A packet switch which can cyclically use ? scheduling process results to determine one of M output lines as a destination of a packet stored in each of N input buffer sections by ? scheduler sections independently performing scheduling processes is disclosed.

Abstract: A data switch is proposed of the type having virtual queue ingress routers interconnected with egress routers by way of a memoryless switching matrix controlled by a control unit which performs an arbitration process to schedule connections across the switch. This scheduling is performed to ensure that data cells which arrive at the ingress routers at unpredictable times are transmitted to the correct egress routers. Each ingress router further includes a queue for time division multiplex traffic, and at times when such traffic exists, the control unit overrides the arbitration process to allow the time division multiplex traffic to be transmitted through the switch.

Abstract: A multiport switching device includes an Internal Rules Checker (IRC) that determines forwarding addresses for packets received at the device. The determined forwarding addresses may include a new MAC destination address that is to substituted for the MAC destination address of the received packet. In one implementation, the new MAC destination address is transmitted from the IRC to the dequeuing logic by transmitting pairs of adjacent words through the switch output queues. In other implementations, the new MAC destination address is transmitted from the IRC to the dequeuing logic by transmitting an index field to the output queuing logic or by having the IRC write the new MAC destination address directly to memory.

Abstract: A Pipelined-based Maximal-sized Matching (PMM) scheduling approach for input-buffered switches relaxes the timing constraint for arbitration with a maximal matching scheme. In the PMM approach, arbitration may operate in a pipelined manner. Each subscheduler is allowed to take more than one time slot for its matching. Every time slot, one of them provides the matching result. The subscheduler can adopt a pre-existing efficient maximal matching algorithm such as iSLIP and DRRM. PMM maximizes the efficiency of the adopted arbitration scheme by allowing sufficient time for a number of iterations. PMM preserves 100% throughput under uniform traffic and fairness for best-effort traffic.

Abstract: A novel scalable-port non-blocking shared-memory output-buffered variable length queued data switching method and apparatus wherein successive data in each of a plurality of queues of data traffic is distributed to corresponding cells of each of successive memory channels in striped fashion across a shared memory space.

Abstract: A method and apparatus provides QoS shaping/provisioning scheme for a data communications switch, such as a DiffServ aware router or a 802.1Q aware bridge, in which distinct internal and outbound priority values are assigned to a packet based on flow properties associated with an inbound packet. The flow properties used to assign the internal and outbound priority values may include at least one value from a packet field that is not dedicated to defining QoS. The internal priority value provides a priority to the packet during processing in the switch. The outbound priority value is applied to the packet in lieu of the inbound priority value prior to transmitting the packet from the switch. The flow properties used to determine the internal and outbound priority values may include, for example, Layer 2, Layer 3, and Layer 4 information encoded in the packet.

Abstract: The system provides an IP network card that comprises a redundancy configuration register; an interface; and redundancy mapping logic. The redundancy configuration register stores card configuration data. The interface receives slot active signals from other cards. The redundancy mapping logic is communicatively coupled to the register and interface. The logic maps a packet to a slot having an active card based on the data in the register, an address in the packet, and received slot active signals.

Abstract: In a switching device, a method of communicating data packets from sending ports to destination ports includes storing in a first stage queue packet-related data from a sending port; determining from the packet-related data which destination ports are to receive the packet-related data in the first stage queue; storing in a second stage queue associated with each determined destination port the packet-related data from the first stage queue; and using the packet-related data in the second stage queue to complete the communication of the data packet from the sending port to each determined destination port. Apparatus for practicing the method comprises a first stage queue storing packet-related data from a sending port; and a second stage queue associated with each of a set of destination ports storing the packet-related data from the first stage queue.

Abstract: A packet switch device having a plurality of input buffers; a packet switch; a plurality of schedulers, having a pipeline scheduling process module wherein a plurality of time units corresponding to the number of output lines is spent in scheduled sending process of the fixed length packets from the input buffer, and wherein the scheduled sending process is executed in a number of processes, in parallel, the number of processes corresponding to the number of the input lines, having a sending status management module wherein sending status of the fixed length packets which constitute one frame is managed for each of the input lines, and provided corresponding to any of the output lines; and at least one result notification module for notifying the input buffer of result information from the scheduled sending process performed by each of the plurality of schedulers.

Abstract: In a switch provided on a network for transferring data, a switch unit includes a scheduler for setting a switch core and an input port unit includes a data allotting unit for allotting transfer data on a priority basis, buffers provided corresponding to the priorities for temporarily storing and outputting the allotted transfer data, a request aggregating unit for aggregating connection requests related to transfer data which are allotted on a priority basis, allotting the connection requests in accordance with the priorities which are taken into consideration in processing by the scheduler and outputting the obtained requests, and a data aggregating unit for aggregating transfer data output from the buffers and transmitting the aggregated data to the switch core.

Abstract: A system, method and article of manufacture are provided for storing an incoming datagram in a switch matrix of a switch fabric. The switch matrix has a pair of buffers with each buffer having a pair of portions. Data of a datagram is received and the buffer portions are sequentially filled with the data. Periodically, transfer of data is allowed from the buffers into the switch matrix. At each period where transfer of data is allowed in the sequence that the buffer portions were filled, the data in one of the buffer portions may be transferred into the switch matrix.

Abstract: A data reception unit for receiving a plurality of data streams over a data channel, the data streams being received as amounts of data and each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream, the data reception unit comprising: a data stream memory comprising a plurality of data stream storage areas, each for storing data from a respective one of a set of the data streams, and an escape buffer; a first storage information memory for holding first storage information for facilitating storage in the respective data stream storage area of data from the set of the data streams; and a data storage controller for, for each received amount of data, receiving the identity portion of the amount of data and performing a storage operation comprising: accessing the first storage information memory; and if the first storage information memory holds first storage information for the data stream identified by the identity portion, storing the

Abstract: The cell switching architecture of the present invention uses at least one earliest deadline first (EDF) queue for each of the output ports in a cell switch so that no two output ports have a common earliest-deadline-first queue. Cells are arranged in each EDF queue according to deadline, but each EDF queue only contains cells for a single destination output port. Each input port also has an input queue with an EDF queue for each of the output ports, and each EDF queue arranges the cells for a single output port. Many equivalent cells may be represented by a single EDF queue entry, enabling large buffer capacity to be supported by small EDF queues. The architecture provides a method for switching cells between a plurality of input ports and a plurality of output ports. Cells are accepted from input ports into a plurality of corresponding input queues. Cells are sorted into groups according to the destination output port such that each group includes cells destined for a single output port.

Abstract: Connection distributors are used to route packets corresponding to multiple streams of packets through a packet switching system. During each time slot, one packet is typically sent from each packet stream. During the configuration of a packet stream, a time slot and primary route is determined for the packet stream. The primary route is a route through the packet switch which is non-blocking with other packet streams during the assigned time slot. During a common frame, a packet of each packet stream is sent out of a line card or packet interface to be routed through the packet switch over the designated primary route. During subsequent frames, packets are sent over different routes through the network (until all routes are used and then the cycle repeats). These routes are selected based on a deterministic method so as to maintain the non-blocking characteristic of the primary route selection.

Abstract: Signaling messages are exchanged for a call between a calling party to a called party. A setup message for the call is exchanged through at least one gate controller. Network resources are reserved for the call based on the exchanged setup messages. An end-to-end message for the call is exchanged without the end-to-end message being routed through the at least one gate controller.

Abstract: A method, apparatus and computer program product are provided for implementing queue pair connection protection over an interconnect network, such as InfiniBand. A message packet is received for a queue pair (QP) and the QP is checked for an imminent connection failure. Responsive to identifying an imminent connection failure, a special message processing mode is established for the QP. After the special message processing mode is established, packets of the message are received without establishing a message queue entry and without storing packet data.

Abstract: The present invention reduces the number of multicast synchronization delays in a packet switch by determining the mix of packets pending at the input ports. When a sufficient number of multicast packets are ready for transferal, the packet switch preferably transmits a programmed number of multicast packets (or as many multicast packets that exist up to that programmed number). After transmitting these multicast packets, the packet switch resumes preferably transmitting unicast packets. Thus, the number of multicast synchronization delays is reduced over the prior art, the bandwidth utilization of the packet switch is correspondingly increased and the load due to multicast packets and unicast packet is balanced. One embodiment of the invention includes a timer that ensures that multicast packets are transmitted without undue delay.

Abstract: The invention includes a way to route multicast traffic through a switch or other device that uses input queuing. Basis vectors are associated with each virtual queue, which in a preferred embodiment are multicast virtual output queues (MVOQs). Each incoming flow is allocated to the MVOQ whose basis vector is closest to the destination vector of the incoming flow, creating queues whose contents are distinct from each other in terms of destination addresses of the flows in the respective queue. To optimize for traffic encountered basis vectors can be chosen using vector quantization methods. Basis vectors can be set statically or can be selected and updated dynamically, responsive to the traffic encountered or as set by an operator. The invention can reduce the number of virtual queues required for a given incremental improvement in performance or can improve performance for a given number of virtual queues.

Abstract: Disclosed is a packet switching apparatus in a data network including a plurality of ports for taking charge of an input/output of packet transmission/reception commands and data packets, a plurality of transmission/reception control sections for accessing information resources classified into groups in response to the packet transmission/reception commands, and storing the corresponding data packets in a packet memory or transmitting the corresponding data packets stored in the packet memory to the corresponding ports, a plurality of the information resources for storing in groups information required for packet switching, and providing the information stored therein to the transmission/reception control sections, and a plurality of information resource schedulers, connected to the respective information resources, for scheduling accesses of the transmission/reception control sections.

Abstract: An ATM cell buffer read control system prevents over-rate due to excessive use of an extra line capacity with guarantee of a minimum output rate in a WRR system. The ATM cell buffer read control system effectively uses a band by distributing an extra band with a ratio of number of ATM cell number per connection with guarantee of minimum output band per connection according to preliminarily set ratio of output ATM cell number per a given period. The ATM cell buffer read control system makes judgment whether the output band after distribution of the extra band falls within a reference output range.

Abstract: A method and distributed scheduler for use therewith has at least two clusters of source port modules, each tracking all queues associated with a respective input-node and relating to a respective subset of available input-nodes. Each source port module receives available output-nodes, and generates a weight for each queue therein. Each source port module generates at least one request relating to the highest weight serviceable queue. The respective requests of each source port module are accumulated, and for each cluster of source port modules, the request is chosen for which no two requests relate to the same input-node, and for each output-node, the chosen requests have highest weight. The highest weight request from all clusters is determined in respect of each output node receiving requests from one or more input nodes. A grant is sent to the input-node having the highest weight request.

Abstract: Several embodiments of a computer system are described which achieve separation of control and data paths during data transfer operations, thus allowing independent scalability of storage system performance factors (e.g., storage system iops and data transfer rate). In one embodiment, the computer system includes a data switch coupled between a host computer and one or more storage devices. A storage controller for managing the storage of data within the one or more storage devices is coupled to the switch. The switch includes a memory for storing data routing information generated by the controller, and uses the data routing information to route data directly between the host computer and the one or more storage devices such that the data does not pass through the storage controller. Within the computer system, information may be conveyed between the host computer, the switch, the one or more storage devices, and the storage controller according to a two party protocol such as the Fibre Channel protocol.

Abstract: Multi-level buffer system dynamically allocates storage for data units arriving at network gateway, and retrieves stored data units according to hierarchical schedule. Minimum and maximum thresholds associated with system resource and storage availability determine acceptance and storage of data units. Data units are accepted preferably if all threshold criteria are met. Threshold criteria may be determined from reserved minimum buffer length, calculated maximum buffer length, or random early discard-type algorithm applied separately to each buffer level. Optionally, buffer management applies to non-hierarchical storage systems.

Abstract: In candidate selection to select the queue issuing the connection request to a certain output port out of a plurality of logic queues provided in an input buffer section of an input buffer type ATM switching system to store cells for each output port and each connection, whether a logic queue holds cells in predetermined order is checked, and the logic queue located next to the queue to which gained the right to connect to an output port last time is taken as a start point of the rotation priority control to select the logic queue holding the cell searched first.

Abstract: The present invention provides a method and apparatus for arbitration among the inputs of a crossbar cell switch. The input cells of the crossbar cell switch are stored at their respective input ports in input queues prior to switching. The first cell of each input queue is known as the Head of Line (HoL) cell. For each set of HoL cells that may be directed to a specific output port, the HoL cell with the largest input port queue size is assigned to be switched during the current switching epoch. The method and apparatus for arbitration allows the crossbar cell switch to operate with smaller input queues, increasing the throughput of the switch and minimizing both the transit delay for the data cells through the switch and the buffer size needed to accommodate input queues.

Abstract: There is disclosed an QoS-oriented burstification method supporting various grades of burstification delay guarantee. For the arrival packets, the packets are sequentially inserted in a sequence of windows on weight basis, thereby forming a queue. The window size together with the weight of each flow determines a maximum number of packets of each flow in a window. For the departure packets, there is generated a burst consisting of a plurality of packets from the head of the queue when either a total number of packets reaches a maximum burst size or a burst assembly timer expires.

Abstract: A process for the control of forwarding packets of completed packet sequences of packet-switched networks as well as a software module, an interface, a terminal device, and a server for this purpose. In these packets of packet sequences, information is transported segmentally. First, that the authorization of a packet to be forwarded is tested by using the transported information of the packet by way of comparison with a certain criterion, at least whenever the packet belongs at the start of a packet sequence (C11A, C12A, C13A).

Abstract: A network switch maintains transmit queues and for each transmit queue a table which identifies the contributions of traffic received at the ingress ports to that queue. When a queue is too long, a pause frame is dispatched from a selected one of the ingress ports. The ingress port may be selected as that making the greatest contribution to the transmit queue. However, a control algorithm allows ports carrying high priority traffic to be excluded from the selection.

Abstract: A reassembly unit comprising of a reassembly buffer and a control unit and a detector. The reassembly unit monitors an amount of data AMD stored in the reassembly register and compares AMD to four thresholds, TS1, TS2, TS3 and TS4. TS1 and TS4 define the size of the reassembly buffer. TS2 defines the delay of reassembly unit 40. A difference between TS1 and TS2 defines an underflow recovery period in which data is not read out of the buffer. A difference between TS4 and TS3 define an overflow recovery period in which data is not written in the buffer. The four thresholds can be changed during an operation of the reassembly unit, allowing a user to adjust the thresholds according to the state of the reassembly unit.

Abstract: A switching fabric connects input ports to output ports. Each input has an input pointer referencing an output port, and each output has an output pointer referencing an input port. An arbiter includes input and output credit allocators, and an arbitration module (matcher). The input credit allocator resets input credits associated with input/output pairs and updates the input pointers. Similarly, the output credit allocator resets output credits associated with input/output pairs and updates the output pointers. The matcher matches inputs to outputs based on pending requests and available input and output credits. A scheduler schedules transmissions through the cross-bar switch according to the arbiter's matches.

Abstract: A switch for switching traffic from N sources to M destinations, where M and N are each an integer greater than or equal to 2. The switch includes K segments, where K is greater than or equal to 2 and is an integer. Each segment receiving traffic from R of the N sources, where 1≦R<N and is an integer, and all K segments in total receiving traffic from the N sources. Each segment collecting and queuing traffic from the respective R sources. The switch includes an arbitrator which receives information from the destinations regarding if they can receive data or not, and from the K segments about the traffic they have for different destinations. A method for switching traffic from N sources to M destinations, where M and N are each an integer greater than or equal to 2. The method includes the steps of receiving traffic from the N sources at input ports of K segments, where K is greater than or equal to 2 and is an integer.

Abstract: A novel method of flow control in a multiport data switching system having a decision making engine for controlling data forwarding between receive ports and at least one transmit port. Data blocks representing received data packets are placed in a plurality of data queues to be processed by the decision making engine. The data queues allocated to the receive ports are monitored to produce a flow control threshold signal for a selected data queue to indicate a heavy traffic condition of a receive port corresponding to the selected data queue. For example, the flow control threshold signal may indicate that the receive port is close to an overflow condition. Monitoring of a selected data queue may be performed by comparing a write pointer indicating a memory location for writing the data blocks into the selected data queue with a read pointer indicating a memory location for reading the data blocks from the selected data queue.

Abstract: A method and system of combining a plurality of parallel communication channels to emulate a single high-bandwidth communication channel. A continuous stream of packets are grouped as traffic aggregates and assigned to queues associated with the plurality of parallel communication channels. The assignment and reassignment of traffic aggregates to the queues is performed dynamically based on measuring the queue load ratios associated with the lengths of the queues for each of the parallel communication channels. Grouping of existing and future packets as traffic aggregates is based on common attributes shared by the packets such as common source and destination IP addresses.

Abstract: An apparatus and method are disclosed for maintaining free buffer information for a network switch. A first Random Access Memory (RAM), located on the network switch, functions to store values that indicate whether or not free buffers, located in a second RAM, are available for storing received data frames. An input logic is provided for placing values in the first RAM to indicate which free buffers are available for storing the data frames. When free buffers are required to store data frames, the output logic searches the first RAM and locates values that indicate available free buffers in the second RAM. The output logic then generates buffer pointers that address the locations of the free buffers in the second RAM. The buffer pointers that are generated are stored in a small capacity queue on the network switch to provide immediate availability to free buffers.

Abstract: A packet switch which can cyclically use &agr; scheduling process results to determine one of M output lines as a destination of a packet stored in each of N input buffer sections by &agr; scheduler sections independently performing scheduling processes is disclosed.

Abstract: A packet memory system including a memory space having a multiplicity of addressable memory locations for the storage of data packets, pointer control means for generating a write pointer which progressively defines where data is to be written to the memory space and a read pointer which progressively defines where data is to be read from the memory space and an ageing clock which defines a succession of intervals. The pointer control means generates a ‘current’ pointer and a ‘discard’ pointer and for each interval is operative to cause the ‘current’ pointer to correspond to an immediately previous value of the write pointer and to cause the discard pointer to correspond to an immediately previous value of the said current pointer. In this manner the portion of the memory space between the ‘discard’ pointer and the read pointer denotes data which has been in said memory space for at least two of said intervals.

Abstract: The invention provides a system and method of controlling timing of release of traffic for a communication switch. The traffic originates from at least one source, is directed to a common ingress point of the switch and is directed to a common egress point in the switch. The egress point has a maximum egress transmission rate. The traffic has at least one datastream. Each datastream has a requested transmission rate. The method comprises, for each datastream, establishing a maximum cell release rate such that a sum of each of the maximum cell release rate does not exceed the maximum egress transmission rate and utilizing the maximum cell release rate to govern release of local traffic in the datastream from the ingress point.

Abstract: Defines and handles segments in messages to place pauses and interruptions within the communication of a message between transmitted segments of the message. A port cache of the destination node of each transmitted message obtains a message control block (MCB) which is used to control the reception of inbound segments within each message sent or received by the node. Each MCB stays in the cache only while its message is being communicated to the port and may be castout between segments in its message when there is no empty cache entry to receive a MCB for a current message being communicated but not having its MCB in the cache.

Abstract: Disclosed is a system for scheduling reservation of traffic with priority, in which each of input ports detects the reserved addressed output port for a high priority traffic by detecting signaling of the traffic and notifies the reserved addressed output port to a scheduler, the scheduler sets a switch connection for passing the high priority traffic with priority every time slot and assigns other switch connections to best effort traffics, and when the switch connections are determined, outputs grant signals to input ports and setting signal to a switch.

Abstract: A packet switch for switching variable length packets, wherein each of output port interfaces includes a buffer memory for storing transmission packets, a transmission priority controller for classifying, based on a predetermined algorithm, transmission packets passed from a packet switching unit into a plurality of queue groups to which individual bandwidths are assigned respectively, and queuing said transmission packets in said buffer memory so as to form a plurality of queues according to transmission priority in each of said queue groups, and a packet read-out controller for reading out said transmission packets from each of said queue groups in the buffer memory according to the order of transmission priority of the packets while guaranteeing the bandwidth assigned to the queue group.

Abstract: A data switch for network communications includes a data port interface which supports at least one data port which transmits and receives data. The switch also includes a CPU interface, where the CPU interface is configured to communicate with a CPU, and a memory management unit, including a memory interface for communicating data from the data port interface to the switch memory. A communication channel is also provided, communicating data and messaging information between the data port interface, the CPU interface, the switch memory, and the memory management unit. The data port interface also includes an access control unit that filters the data coming into the data port interface and takes selective action on the data by applying a set of filter rules such that access to the switch is controlled by the set of filter rules.

Abstract: A switching method and apparatus operates as a work conserving network device. An arbiter using an arbitration algorithm controls a switch fabric interconnecting input ports and output ports. To switch cells, a virtual output queue of an input port is selected that corresponds to an output port with a lowest occupancy rating and a request is sent to this output port. In a greedy version of the algorithm, input ports may send requests to the lowest occupied output port for which they have a cell. In a non-greedy version, requests may only be sent if that input port has a cell for the lowest occupied output port in the entire network device. An output port that receives one or more requests from input ports uses an input port selection algorithm to select an input port from which to receive a packet. After as many input and output ports are matched as is possible in a phase, the packets for those matched ports are transferred across the switch.

Abstract: An apparatus and method for queuing data such as data being transferred across or within a switching node on a network are described. The queuing apparatus includes a plurality of inputs for receiving data to be transferred to at least one output, each input being adapted to receive data at a data rate associated with the input. Each input transfers data to a relatively short queue which stores the data received at the input. Each output is associated with as many short queues as their inputs capable of transferring data to the output. A long queue associated with the output receives data from each of the short queues associated with the output and forwards the data to the output. A control circuit associated with the output transfers data stored in all of the short queues associated with the output into the long queue. This transfer takes place at a data rate that is higher than the data rate associated with the input such that the short queues are prevented from becoming full.

Abstract: For allocating radio resources in a time-division multiple access packet mode radio communication system, each remote station stores transmit authorizations for each time slot of a frame in a table. The packets are stored in a plurality of queues in each remote station. The table is duplicated and one table is read during a frame while the other table is being written.

Abstract: A low-cost, high-speed data switching system and method uses several parallel switching systems or fabrics. In one of various embodiments, for example, the constituent data flows in a data stream can be selectively routed to a switching fabric that has the lowest input data rate. Data flows can be assigned to the various switching fabrics so as to balance the amount of data passing through each parallel system. Data flows can be re-assigned on an as-needed basis to insure maximum throughput. In the case where a data flow initially routed into one switching fabric must be re-routed to a different fabric, the ordering of data packets can be preserved by withholding the transfer of packets through the second fabric until the packets previously sent into the first fabric have cleared. Methods and apparatus of the present invention find application to parallel computing as well.

Abstract: An architecture that achieves high speed performance in a network protocol handler combines parallelism and pipelining in multiple programmable processors, along with specialized front-end logic at the network interface that handles time critical protocol operations. The multiple processors are interconnected via high-speed interconnect, and each processor's memory is globally accessible by other processors. Each processor has multiple threads, each capable of fully executing programs. Each processor contains embedded dynamic random access memory (DRAM). Threads within a processor are assigned the processing of various protocol functions in a parallel/pipelined fashion. Data frame processing is done by one or more of the threads to identify related frames. Related frames are dispatched to the same thread so as to minimize the overhead associated with memory accesses and general protocol processing.

Abstract: A head of line (HOL) blocking count value, which is directly proportional to the committed traffic load for traffic flow through an output port within a multi-stage switch mesh, is computed for a path by adding the values associated with all output ports within the path. In selecting a route, all paths from the source to the destination are identified and sorted by head of line blocking count value. Rather than selecting a path based on traffic load, the path having the lowest head of line blocking count value and sufficient capacity for the requested traffic is selected, with selection between paths having equal head of line blocking count values being made based on traffic load.

Abstract: A method and apparatus are disclosed for scheduling arriving data packets for input to a switch having a plurality of input channels, and a plurality of output channels, the scheduling method is performed in successive scheduling phases where each scheduling phase further comprises at least log N scheduling iterations. The method is a parallelized weight-driven input queued switch scheduling algorithm which possesses good bandwidth and delay properties, is stable, and can be configured to offer various delay and quality of service (QoS) guarantees. The scheduling method utilizes envelope scheduling techniques and considers partially filled envelopes for scheduling.