Abstract: A data flow control device in a streaming architecture chip includes at least one first data buffer module, at least one operation module and at least one second data buffer module. The second data buffer module is configured to send a flow control count signal to the first data buffer module, the flow control count signal being used for informing the first data buffer module of an amount of data that can be received of the second data buffer module. The first data buffer module is configured to send a data signal and a valid signal to the second data buffer module via the operation modules according to the flow control count signal, the valid signal being used for indicating that a corresponding data signal is valid.

Abstract: Deterministic real-time multi-protocol heterogeneous packet-based transport is achieved by traffic shaping. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets pass traffic scheduling or traffic shaping prior being sent via a plurality of connections to avoid burstiness and to achieve bounded transport latency in the plurality of connections, thereby providing deterministic real-time behavior in distributed systems.

Abstract: Deadlocks in a multi-protocol heterogeneous packet-based transport system are avoided while maintaining real-time aspects. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets are sent via a plurality of connections so that each connection from the plurality of connections only transports packets from the second plurality of packets that encapsulate packets from the first plurality that have a same packet type.

Abstract: Systems and methods are provided for scheduling the transmission of CPRI traffic over Ethernet in a datapath. A source node can send a registration request indicating its preferred sending time for data transmission. Intermediate nodes can determine if there are overlaps in timeslot reservations and adjust, and schedule, the requested preferred sending time accordingly.

Abstract: Deadlocks in a heterogeneous packet-based transport system are avoided. When receiving a plurality of packets from a root complex where contents of each packet from the plurality of packets organized in accordance with a first protocol, a sequence number is added to each packet and a packet type is identified. Every packet in the first plurality of packets is encapsulated into at least one packet organized in accordance with a second protocol to form a second plurality of packets organized in accordance with the second protocol. All the packets from the second plurality of packets are sent via a plurality of connections so that each connection from the plurality of connections only transports packets from the second plurality of packets that encapsulate packets from the first plurality that have a same packet type.

Abstract: Example implementations relate to hybrid arbitration of requests for access to a shared pool of resources. An example implementation includes receiving a set of requests for access to the shared pool of resources. The requests may each be from any number of traffic classes. A traffic class may be selected according to turn-based arbitration logic. Additionally, a request from each traffic class of a subset of received requests may be selected. A request selected by the age-based arbitration logic and of the selected traffic class may be granted access to the shared pool of resources.

Abstract: An on-chip optical interconnection structure and network, where the on-chip optical interconnection structure includes M levels of optical switches, and mth-level optical switches in the M levels of optical switching devices include 2m-1 optical switches. Each optical switch in (i-1)th-level optical switches in the M levels of optical switches is coupled to two optical switches in ith-level optical switches. Two optical switches in the ith-level optical switches coupled to a same optical switch in the (i-1)th-level optical switches are coupled. The on-chip optical interconnection network is divided into levels, and switches coupled in a grid manner are formed such that hierarchical switching may be performed, and conflicts and delays in communication are reduced.

Abstract: The flow of data in an integrated circuit is controlled. The integrated circuit comprising a plurality of tiles, each tile comprising a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a receive buffer to store data from the switch. At a first tile, a count is maintained of data that has been sent to a second tile without receiving an acknowledgement up to a credit limit. At the second tile, data that arrives from the first tile when the receive buffer is full is sent to a memory outside of the tile.

Abstract: A connection method, adapted for an electronic device is provided.

Abstract: A packet is received. A flow associated with the packet is determined. An access control (“AC”) policy for the flow is determined. The flow in a flow set is organized for transmission based at least on the AC policy. A bandwidth for the flow is monitored. The flow is marked for transmission based on the monitoring.

Abstract: Methods to achieve bounded router buffer sizes and Quality of Service guarantees for traffic flows in a packet-switched network are described. The network can be an Internet Protocol (IP) network, a Differentiated Services network, an MPLS network, wireless mesh network or an optical network. The routers can use input queueing, possibly in combination with crosspoint queueing and/or output queueing. Routers may schedule QoS-enabled traffic flows to ensure a bounded normalized service lead/lag. Each QoS-enabled traffic flow will buffer O(K) packets per router, where K is an integer bound on the normalized service lead/lag. Three flow-scheduling methods are analyzed. Non-work-conserving flow-scheduling methods can guarantee a bound on the normalized service lead/lag, while work-conserving flow-scheduling methods typically cannot guarantee the same small bound.

Abstract: A multi-level replication counter storage device for multicast packet processing includes a first-level storage device and a second-level storage device. The first-level storage device stores a plurality of first count values associated with a same cell data of a first multicast packet required to be broadcasted to a plurality of multicast targets, wherein a sum of the stored first count values is equal to a number of multicast targets to which the same cell data of the first multicast packet is not broadcasted yet. The second-level storage device stores a second count value which is adjusted based on the first count values to indicate whether a multicast operation of the same cell data of the first multicast packet is accomplished.

Abstract: A method for determining padding compatibility is disclosed. A determination is made of a number of protocol data units (PDUs) for a logical channel mapped to a transport channel such that, for a logical channel allowing segmentation, calculate n wherein n=service data unit size/transport block size (SDU size/TB size), and on a condition that n is an integer, setting the number of PDUs=n.

Abstract: A storage controller system may include a host controller that queues host commands as data transfer commands in a plurality of queue channels. The storage controller system may also include a data storage controller that selects data transfer commands for execution. The data storage controller may select all data transfer commands associated with a host command when all of the data transfer commands are located at heads of the queue channels. Alternatively, the data storage controller may select for execution data transfer commands at heads of the queue channels when associated cache areas are available to receive data, regardless of whether all of the data transfer commands associated with a host command are at the heads. The host controller may then retrieve the data in the cache areas when all of the data to be sent to the host in response to the host command is being cached.

Abstract: A data processing apparatus includes multiple processing means that are connected in a ring shape via corresponding communication means respectively. Each communication means includes a reception means for receiving data from a previous communication means, and a transmission means for transmitting data to a next communication means. Connection information is assigned to each of the reception means and the transmission means. The communication means, when receiving a packet that has same connection information as one assigned to its reception means, causes the corresponding processing means to perform data processing on the packet, sets the connection information assigned to its transmission means to the packet, and transmits the packet to the next communication means, and when receiving a packet that has connection information that is not same as one assigned to its reception means, transmits the packet to the next communication means without changing the connection information of the packet.

Abstract: The invention is related to a method of transmitting data whereby a transmission channel towards an access point (10) is shared among a plurality of users (12), the data being transmitted using the Contention Resolution Diversity Slotted ALOHA (CRDSA) method. According to the invention the number of copies (14a,14b, 14c; 16a, 16b, 16c; 18a,18b,18c) of data packet (14, 16, 18) transmitted simultaneously by a user (12) within one frame is varied.

Abstract: An intelligent electronic device segregates urgent data frames from non-urgent data frames on reception so that the urgent data frames may be handled with greater priority. A switching device is disposed between an external network interface and multiple internal network ports. Based on a network data type indicia, urgent data frames are routed to one of the ports, and non-urgent data frames are routed to another port. A processor coupled to the internal network ports handles urgent data frames before handling any non-urgent data frames.

Abstract: A method for routing input/output (10) data in a telecommunication system including a network node having a plurality of first integrated circuit (IC) cards, a plurality of second IC cards and a switching fabric, each second IC card connected to a corresponding first IC card in a respective slot of the network node xs described. The method involves receiving the IO data at an external port of any of the plurality of first or second IC cards. When packets of the IO data are received at an external port of a given second IC card, the given second IC card performs a packet classification of the packets to at least in part determine a destination for the packets. A further step of the method includes delivering the packets to a first or second IC card destination according to the packet classification performed by the given second IC card via a logical network layer existing on the first and second IC cards and the switching fabric.

Abstract: A buffer temporarily stores data received from a network by a receiving unit. An output mode switching unit switches the mode in which the data received by the receiving unit is output to the buffer, between FIFO and FILO, in accordance with the storage amount of data temporarily stored in the buffer. For example, if the data temporarily stored in the buffer falls below a given threshold value of the buffer, data is stored in the buffer in FIFO. If the data temporarily stored in the buffer exceeds a given threshold value of the buffer, data is stored in the buffer in FILO. A sending unit outputs data taken from the buffer in FIFO or FILO, to a network.

Abstract: A multi-function device capable of executing a plurality of functions, the device comprising: a first acquisition unit configured to acquire communication state information relating to a current communication state of the multi-function device; a determination unit configured to determine: a first priority order in a case of a first state indicating that the current communication state of the multi-function device is good; and a second priority order in a case of a second state indicating that the current communication state of the multi-function device is poor, wherein the second priority order is different from the first priority order, and wherein each of the priority orders indicate each of priorities of the plurality of functions; and a data transmission unit configured to execute preferentially a transmission of data for a high-priority function earlier than a transmission of data for a low-priority function, based on the determined priority order.

Abstract: An interface and corresponding method, where the interface is connected via a first connection to a factory data bus of a vehicle which transports signals according to a first data format, and further connected via a second connection to a data channel of the aftermarket component which transports signals according to a second data format. The interface identifies a factory data bus type corresponding to the factory data bus, out of a plurality of potential factory data bus types. The interface receives digital signals from the aftermarket component via the second connection, the digital signals being in the second data format which corresponds to the aftermarket component. The interface translates the digital signals into the first data format which corresponds to the identified factory bus type. The interface transmits the translated digital signals in the first data format to the vehicle via the first connection.

Abstract: A Network Interface (NI) includes a host interface, which is configured to receive from a host processor of a node one or more cross-channel work requests that are derived from an operation to be executed by the node. The NI includes a plurality of work queues for carrying out transport channels to one or more peer nodes over a network. The NI further includes control circuitry, which is configured to accept the cross-channel work requests via the host interface, and to execute the cross-channel work requests using the work queues by controlling an advance of at least a given work queue according to an advancing condition, which depends on a completion status of one or more other work queues, so as to carry out the operation.

Abstract: A crossbar switch with primary and secondary pickers is described herein. The crossbar switch includes a crossbar switch command scheduler that schedules commands that are to be routed across the crossbar from multiple source ports to multiple destination ports. The crossbar switch command scheduler uses primary and secondary pickers to schedule two commands per clock cycle. The crossbar switch may also include a dedicated response bus, a general purpose bus and a dedicated command bus. A system request interface may include dedicated command and data packet buffers to work with the primary and secondary pickers.

Abstract: A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data and at least one egress module for transmitting the incoming data to at least one egress port. The at least one egress module includes an egress scheduling module and multiple queues per each of the at least one egress port. Each of the multiple queues serve data attributable to a class of service, and the egress scheduling module is configured to service a minimum bandwidth requirement for each of the multiple queues and then to service the multiple queues to allow for transmission of a maximum allowable bandwidth through a weighting of each of the multiple queues.

Abstract: In one embodiment, a method for processing a series of MAC-hs protocol data units (PDUs) in an HSDPA-compatible (high-speed downlink packet access) receiver in a 3G wireless communication network, the method including: (a) receiving a MAC-hs PDU having: (i) a queue identification (QID), (ii) a transmission sequence number (TSN), and (iii) one or more MAC-d PDUs, (b) then disassembling the MAC-hs PDU (c) then distributing the one or more MAC-d PDU to a reordering queue indicated by the QID, and (d) then performing reordering processing for the corresponding reordering queue based on the TSN. Steps (a) and (b) are performed in a physical layer of the receiver. Steps (c) and (d) are performed in a data-link layer of the receiver.

Abstract: Transmitting from a mobile terminal to a telecommunication network data stored in a plurality of queues, each queue having a respective transmission priority, includes setting the data in each of the queues to be either primary data or secondary data, or a combination of primary data and secondary data. The data may be transmitted from the queues in an order in dependence upon the priority of the queue and whether the data in that queue are primary data or secondary data. Resources for data transmission may be allocated such that the primary data of each of the queues are transmitted at a minimum predetermined rate and such that the secondary data of each of the queues are transmitted at a maximum predetermined rate, greater than the minimum predetermined rate.

Abstract: One embodiment of the present invention provides a system that facilitates flow control of multi-path-switched data frames. During operation the system transmits from an ingress edge device data frames destined to an egress edge device across different switched paths based on queue status of a core switching device and queue status of the egress edge device. The egress edge device is separate from the core switching device.

Abstract: Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue.

Abstract: Each transmission port module includes a plurality of queues in association with combinations of a priority and a VLAN number. An accumulated-amount storage unit stores a total size of packets accumulated in queues associated with the same priority. A threshold storage unit stores a threshold of a total packet accumulated amount for each queue. When a packet is received, whether to discard the packet is determined based on a total packet accumulated amount stored in the accumulated-amount storage unit in association with a priority set for the packet and the threshold stored in the threshold storage unit in association with a storage-destination queue of the packet.

Abstract: A system determines a scheduling value based on a current length of a downstream queue in a network device. The system sends the scheduling value from the downstream queue to an upstream queue and schedules dequeuing of one or more data units, destined for the downstream queue, from the upstream queue based on the scheduling value.

Abstract: A method, computer readable medium, and apparatus for managing server resources includes receiving at a traffic management device one or more requests in a message based protocol. The traffic management device determines a difference between a level of utilization of resources maintained by a server that handles the one or more received requests and a threshold level of utilization of resources that can be maintained by the server; and randomly delays the one or more requests based upon the determined difference.

Abstract: An interconnection network with m first electronic circuits and n second electronic circuits, comprising m interconnection sub-networks, each interconnection sub-network including: at least one addressing bus and one information transfer bus connecting one of the m first circuits to all the n second circuits, the information transfer bus comprising a plurality of portions of signal transmission lines connected to each other through signal repeater devices, and a controller device that controls the signal repeater devices, at least one of the signal repeater devices is controlled to be active depending on a value of an addressing signal to be sent to the addressing bus by said one of the m first circuits to the controller device, where m and n are integer numbers greater than 1.

Abstract: Network switching and/or routing devices can use multiple priority data streams and queues to support prioritized serial transmission of data from line cards (or the like) through a fabric switch to other line cards (or the like). Preemption logic is used to insert within a data stream commands indicating a switch from one priority level data to another. Delimiter commands and combination switch/delimiter commands can also be used. Multiple crossbars are implemented in the fabric switch to support the various data stream priority levels.

Abstract: A data communication system includes a portable electronic apparatus, a server apparatus, a cradle apparatus, and a home apparatus. The portable electronic apparatus includes a communication section, a reception control section, a storage section, and a utilization control section. The cradle apparatus includes a first communication section, a second communication section, a connection detection section, a notification control section, and a relaying control section. The server apparatus includes a first communication section, a second communication section, a first transmission control section, and a relaying control section. The home apparatus includes a communication section, a preparation section, and a transmission control section.

Abstract: A digital broadcast transmitting/receiving system and a method for processing data are disclosed. The method for processing data may enhance the receiving performance of the receiving system by performing additional coding and multiplexing processes on the traffic information data and transmitting the processed data. Thus, robustness is provided to the traffic information data, thereby enabling the data to respond strongly against the channel environment which is always under constant and vast change.

Abstract: A memory system for ingress processing is arranged to access multiple banks in a time interleaved fashion. Each memory bank has an associated memory bank manager, which is arranged to track the contents and egress ports associated with data stored in the memory bank. Incoming data from ingress traffic is evaluated and segregated based on criteria. One of the memory banks is identified based on the criteria, and the incoming data is stored in the identified memory bank in the next available write cycle timeslot. Data constructs in the memory bank manager are updated to indicate the location and egress port associated with the stored data. The memory bank managers submit egress transmit bids to a master scheduler, which controls access to the memory banks. The memory banks are readout in interleaved fashion such that the effective average traffic arrival rate is increased and memory bandwidth requirements are reduced.

Abstract: Embodiments disclosed here relate to scheduling packet transmission in a multi-carrier communication system. In an embodiment, a master scheduler having at least one processor and at least one memory operably connected to the at least one processor is adapted to execute instructions stored in the at least one memory, the instructions comprising selecting a packet with a highest packet metric from among candidate packets from one carrier of a plurality of carriers, whereby expedited forwarding flows do not have a higher metric on another carrier.

Abstract: Examples of are disclosed for configuring one or more routes through a three-stage Clos-network packet switch.

Abstract: A packet switch receives packets at an ingress port, generates enqueue records for the packets, and stores the enqueue records in an enqueue structure. The enqueue record of a packet includes a pass flag for indicating whether a permissive passing rule is applicable to the packet. The packet switch determines a routing order for the packets stored in the ingress port based on the enqueue records and a set of ordering rules including the permissive passing rule. If a packet is blocked in the packet switch, the packet switch identifies an oldest unblocked routable packet stored in the ingress port based on the enqueue records and the set of ordering rules. Further, the packet switch routes the oldest unblocked routable packet through the packet switch. In this way, the packet switch allows the oldest unblocked routable packet to pass the blocked packet in the packet switch.

Abstract: A source-based memory usage table is accessed to identify a source having a memory usage satisfying a predetermined memory usage threshold, the source-based memory usage table including a plurality of source records, each corresponding to a source from which packets are received. A first flow control signal is transmitted to the identified source that has a memory usage satisfying the corresponding predetermined memory usage threshold to control further packet transmission from the identified source. A priority-based memory usage table is accessed to identify a priority of which a memory usage satisfies a predetermined memory usage threshold of the priority. A second flow control signal is transmitted to one or more sources associated with the identified priority having a memory usage satisfying the corresponding predetermined memory usage threshold to control further packet transmission from the identified one or more sources.

Abstract: A method, system and computer program product for transmitting data entities, the method includes: receiving data entities to be transmitted over multiple channels; and preventing a transmission of data entities that are to be transmitted over congested channels while transmitting data entities that are to be are to be transmitted over non-congested channels.

Abstract: A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.

Abstract: Packets are processed in a system that comprises a plurality of interconnected processor cores. The system receives packets into one or more queues. The system associates at least some nodes in a hierarchy of nodes with at least one of the queues, and at least some of the nodes with a rate. The system maps a set of one or more nodes to a processor core based on a level in the hierarchy of the nodes in the set and based on at least one rate associated with a node not in the set. The packets are processed in one or more processor cores including the mapped processor core according to the hierarchy.

Abstract: A scaling device or striper improves the lane efficiency of switch fabric. The striper controls or adjusts transfer modes and payload sizes of a large variety of devices operating with different protocols. The striper interfaces between network devices and the switch fabric, and the resulting switching system is configurable by a single controller. A source device sends a data packet to its corresponding striper for transmission across the switch fabric to a destination device. The corresponding striper parses the packet to determine its type and payload length, and divides the packet into numerous smaller segments when the payload length exceeds a predetermined length. The segments may be stored in the striper to adapt to the available bandwidth of the switch. The segments are sent across the switch fabric and reassembled at a destination striper. The packet as reassembled is forwarded to the destination device.

Abstract: Each of the plurality of queues stores packet data of a received packet. The read concession assignor assigns one of the plurality of queues with a read concession for a predefined time period. The overdraft storage stores an overdraft amount in connection with each of the plurality of queues. The read adequacy determiner determines, in accordance with an overdraft amount stored in connection with one queue out of the plurality of queues, whether to read packet data from the one queue. The overdraft updater updates at least one of a first overdraft amount stored in connection with a first queue and a second overdraft amount stored in connection with a second queue different from the first queue upon reading packet data from the first queue during a time period while the second queue is assigned with the read concession.

Abstract: There is disclosed a method, apparatus and computer program for communicating messages between a first messaging system and a second messaging system. The messaging system comprises a set of source queues with each source queue owning messages retrievable in priority order. It is determined that a message should be transferred from the first messaging system to the second messaging system. A source queue is selected which contains a message having at least an equal highest priority when compared with messages on the source queues. A message having the at least equal highest priority from the selected source queue of the first messaging system is then transferred to a target queue at the second messaging system.

Abstract: A method of transforming an ordered list of nodes of a network into one of a plurality of elite ordered lists, the ordered list corresponding to a deloading sequence, the deloading sequence including a temporary capacity requirement, each of the elite ordered lists corresponding to an elite deloading sequence including an elite temporary capacity requirement by generating at least one intermediate ordered list corresponding to an intermediate deloading sequence including an intermediate temporary capacity requirement, selecting one of the intermediate ordered list and the ordered list based on a comparison of the intermediate temporary capacity requirement and the temporary capacity requirement and replacing one of the elite ordered lists with the one of the intermediate ordered list and the ordered list if a value corresponding to one of the intermediate temporary capacity requirement and the temporary capacity requirement is less than a lowest value of the elite temporary capacity requirements.

Abstract: A First In First Out (FIFO) communication buffer for receiving data from a source and distributing the data to a first sink and a second sink is disclosed. The FIFO communication buffer includes a FIFO memory and a FIFO control circuit. The FIFO memory includes a first data port, a second data port, and a third data port. The FIFO control circuit provides the first address, the second address and the third address. The FIFO control circuit increments the first address toward the second address and the third address when valid data is received, and increments the second address and the third address when data is read out.

Abstract: A mobile communication device has a wireless transceiver and one or more processors for communicating data in a wireless communication system. The one or more processors are operative to receive a plurality of data packets of varying payload size in a queue; associate one or more of the data packets from the queue into a group, such that a total size of the group is at or near a maximum transmissible unit (MTU) size of a data frame; cause the one or more data packets associated into the group to be formatted into the data frame for data transmission via the wireless transceiver; and repeat, for a plurality of data frames, the associating and formatting, for communicating the data via the wireless transceiver in the wireless communication system. By associating the data packets into groups having the MTU size, data throughput of the data transmission is increased.

Abstract: A switching device comprising at least one ingress port and at least one egress port. The switching device is arranged to receive data packets through the at least one ingress port and to forward received data packets to respective ones of the at least one egress port. The switching device further comprises a primary buffer arranged to store data packets received via at least one of the least one ingress ports and a secondary buffer associated with the primary buffer. The switching device is adapted to select a data packet from the primary buffer and if but only if the secondary buffer satisfies a least one first predetermined criterion, transfer the selected data packet to the secondary buffer.