Abstract: An exhaustive service dual round-robin matching (EDRRM) arbitration process amortizes the cost of a match over multiple time slots. It achieves high throughput under nonuniform traffic. Its delay performance is not sensitive to traffic burstiness, switch size and packet length. Since cells belonging to the same packet are transferred to the output continuously, packet delay performance is improved and packet reassembly is simplified.

Abstract: The present invention provides method for data packet processing in a telecommunications system. The method of the present invention can include the steps of (i) determining a set of classification parameters for a data packet at an ingress edge unit, wherein the classification parameters include a packet destination, (ii) communicating the data packet to an egress edge unit and (iii) routing the data packet to a destination egress port at the egress edge unit according the classification parameters determined at the ingress edge unit. In one embodiment of the present invention, the classification parameters can include a destination egress edge unit, a destination egress port at the destination egress edge unit, and quality of service parameter for proper processing of the data packet.

Abstract: A method of providing virtual output queue feedback to a number of boards coupled with a switch. A number of virtual queues in the switch and/or in the boards are monitored and, in response to one of these queues reaching a threshold occupancy, a feedback signal is provided to one of the boards, the signal directing that board to alter its rate of transmission to another one of the boards. Each board includes a number of virtual output queues, which may be allocated per port and which may be further allocated on a quality of service level basis.

Abstract: Arbitration for a switch fabric (e.g., an input-buffered switch fabric) is performed. For a first port, a link subset from a set of links associated with the first port is determined. Each link from the link subset is associated with its own candidate packet and is associated with its own weight value. A link from the link subset for the first port is selected based on the weight value associated with each link from the link subset for the first port. For a second port, a link subset from a set of links associated with the second port is determined. Each link from the link subset associated with the second port is associated with its own candidate packet and is associated with its own weight value. The determining for the second port is performed in parallel with the determining for the first port. A link from the link subset for the second port is selected based on the weight value associated with each link from the link subset of associated with the second port.

Abstract: In one embodiment, an integrated circuit provides a test access port that communicates with scan chain registers in a processor core. The integrated circuit synchronizes data transferred between a debug controller that operates under control of a test clock (TCK) and the processor core that operates under control of a processor clock (CLK).

Abstract: The multi-initiator control unit for performing packet-unit communication with each of a plurality of devices connected via a transmission line includes: a packet filter for analyzing a received packet and outputting the results; a plurality of command control circuits each for controlling a command processing sequence performed with the corresponding device; a multi-control circuit for giving sequence execution permission to one of the plurality of command control circuits; and a packet processing circuit for generating a packet containing information output by the permission-given command control circuit and outputting the packet for transmission, and also outputting a received packet according to the analysis results output by the packet filter.

Abstract: In one embodiment, queues associated with a first traffic class (FTC) are selected for service. Each FTC queue having at least one enqueued cell is identified as an occupied FTC queue, Where at least one FTC queue is provisioned for burst scheduling of multiple cells when serviced. An occupied FTC queue provisioned for burst scheduling is identified as a super-occupied FTC queue when the number of cells enqueued is greater than a specified number. Each occupied FTC queue is set as eligible for service based on a FTC scheduling algorithm. An eligible FTC queue is selected for service based on a corresponding sub-priority of each eligible FTC queue. Each FTC queue is assigned a sub-priority based on a service level of a connection associated with enqueued cells. When the super-occupied queue is serviced, the number of cells dequeued is based on a burst size.

Abstract: A method and system for detecting and controlling congestion in a multi-port shared memory switch in a communications network. The proposed congestion management scheme implements a local and a global congestion monitoring process. The local monitoring process monitors the queue depth. When the queue depth for any queue exceeds a queue length threshold a congestion control mechanism is implemented to limit incoming data traffic destined for that queue. Additionally, the global congestion monitoring process monitors the shared memory buffer and if the traffic thereto exceeds a shared memory buffer threshold a congestion control mechanism limits incoming traffic destined for any output queue which has been exceeding a fair share threshold value.

Abstract: A method and system for controlling a plurality of pipes in a computer network, including at least one processor for a switch, the at least one processor having a queue, the plurality of pipes utilizing the queue for transmitting traffic through the switch, wherein each pipe is assigned a priority ranking class, each class has a unique priority rank with respect to each of the other classes, the ranks ranging from a highest priority rank to a lowest priority rank. A transmission probability is calculated for each pipe responsive to its priority rank. If excess bandwidth exists for the queue, the transmission probability of each pipe is linearly increased. Alternatively, if excess bandwidth does not exist, the transmission probability for each pipe is exponentially decreased. Packets are transferred from a pipe to the queue responsive to the pipe transmission probability and priority rank.

Abstract: An ATM switch includes a first stage, a second stage and a third stage each of which stages includes at least one basic switch, wherein the first stage, the second stage and the third stage are connected. The basic switch includes a part which refers to time information written in a header of an input cell and switches cells to an output port in an ascending order of the time information. In addition, the ATM switch includes a cell distribution part in the basic switch of the first stage. The cell distribution part determines a routes of a cell to be transferred such that loads of routes within the ATM switch are balanced. The ATM switch further includes an adding part which adds arriving time information to an arriving cell as the time information.

Abstract: A switch node includes arbiter logic configured to gather global information regarding switching requests within the switch node and to control switching of one or more packets through the switch node. The arbiter logic may include a bus snooping interface configured to detect the switching requests within the switch node. The bus snooping interface includes a plurality of switching request destination registers configured to store switching request destination information from the detected switching requests. In addition, the arbiter logic includes a packet switching request array configured to transmit a next switching request within the switch node according to prior switching request destination information stored in the switching request destination registers. The switching of the one or more packets may be through a cross-point switch matrix in the switch node.

Abstract: There is provided a packet scheduler for managing output awaiting packets stored in a plural of queue blocks each having a weighting coefficient settled based on an output guaranteeing bandwidth, whereby an output order for the head packets is stored in respective queue blocks. The packet scheduler includes means for controlling selection of a queue having a packet to be sent at the highest priority, based on scheduled output time information obtained by calculation using management information of the output awaiting packets and the weighting coefficient of each queue, and means for correcting processing carried out in the controlling means based on the current time information. The arrangement enables to ensure assignment of vacant bandwidth in a fair manner while suppressing erroneous operation deriving from deviation of a scheduled packet output time from the real time caused by a calculation error or the like in WFQ calculation.

Abstract: A method for selecting packets comprises pipelining execution of packet selection processes so that execution of each of the packet selection processes occurs at different levels of a scheduling hierarchy. At least two different packets are selected at two different times in response to execution of the packet selection processes.

Abstract: In a data switching system, the ingress and egress ports of a memoryless cross-bar switch are controlled by an arbitration method. The arbitration method uses a three phase process involving (i) a request phase in which each ingress port sends its connection requests to egress ports to which a connection is required, (ii) a grant phase in which each egress port uses a grant pointer to select one of the requests directed to it using a grant pointer, and generates a grant signal, and (iii) an accept phase in which each ingress port selects one of the received grant signals to accept, so defining an ingress to egress port connection across the cross-bar switch. The transition sequences for each of the grant pointers are mutually exclusive, so that any synchronisation of the grant pointers is eliminated on the next arbitration cycle. This is arranged by a setting of the paths taken by request and grant signals.

Abstract: A method and apparatus provides QoS shaping/provisioning scheme for a data communications switch, such as a DiffServ aware router or a 802.1Q aware bridge, in which distinct internal and outbound priority values are assigned to a packet based on flow properties associated with an inbound packet. The flow properties used to assign the internal and outbound priority values may include at least one value from a packet field that is not dedicated to defining QoS. The internal priority value provides a priority to the packet during processing in the switch. The outbound priority value is applied to the packet in lieu of the inbound priority value prior to transmitting the packet from the switch. The flow properties used to determine the internal and outbound priority values may include, for example, Layer 2, Layer 3, and Layer 4 information encoded in the packet.

Abstract: A data network including at least one crossbar, wherein each crossbar comprises N ports and a plurality N of devices each associated with and connected to one port of one of the crossbars. Each one port of one crossbar includes an input buffer, a plurality N?1 of port output buffers, a plurality N?1 of fullness sensors, shutoff devices. The input buffer receives messages from the device connected to its port and sends the messages to the other ports of the one crossbar. Each port output buffers corresponds to one of the other ports, wherein each port output buffer receives the messages only from the input buffer of its associated other port. Each fullness sensor is associated with one port output buffer and measures the fullness state of its associated port output buffer.

Abstract: A redundant information processing system with sufficient reliability is provided at a moderate cost without any part that could be a single fault point in the system. In the redundant information processing system in which an actuator 5 is controlled based on a signal from a sensor 4, each of processing devices 1A to 1C collects command signals from other processing devices and determines which command signal to be valid according to a logical decision, for example, a majority decision. When the command signals of more than two of the processing devices including the relevant processing device which determines are valid, the command signals are output according to priority while a control information blocking signal is output to a processing device other than those which are valid.

Abstract: A congestion control method and apparatus in a cell-switched data switch. The switch attaches a tag with a discard processing indicator, such as a particular random number, to all cells belonging to a same packet. In determining which cells to drop when running a congestion control algorithm such as RED, the switch compares the discard processing indicator of the cells with a discard criterion and only drops cells that conform with the discard criterion.

Abstract: In a multi-mode scheduler including a N×kM scheduler for adjusting data transmission between N-pieces of input interface sections and kM-pieces of output interface sections, the multi-mode scheduler, k-pieces of N×M schedulers to be the N×kM scheduler, and (k?1)-pieces of selection circuits for switching allocated output port information input from an outside of the N×kM scheduler and information from a N×M scheduler at front step, so as to be input to the N×M scheduler as allocated output port information, and two operations are set freely with a switching operation of the selection circuits. As a result, it is possible to provide a general scheduler.

Abstract: A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from “empty” to “not empty”, or vice versa, rather than on a “per cell” request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from “not clear to release” to “clear to release”, or vice versa, rather than on a “per cell” grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is “empty” and the opposite binary value when the logical output queue's status is “not empty”.

Abstract: A method of communications employs a communications protocols defining respective responses to predetermined events. The protocol is separated into a first group of behaviours defining responses to corresponding first, relatively frequently occurring, events, and a second group of behaviours defining responses to corresponding first, relatively frequently occurring, events, and a second group of behaviours defining responses to corresponding second, relatively infrequently occurring events. The first group is stored at a user communications terminal. At least the second group is stored at a store remote from the user terminal, and interconnected therewith via a communications channel. Communication is established from the user terminal using first events. On detecting an event other than one of said the first events at the user terminal, event holding data is signaled from the store to the user terminal; and communication is established from the user terminal using the event-handling data.

Abstract: An active partner and a passive partner communicate via a number of parallel data transmission paths by alternately exchanging messages. During the process, a number of the available data transmission paths are initialized and used simultaneously for exchanging messages during normal operation.

Abstract: A data switching device has ingress routers and egress routers interconnected by a switching matrix controlled by a controller. Each ingress router maintains one or more virtual output queues for each egress router. The switching matrix itself maintains a head-of queue buffer of cells which are to be transmitted. Each of these queues corresponds to one of the virtual output queues, and the cells stored in the switching matrix are replicated from the cells queuing in the respective virtual output queues. Thus, when it is determined that a connection is to be made between a given input and output of the switching matrix, a cell suitable for transmission along that connection is already available to the switching matrix. Upon receipt of a new cell by one of the ingress routers, the cell is stored in one of the virtual output queues of the ingress router corresponding to the egress router for the cell, and also written the corresponding head of queue buffer, if that buffer has space.

Abstract: The assignment result reception circuit 11 receives the accumulation assignment result from the external portion, and sends the already-assigned input port and output port information to the assignment request mask circuit 12. The assignment request mask circuit 12 uses the already-assigned input port and output port information received from the assignment result reception circuit 11, performs the mask process on the connection assignment request received from the external portion, and sends its result to the M×N scheduler circuit 13. The M×N scheduler circuit 13 determines the assignment of the port connection in accordance with the information received from the assignment request mask circuit 12, and sends the connection assignment result to the external portion and the assignment result transmission circuit 14.

Abstract: To address the need for protecting the QoS of high priority flows in a communication network when network conditions vary, original queue weights (B) are modified by a bandwidth allocation adaptor. The modification of the original queue weights is based, in part, on channel conditions.

Abstract: An arbiter which arbitrates between a plurality of clients generating requests for access to a resource in a computing environment, including a memory which includes for each of the plurality of clients a request register, which is adapted to record the respective client's access requests, and a next-client pointer, which is adapted to record an identification of another one of the clients making a subsequent request to access the resource, so as to form a linked list of the requests. The arbiter further includes logic circuitry which is adapted to decide, responsive to the linked list, which of the plurality of clients is given access to the resource.

Abstract: A circuit arrangement improves CPU efficiency by processing data through a FIFO circuit of a UART chip using a CPU adapted to detect, and respond with various options to, the current storage capacity of the FIFO circuit. In one example embodiment, a circuit arrangement includes a universal asynchronous receiver/transmitter (UART) chip having a FIFO circuit and an arithmetic logic unit (ALU) adapted to generate an N-bit variable binary signal, wherein the binary signal varies as a function of a current storage capacity of the FIFO circuit. The circuit arrangement further includes a control circuit communicatively coupled with the UART chip that is adapted to read the N-bit variable binary signal and, in response, to control the data flow through the FIFO circuit.

Abstract: Connection distributors are used to route packets corresponding to multiple streams of packets through a packet switching system. During each time slot, one packet is typically sent from each packet stream. During the configuration of a packet stream, a time slot and primary route is determined for the packet stream. The primary route is a route through the packet switch which is non-blocking with other packet streams during the assigned time slot. During a common frame, a packet of each packet stream is sent out of a line card or packet interface to be routed through the packet switch over the designated primary route. During subsequent frames, packets are sent over different routes through the network (until all routes are used and then the cycle repeats). These routes are selected based on a deterministic method so as to maintain the non-blocking characteristic of the primary route selection.

Abstract: The present invention reduces the number of multicast synchronization delays in a packet switch by determining the mix of packets pending at the input ports. When a sufficient number of multicast packets are ready for transferal, the packet switch preferably transmits a programmed number of multicast packets (or as many multicast packets that exist up to that programmed number). After transmitting these multicast packets, the packet switch resumes preferably transmitting unicast packets. Thus, the number of multicast synchronization delays is reduced over the prior art, the bandwidth utilization of the packet switch is correspondingly increased and the load due to multicast packets and unicast packet is balanced. One embodiment of the invention includes a timer that ensures that multicast packets are transmitted without undue delay.

Abstract: A queued memory switch includes separate devices that switch received data to the outputs of the queued memory switch. Data is received by a first device (the master) and a second device (the slave) at a series of reception times. The slave sends information to the master indicating whether data directed to an output port was received by the slave at each of the reception times. The master stores the information from the slave with information indicating whether data directed to the same output port was received by the master at each of the reception times. The information indicates the order in which the master and slave received their respective data. The indication can be used to transmit the data from master and the slave in the order in which the data was received by the master and the slave. Related methods, systems, and computer program products are also disclosed.

Abstract: A method and apparatus are provided for scheduling multicast data in an input-queued network device. According to one aspect of the present invention, deterministic and bounded delay for high priority multicast cells is guaranteed by the multicast scheduler. The scheduler receives a transmit request associated with each of a plurality of input ports. The transmit request identifies output ports to which pending multicast cells are ready to be transmitted, if any. Then, for each of multiple classes of service, the scheduler performs a single scheduling iteration. The single scheduling iteration includes a grant phase, an accept phase, and an update phase. During the grant phase, the scheduler grants one or more of the input ports access to the fabric by issuing grants based upon the transmit requests and a priority indicator that identifies an input port that is given scheduling priority for the scheduling iteration.

Abstract: For establishing a parent-child relationship between adjacent network nodes interconnected by a transmission medium, a handshaking circuit comprises a state detector for monitoring the transmission medium to detect predetermined first and second states and a contention that occurs when the predetermined first states are simultaneously present. A state machine asserts the first state for initiating a handshaking process and relinquishes this state when a contention is detected. A receive count value is continuously incremented from the instant the contention is detected to the instant the transmission medium changes to an idle state. A transmit count value is continuously incremented from the instant the first state is detected to the instant the contention is detected. When the transmit count value is greater than the receive count value, the state machine asserts the first state again and when the transmit count value is smaller than the receive count value, it asserts the second state.

Abstract: An exhaustive service dual round-robin matching (EDRRM) arbitration process amortizes the cost of a match over multiple time slots. It achieves high throughput under nonuniform traffic. Its delay performance is not sensitive to traffic burstiness, switch size and packet length. Since cells belonging to the same packet are transferred to the output continuously, packet delay performance is improved and packet reassembly is simplified.

Abstract: A method and apparatus for controlling multi-party conference calls includes circuitry which is operable according to a new conference call protocol. The protocol and accompanying apparatus and method allow a conference call controlling party to selectively have private conversations with one of the subject parties in the conference call. Additionally, the controlling conference call party may selectively drop conference call participants. A mobile station includes a store for storing the conference call participant “subject party setup number” in relation to the subject party number and/or name. The mobile station also allows the conference call controller to scroll up and down a list of conference call participants. This allows the controller to be certain of a conference call participant's “call set-up number” when using a command for a private call or a command to drop a conference call participant.

Abstract: A packet memory system including a memory space having a multiplicity of addressable memory locations for the storage of data packets, pointer control means for generating a write pointer which progressively defines where data is to be written to the memory space and a read pointer which progressively defines where data is to be read from the memory space and an ageing clock which defines a succession of intervals. The pointer control means generates a ‘current’ pointer and a ‘discard’ pointer and for each interval is operative to cause the ‘current’ pointer to correspond to an immediately previous value of the write pointer and to cause the discard pointer to correspond to an immediately previous value of the said current pointer. In this manner the portion of the memory space between the ‘discard’ pointer and the read pointer denotes data which has been in said memory space for at least two of said intervals.

Abstract: First to fourth input buffers stores cells inputted from first to fourth input ports, respectively. Each input buffer is equipped with a main buffer section, a plurality of sub-buffer sections connected to the main buffer section in series and a buffer controller for controlling them. A collision judging section judges whether or not a collision occurs between the cells outputted from each sub-buffer section, and the judged result is sent to a cell converter. The cell converter returns a collision information to the buffer controller in accordance with the judged result, and further sends a cell, which has a victory information since it is judged as a victory over the collision, through a sorter to a self-routing section. The self-routing section outputs the received cell to an output port. This configuration enables a shuffle operation to be carried out in the sub-buffer section and the cell converter to thereby avoid the drop of the throughput.

Abstract: A method and apparatus for preserving loop fairness. Some embodiments include a dynamic half-duplex feature. One aspect includes a communications channel system and method for preserving loop fairness that includes a first channel node having one or more ports, each port supporting and attached to a fibre-channel arbitrated-loop serial communications channel. One of the ports will arbitrate for control of that port's attached channel, wherein control of the channel loop, once arbitration is won, a fairness-preserving apparatus causes control of the communications channel to be released based at least in part on whether a predetermined amount of use has occurred between the first port and the communications channel. In some embodiments, the predetermined amount of use includes a transfer of a first predetermined amount of data. In some embodiments, release of control of the channel is inhibited if less than a second predetermined amount of data remains to be transferred.

Abstract: A SIMA Traffic Shaper (STS) and method is disclosed for use between the customer equipment and the SIMA access node to shape the transmitted traffic so that the cells will receive as good priority as possible in the access node. The STS includes an input device for receiving cells from a traffic source, a buffering device, coupled to the input, for holding the cells until instructed to send the cells; and a calculation unit, operatively coupled to the buffer processor, for calculating a send time for sending cells held by the buffering device. The buffering device further includes a buffer and a transmission unit, wherein the buffer holds the cells and the transmission unit sends the cell forward according to the send time received from the calculation unit. A monitoring unit is included for monitoring the input device and the buffering device to obtain loading information regarding the network.

Abstract: For allocating radio resources in a time-division multiple access packet mode radio communication system, each remote station stores transmit authorizations for each time slot of a frame in a table. The packets are stored in a plurality of queues in each remote station. The table is duplicated and one table is read during a frame while the other table is being written.

Abstract: A transmission convergence sublayer circuit and operating method for an asynchronous transfer receiver. The transmission convergence sublayer circuit is coupled between a buffer and a deframer. The deframer submits a data stream enable signal and data bytes to the circuit. The data stream enable signal enables the circuit so that multiple groups of byte data belonging to a data cell are received and temporarily stored inside a byte-wise data pipeline. A header cyclic redundancy checker also receives the byte data and then conducts a header search. An idle cell identifier is used to determine if the data cell is a non-idle cell. When the header is found and determined to be a non-idle cell, a descrambler retrieves payload data of data cell from the byte-wise data pipeline and conducts a descrambling operation after obtaining a quantity of data equal to a double word. Ultimately, the double word data is output to the buffer with minimum delay.

Abstract: A method and system for combined unicast and multicast scheduling. Data cells are assigned at each input to one unicast input queue for each output or to a single multicast input queue. Each input makes two requests for scheduling to each output for which it has a queued data cell, one unicast request and one multicast request. Each output grants up to one request, choosing highest priority requests first and giving precedence to one such highest priority request using an output precedence pointer. The output precedence pointer is either an individual output precedence pointer specific to that output for unicast data cells or a group output precedence pointer generic to all outputs for multicast data cells. Each input accepts up to one grant for unicast data cells or as many grants as possible for multicast data cells, choosing highest priority grants first and giving precedence to one such highest priority grant using an input precedence pointer.

Abstract: The network switch described herein provides a cell/packet switching architecture that switches between line interface cards across a meshed backplane. In one embodiment, the switching can be accomplished at, or near, line speed in a protocol independent manner. The protocol independent switching provides support for various applications including Asynchronous Transfer Mode (ATM) switching, Internet Protocol (IP) switching, Multiprotocol Label Switching (MPLS) switching, Ethernet switching and frame relay switching. The architecture allows the network switch to provision service on a per port basis. In one embodiment, the network switch provides a non-blocking topology with both input and output queuing and per flow queuing at both ingress and egress. Per flow flow-control can be provided between ingress and egress scheduling. Strict priority, round robin, weighted round robin and earliest deadline first scheduling can be provided.

Abstract: A packet switch for switching variable length packets, wherein each of output port interfaces includes a buffer memory for storing transmission packets, a transmission priority controller for classifying, based on a predetermined algorithm, transmission packets passed from a packet switching unit into a plurality of queue groups to which individual bandwidths are assigned respectively, and queuing said transmission packets in said buffer memory so as to form a plurality of queues according to transmission priority in each of said queue groups, and a packet readout controller for reading out said transmission packets from each of said queue groups in the buffer memory according to the order of transmission priority of the packets while guaranteeing the bandwidth assigned to the queue group.

Abstract: In a data packet switching apparatus for switching a data packet, arriving from a plurality of incoming virtual connections in the form of logically multiplexed cells, to a plurality of outgoing virtual connections, efficient use is made of a buffer under congestion. A required data buffer plane quantity monitoring/calculation circuit calculates the number of required data buffer planes (segments) from the packet length contained in the starting cell data, and a packet reception allow/disallow decision/buffer plane quantity securing circuit compares it with the remaining buffer amount. If the number of required buffer planes is larger than the remaining buffer amount, all cell data belonging to the packet are discarded. If the number of required buffer planes is not larger than the remaining buffer amount, the required buffer is presecured by reducing the remaining buffer amount by an amount equivalent to the number of required buffer planes.

Abstract: A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from “empty” to “not empty”, or vice versa, rather than on a “per cell” request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from “not clear to release” to “clear to release”, or vice versa, rather than on a “per cell” grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is “empty” and the opposite binary value when the logical output queue's status is “not empty”.

Abstract: A switch node includes arbiter logic configured to gather global information regarding switching requests within the switch node and to control switching of one or more packets through the switch node. The arbiter logic may include a bus snooping interface configured to detect the switching requests within the switch node. The bus snooping interface includes a plurality of switching request destination registers configured to store switching request destination information from the detected switching requests. In addition, the arbiter logic includes a packet switching request array configured to transmit a next switching request within the switch node according to prior switching request destination information stored in the switching request destination registers. The switching of the one or more packets may be through a cross-point switch matrix in the switch node.

Abstract: A scheduler allocates service to enqueued cells of connections provisioned for guaranteed service levels employing a structure with one or more of the following features to achieve efficient high-speed packet switching (cell relay). For very high-speed switching of connections, such switches operating up to 10, or even 100, Tbps, burst scheduling of cells is employed in which a number of cells, termed a burst, are serviced when a queue is eligible for service. When a queue has less than the number of cells in the burst (termed a short burst), the scheduler still schedules service, but accounts for saved service time (or bandwidth) of the short burst via queue length when the queue's eligibility is next considered for service. In addition, high and low bandwidth connections of a queue may be allocated into two sub-queues, with priority assigned to the two queues and delay-sensitive traffic (high bandwidth connections) assigned to the higher priority sub-queue.

Abstract: In a communication network having a plurality of terminals, such as packet forwarding apparatus, and a transport network which provides a connection between the terminals, when the transport network performs a state transition associated with a brief disconnection, a brief disconnection begin notification signal is sent to a terminal prior to a state transition operation and a brief disconnection end notification signal is sent to the terminal after the state transition operation. The terminal reroutes communication data to a storage or a redundant transport route during the period between the receipt of the brief disconnection begin notification and the receipt of the brief disconnection end notification. Accordingly, the communication data loss due to the brief disconnection between terminals associated with the state transition of the transport network can be reduced or eliminated.

Abstract: An arbiter utilizing a link list to arbitrate access between multiple data sources and a single destination. The arbiter is of the least recently used type whereby the data source that has not sent data for the longest time is given the highest priority. The arbiter provides an arbitration function in a simple manner and at high speeds. The arbiter utilizes a Non Empty Source Queue (NESQ) list that comprises only sources that are non empty, i.e., that have data ready to send. If a source queue chosen for data transmission still has data to send, it is placed at the end of the NESQ list. When a source queue becomes empty after the transmission of data, the source index is removed from the linked list. Conversely, when a source queue that was previously empty receives a new packet it is added to the end of the linked list.

Abstract: A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from “empty” to “not empty”, or vice versa, rather than on a “per cell” request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from “not clear to release” to “clear to release”, or vice versa, rather than on a “per cell” grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is “empty” and the opposite binary value when the logical output queue's status is “not empty”.