Abstract: An ATM switching matrix has input ports, output ports and a passive optical core consisting of optical couplers. Each output port includes at least p optical receivers which are tuned to the same fixed wavelength which is specific to the output port. Each receiver has an input respectively connected to a port of one of the p couplers, a buffer having p inputs respectively connected to the outputs of the p receivers and an output connected to an output of the matrix. The matrix includes distributed allocation arrangements which control switching arrangements of each input port to connect, to k separate couplers, k respective input ports which at the time concerned are receiving k cells addressed to the same output port, k being less than or equal to p, and this operation being repeated for each output port.

Abstract: A packet switching equipment and a switch control system employing the same performs operation of the switch core portion independent of content of decision of an arbiter portion and overall equipment can be constructed with simple control structure. The packet switching equipment includes input buffer portions temporarily storing packets arriving to the input ports and outputting packets with adding labels indicative of destination port numbers, a switch core portion for switching the packets on the basis of labels added to the input buffer portions, and an arbiter portion adjusting input buffer portions to provide output permissions for outputting to the output ports. A sorting network autonomously sorting and concentrating the packets on the basis of the labels added to the packets is employed in the switch core portion.

Abstract: Described herein is a method of cell level scheduling for handling unicast traffic in routing devices, for example, crossbar switches. This is achieved by the provision of support for multimedia and real-time traffic in large bandwidth routing devices known as terabit routers. Each terabit router has a plurality of ingress line interface cards (210, 212, 214, 216), a plurality of egress line interface cards (220, 222, 224, 226) and a cell based cross-bar (202). Each ingress card has a plurality of queues, a different queue for each of the egress cards respectively. The cross-bar (202) is controlled by a cross-bar controller (204) in association with a bandwidth controller (206). In operation, a target rate matrix is maintained over a set period. At the beginning of each period, a matrix of numbers of cells queued to be transmitted is calculated in accordance with the target rate.

Abstract: Described herein is a method for making bandwidth allocation for data to be sent from a plurality of ingress forwarders or LICs (310, 312, 314, 316) to a plurality of egress forwarders or LICs (320, 322, 324, 326) across a routing device (330). The data may be unicast and/or multicast. The bandwidth allocation is calculated in accordance with ingress forwarder multicast queue occupancy for each ingress forwarder (312, 314, 316), the number of multicast cells received by egress forwarders (322, 324, 326) from the ingress forwarders in the last bandwidth allocation period, and the bandwidth allocated to non-real time multicast flows from ingress forwarders (310, 312, 314, 316) to egress forwarders (320, 322, 324,326).

Abstract: In respective leaf tables (LT(1) to LT(m)) of a coupling management table (20), there are provided delete operation identifiers (D(1) to D(m)) indicating that leaf queues (LQ) respectively next to them toward the upstream direction are under delete operation. When one of the leaf queues (LQ(n)) should be deleted, if the leaf queue (LQ(n)) to be deleted stores any element, the delete operation identifier (D(n+1)) is set to 1. Thereby, the leaf table (LT(n−1)) can acknowledge that the leaf queue (LQ(n)) is currently under delete operation. Therefore, the coupled packet queue after deletion of the leaf queue and the coupling management table can be maintained consistent.

Abstract: Various aspects of an interactive multimedia system and associated methods. In general, the multimedia system employs central and peripheral hubs that function to provide services to a plurality of clients of a call manager server, or manager subsystem. The hubs and subsystem cooperate to serve requests originating in the plurality of clients. The client-server-client architecture allows for distributed processing and resource management. Redundant connections between the various network subsystems and hubs provide survivability. Each subsystem or hub is provided with the ability to initialize or recover from systemic errors, thereby distributing initialization and recovery. Certain of the distributed resources are capable of being managed from other subsystems, thereby allowing sharing of the resources. An open numbering plan allows efficient call treatment of dialed numbers. Call processing is sharable between multiple manager subsystems.

Abstract: An ATM cell buffer circuit including an output buffer type ATM switch for switching ATM cells and an input buffer unit provided for each line, read control means of the input buffer unit for reading a cell from a queue which temporarily stores an input cell and transmitting the same to the output buffer type ATM switch including a state control table, a delay quality class setting table for setting cell reading priority for each priority class assigned to an input cell, table value modifying means for modifying a set value of the delay quality class setting table as required and cell reading means for determining priority order to read a cell based on the delay quality class setting table and the state control table.

Abstract: A network switch for network communications includes a first data port interface supporting a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is configured to communicate with a CPU, and an internal memory communicates with the first data port interface and the second data port interface. A memory management unit is provided, including an external memory interface, for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, for communicating data and messaging information between the first data port interface, the second data port interface, the internal memory, and the memory management unit.

Abstract: Input buffer type packet switching equipment, which can output cells to an external output line having a slower output line rate than a corresponding input line rate without having buffers in its output line sections, is provided. The input buffer type packet switching equipment provides M input line buffers that store cells inputted from M input lines temporarily in a state that one of the M input line buffers stores cells inputted from corresponding one of the M input lines, in this the M is an integer being 2 or more, an M×N crossbar type switch, which provides N output lines, for switching cells outputted from the M input line buffers based on a cross point on/off control signal, in this N is an integer being 2 or more.

Abstract: For achieving elimination of unfairness between ports, reserved output port information transferred between respective modules is input to switch out of the module to vary destination of output. The module and the switch operate in synchronism with the frame for which the connection grant process of a plurality of time slot is performed to vary connection topology so that all connection topology appear. By variation of connection topology, variation combination of adjacent port appear to shuffle preference for the input port which is otherwise held fixed for resolving unfairness relating to reservation chance of the input port.

Abstract: A system and method for scheduling packet transmissions, whereby a Base Station System (BSS) part provides scheduling-related information to a Switching System (SS) part for scheduling of LLC frames, which includes information about the total number of packet data service radio links in the cell, and for each user, the bandwidth per link. Consequently, the SS can determine the required link utilization and hence the transmission time for each data packet the SS submits for transmission over the radio links. As such, the SS can control all end-to-end QoS quantities for each data packet, and how these quantities are affected by the SS scheduling of the LLC frames to the BSS. In this way, the SS can completely control how QoS agreements with users are met.

Abstract: The invention provides a method and system for combined unicast and multicast scheduling. Data cells are assigned at each input, to one unicast input queue for each output, or to a single multicast input queue. Each input makes two requests for scheduling to each output for which it has a queued data cell, one unicast request and one multicast request. Each output grants up to one request, choosing highest priority requests first, giving precedence to one such highest priority request using an output precedence pointer, either an individual output precedence pointer which is specific to that output for unicast data cells, or a group output precedence pointer which is generic to all outputs for multicast data cells. Each input accepts up to one grant for unicast data cells, or as many grants as possible for multicast data cells, choosing highest priority grants first, giving precedence to one such highest priority grant using an input precedence pointer.

Abstract: A network hub and Asynchronous Transfer Mode (ATM) translator system (5) for use in a Local Area Network (LAN)-based communications system is disclosed. The network hub and ATM translator system (5) includes a host controller (10) that serves as the LAN hub, and which interfaces with a translator card (15) which includes a segmentation and reassembly device (12) in connection with SONET receive/transmit circuitry (20) that communicates with a transceiver (22) to transmit and receive ATM packet cells over a communications facility (FO). The translator card (15) also includes a scheduler (14) that includes a heap sort state machine (36) which maintains a sorted list of entries, in a heap fashion, in on-chip parameter memory (44) and off-chip parameter memory (18). The entries include, for each ATM channel, a channel identifier and a timestamp that indicates the time at which the next cell for the channel will be due for transmission. A due comparator (40) compares the timestamp of the root value in the heap (i.

Abstract: In a network switch node, an asymmetric switch. The asymmetric switch comprises a plurality N of inputs each for coupling to a corresponding one of a plurality N of port modules and a plurality M of outputs each for coupling to one of the plurality of port modules. M is greater than N such that at least one of the plurality of port modules is coupled to more outputs than inputs. The asymmetric switch also includes a switching fabric operative to switch packets received from the inputs to the outputs. According to one embodiment, M=kN such that each port module can have one input line to the asymmetric switch and k output lines from the asymmetric switch. Such an asymmetric switch-to-port interface results in less blocking and allows output buffering wherein the output buffers are provided at the ports, rather than at the switch.

Abstract: An input-buffered multipoint switch having input channels and output channels includes multilevel request buffers, a data path multiplexer, and a scheduler. The switch has a distinct multilevel request buffer associated with each input channel and each request buffer has multiple request registers of a different request buffer priority. The request registers store data cell transfer requests that have been assigned quality of service (QoS) priorities, where the QoS priorities are related to packet source, destination, and/or application type. The multilevel request registers are linked in parallel to the scheduler to allow arbitration among requests of different input channels and different request buffer priority levels. The preferred arbitration process involves generating QoS priority-specific masks that reflect the output channels required by higher QoS priority requests and arbitrating among requests of the same QoS priority in QoS priority-specific multilevel schedulers.

Abstract: A method and apparatus for supplying new requests to a scheduler in an input-buffered multiport switch involve selecting a request that does not target output channels that conflict with output channels targeted by requests that are already accessible to the scheduler. Specifically, target output channels of requests that are presently accessible to the scheduler are identified and compared to target output channels of requests that are included in a queue of next-in-line requests. The queue of next-in-line requests is reviewed and the highest priority request having no conflicting output channels is supplied to the scheduler. By supplying the scheduler with a new request that targets non-conflicting output channels, the scheduler is presented with a wider range of requested output channels from which to choose in each arbitration cycle. In a first embodiment, one, two, or eight ports are connected to each one of four input/output controllers in a switch having a four-channel switch fabric.

Abstract: Cells are discarded in conformity with the order of priority when congestion occurs by discarding cells of a traffic class without any special contract for a transfer rate at the time of setting up a connection. A node stores priority information concerning cell discard corresponding to a connection identifier and controls the cell discard in accordance with the discard condition determined by the accumulated number of cells for each connection in the node and cell priority.

Abstract: An optimal multiplexing method is disclosed which allows buffers to be two packets in depth. For a plurality of buffers, with each buffer associated with a packetized data stream, packets are received at respective buffer input rates. The buffers are serviced at a service rate at least equal to a sum of the buffer input rates. For each buffer, once a full packet has been received therein, a time interval until that buffer is expected to reach its buffer depth is determined. The buffer having the least time interval is then serviced first, such that overflow of the buffers is avoided.

Abstract: Techniques of service-rate controls in ATM switches are described, and apparatus for their implementation are devised. The techniques fall in two categories: frequency domain controls, and time-domain controls. The regulators control the service rate on a per-class basis or on a per-connection basis. Some class regulators operate at very high speeds of the order of several gigabits per second and cover a medium number of classes, 32 for example. Other regulators operate at high speeds of the order of several-hundred megabits per second, and cover a very large number of classes, e.g., 10000. A compound regulator which combines both types of regulators is also described. The compound regulators extend the range of controllable classes considerably, covering some 200,000 classes. The main advantages of the regulators of the invention are simplicity, robustness, and high performance.

Abstract: An input-buffered multipoint switch having input channels and output channels includes multi-level request buffers, a data path multiplexer, and a scheduler. The switch has a distinct multi-level request buffer associated with each input channel and each request buffer has multiple request registers for storing data cell transfer requests of different priorities. The multi-level request registers are linked in parallel to the scheduler to allow arbitration among requests of different input channels and different priority levels. The preferred arbitration process involves generating masks that reflect the output channels required by the same priority level requests. Utilizing masks to arbitrate between multiple requests in an input-buffered switch reduces arbitration cycle time and minimizes HOL blocking.

Abstract: A technique, specifically apparatus and accompanying methods, which utilizes a trie-indexed hierarchy forest ("rhizome") that accommodates wildcards for retrieving, given a specific input key, a pattern stored in the forest that is identical to or subsumes the key. The rhizome contains a binary search trie and a hierarchy forest. The search trie provides an indexed path to each unique, most specific, pattern stored in a lowest level of the hierarchy forest and also possibly to increasingly general patterns at higher levels in the pattern hierarchy. The hierarchy forest organizes the patterns into nodal hierarchies of strictly increasing generality. For use as a packet classifier, the rhizome stores wildcard-based packet classification patterns at separate corresponding pattern nodes, along with, corresponding "reference" fields associated therewith. Operationally, as each different queue is established or removed, a corresponding classification pattern is either inserted into or removed from the rhizome.

Abstract: For controlling the data traffic in an ATM network, in which a number of nodes are connected via a closed loop, and in which each node may be equipped with a number of access ports for sending and receiving ATM cells, the ATM cells are processed separately in each node based upon their assignment to a QoS (quality of service) class in a predefined QoS classification. In each access port, each QoS class is assigned a separate queue. The data traffic in the closed loop is monitored separately, based upon QoS class, by a cell monitor. If a performance characteristic of a QoS class is not fulfilled in the closed loop, then at least one back-pressure signal will be generated, which will serve to suppress at least one assigned queue of the access port. The monitoring of the data traffic can be implemented via a leaky-bucket system.

Abstract: A switch system and method transfer a data packet from a source data port to one or more destination data ports through a switch. The system comprises a source input buffer, a first and a second source input path, a first and a second output path and at least one crosspoint circuit. The source input buffer includes a first and a second data section. The first and the second data sections are coupled to the first and the second input paths respectively. The first and the second input paths couple through the crosspoint circuits at each intersection with the first and the second output paths. The method includes loading the data packets into data sections of an input buffer, transferring each data packet across an input path dedicated for each data section, transmitting each data packet over its input path, and switching the data from the input path to the output path based on a voltage differential.

Abstract: A system and method are provided for routing received cells through a switch fabric. A plurality of output channels are organized into a plurality of channel groups, wherein each of the channels groups is associated with one or more unique output ports of a Benes network. A plurality of cells destined to one or more of the plurality of channel groups is received at plural input queues. A different output port of the Benes network is selected for one or more of the input queues that contains a cell. Then, one cell is switched from each of one or more input queues through the Benes network to the respective selected output port.

Abstract: A cell scheduler for a distributed shared memory switch architecture including a controller for scheduling transmissions of cells from output queues of the switch structure pursuant to one of several different scheduling modes. The controller receives a mode selection input, segregates the output queues into groups, assigns priority rankings to the groups, and applies one of scheduling disciplines at each group of output queues as determined by the mode selection input and the priority rankings. The groups of output queues include a group of per-Virtual Channel (VC) queues and at least one group of First In-First Out (FIFO) queues. The scheduling disciplines include a Weighted Fair Queuing (WFQ) scheduling discipline applied by the controller at the group of per-VC queues and a Round Robin (RR) scheduling discipline applied by the controller at the at least one group of FIFO queues. The priority rankings comprising a highest priority ranking which is assigned to the group of per-VC queues.

Abstract: A contention control circuit which temporarily stores cells arriving from a respective plurality of input lines to output cells to a single output line without collisions. The contention control circuit compares, at each input line in turn, the priority of the cell that has arrived from that input line, with the priority of the cell selected from among the cells that have arrived from preceding input lines as the cell having the highest priority, and again selects the cell with the higher priority.

Abstract: An asynchronous mode transfer (ATM) switch conducting switching based upon the calculation of weights for entries corresponding to cells in an input queue to achieve a high throughput rate which avoids head of line blocking. The switch includes a cell scheduler driven by the iterative resolution of a traffic matrix formed by highest priority entries for each of a plurality of output ports queued in each of a plurality input queues each having separate virtual queues corresponding to the output ports. Conflicts in the matrix are resolved according to weight so that one entry per one row is chosen to be transmitted in parallel. Selection of winning entries from among a group of conflicting entries during any step are resolved by selecting the heaviest weighted entry and leaving the remaining ports maximum satisfactory transmission opportunities.

Abstract: A traffic shaper apparatus includes a ring memory, a counter, a schedule circuit, first-priority available area determining circuits, and a storage area determining circuit. The ring memory has a plurality of storage areas for storing cells to be transmitted to an asynchronous transfer mode (ATM) communication network. The counter performs read control of cells at a predetermined read rate by cyclically accessing the storage areas in the ring memory. The schedule circuit obtains an ideal transmission time of a cell to be transmitted to the ATM communication network in accordance with input of a cell. The first-priority available area determining circuits are arranged in correspondence with a plurality of sectors obtained by grouping the storage areas in the ring memory to concurrently search for available storage areas in the respective sectors from which cells are read out at times nearest the ideal transmission time.

Abstract: An explicit rate algorithm is disclosed for use in an end-to-end closed loop flow control algorithm for an ATM network which carries at least constant bit rate (CBR) traffic, variable bit rate (VBR) traffic and adjustable bit rate (ABR) traffic. The algorithm determines how much additional bandwidth is available for ABR traffic on an output link from a node and produces an explicit rate variable that can be forwarded to a source for the ABR traffic. Both the maximum and minimum bandwidths already reserved for all connections on the output link are determined. A single reserved bandwidth value is chosen within the range defined by the maximum and minimum reserved bandwidth values. The current utilization of the ABR input buffer for the node is also determined. The explicit rate variable is generated as a function of the link capacity, the reserved bandwidth value and the current utilization of the ABR input buffer.

Abstract: A multi-stage ATM switch has a plurality of inlet stage fabrics, core stage fabrics and outlet stage fabrics. ATM cells routed by the switch have destination fields including (i) an identification of the outlet stage fabric and (ii) an identification of the outlet port. Cells incoming to a given inlet stage fabric are queued up in queues representing each of the outlet stage fabrics. A queue having at least the number of cells as there are core stage fabrics (or one having a lesser number of cells where cells have been waiting longer than an a pre-defined time) is identified and, in a time slot, cells are transmitted from the front of the identified queue, in parallel, one to each of the core stage fabrics (with blank make-up cells being sent, as necessary, where the identified queue had less cells than there are core stage fabrics).

Abstract: A network-to-CPU interface circuit interfaces an isochronous physical layer to an ISA bus such that a host CPU connected to the ISA bus can communicate with the isochronous physical layer. Inbound B-channel interface circuity is connectable to receive, from the isochronous physical layer, an inbound data stream which includes a plurality of B-channels time division multiplexed into time division multiplexed (TDM) frames. The TDM frames have a predetermined format that defines at least one logical stream such that each logical stream comprises those B-channels that are time division multiplexed into corresponding predetermined locations within the TDM frames. An inbound buffer portion of a memory is provided to hold the received inbound data stream, and an outbound buffer portion of the memory is provided for holding an outbound data stream which, like the inbound data stream, includes a plurality of B-channels time division multiplexed into time division multiplexed (TDM) frames.

Abstract: An plesioasynchronous and asynchronous router circuit communicates with neighboring router circuits and nodes. Each of the router circuits includes a plurality of input ports for receiving frames of data and a plurality of output ports for transmitting frames of data. Each router circuit further includes a plurality of input buffers for storing frames of data received at an input port, and an arbiter system for choosing one of several input buffers associated with a particular one of said output ports. The arbiter system includes a plurality of arbiter subsystems associated with corresponding ones of said plurality of output ports. The plesioasynchronous and asynchronous router circuit further includes a crossbar switch for connecting an arbiter selected input buffer with a particular one of said output ports.

Abstract: A regulation apparatus for ATM cell delay variation includes a variation regulating buffer for temporarily storing cells transferred thereto, a variation waiting timer for controlling a waiting time which extends from reception of the first cell to read-out of cells from the buffer, a read-out timer for controlling intervals at which cells are read from the buffer, a latest cell preservation memory for storing the latest cell transferred from a VPI/VCI demultiplexing unit and, a selector for selecting a cell stored in the buffer or in the memory to transfer the selected cell to a cell reproduction unit.

Abstract: Data communication stations 10, 12, 14 are connected by way of a shared bus 15 common to all the communication stations. When two stations attempt to access the shared bus simultaneously, a conflict resolution method if used to determine which of the two stations is allowed access to the bus 15. Each station seeking access to the bus 15 serially transmits its address. The priority of the stations is determined, and the station with priority is given access to the bus 15.

Abstract: A switch for digital communication networks includes a queuing system cape of implementing a broad class of scheduling algorithms for many different applications and purposes, with the queuing system including both a tag-based primary queue which contain ATM cells organized by priority and a secondary queue which contains ATM cells which are not yet scheduled for transmission and which are organized by virtual channel. A queuing decision module is provided to determine in which queue an incoming ATM cell should be deposited. A requeuing module operates when an event occurs that unblocks a particular virtual channel. The requeuing module, on occurrence of such an event, accesses the secondary queue to obtain another cell, to assign it priority and to move it to the primary queue. The queuing decision module, along with a virtual channel table, can be used easily to block virtual channels when necessary. The combination of queues also allows for round robin scheduling.

Abstract: The ATM communication equipment (KE) serves the purpose of forwarding message cells supplied via at least one offering trunk (E1, . . . , En) during to course of virtual connections with a serving trunk arrangement (A1, . . . , An) coming into consideration for the respective virtual connection. Characteristic parameters as well as at least two different priorities are thereby defined for the respective virtual connection during the course of the call set up. The respective serving trunk arrangement has a handling device (BHE) allocated to it that has a central cell memory (CM) in which call-associated cell waiting lists are established for storing message cells. A control device (STE) in which an allocation table (LUT) is kept is connected to the cell memory. This allocation table allocates a waiting list identifier as well as a priority identifier to the call information (VPA/VCI) carried in the message cells.

Abstract: A bandwidth allocation system allows packets or cells within traffic flows from different sources contending for access to a shared processing fabric to get access to that fabric in an order that is determined primarily on individual guaranteed bandwidth requirements associated with each traffic flow, and secondarily on overall system criteria, such as a time of arrival, or due date of packets or cells within traffic flows.

Abstract: A telecommunications network (10) includes a plurality of transport node controllers (18) that interface with a plurality of local communication processors (16) for the transfer of telecommunications information between subscribers (14) associated with the local communication processors (16) and also for subscribers remote from the transport node controller (18). The transport node controller (18) includes a buffer memory (24) with a pool of buffers (26). A local processor controller (22), in conjunction with a remote processor (20), allocate the buffers (26) within the buffer memory (24) among the plurality of local communication processors (16) and remote communication processors communicating to the transport node controller (18) through a message transporting network (12). The local processor controller (22) assigns a buffer (26) to each of the plurality of local communication processors (16).

Abstract: An ATM network including a plurality of channels comprises a cell memory MC comprising r buffers for virtual circuits (MC1, . . . , MC2). The output cells of MC carried by a multiplex DNO are read by a readout address section circuit. The circuit also comprises a mechanism for establishing a one-to-one relationship between each activated channel and a predetermined level of priority, a rhythm synthesis table, a mechanism dependent on the output of the rhythm table for activating pulse signals which have frequencies that correspond to the data rates of activated channels, an automatic timing unit and a mechanism for selecting a channel of highest priority at each cell time.