Abstract: A communications system receives a modulated signal that carries encoded communications data. An adaptive filter has a plurality of non-adaptive and adaptive filter taps with weighted coefficients and a tap order selection circuit for selecting the number and order of adaptive filter taps based on one of at least measured output power from the adaptive filter and signal modulation. A demodulator and decoder receives the filtered output signal and demodulates and decodes the signal to obtain the communications data.

Abstract: A receiver is provided for a quadrature-modulated signal, which can be divided into an inphase signal and a quadrature signal. The inphase signal is fed to first and third equalizers, and the quadrature signal is fed to second and fourth equalizers, wherein the first and second equalizers each perform a first equalization of the respective signal. An output of the first equalizer is connected to a second input of the fourth equalizer, which, by means of a second equalization of the quadrature signal, transmits an equalized quadrature signal as a function of the previously fed equalized inphase signal of the first equalizer. An output of the second equalizer is connected to the second input of the third equalizer, which, through a second equalization of the inphase signal, transmits an equalized inphase signal as a function of the previously fed equalized quadrature signal of the second equalizer.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: An apparatus and method for mitigation of receive power imbalance including estimating input power levels on two diversity receive branches in a receiver; computing a power imbalance between the two diversity receive branches and determining a weaker receive branch; setting a weakRX parameter based on the weaker receive branch; computing an intercept parameter c0 for a switching curve based on the weakRX parameter; computing a threshold T based on the intercept parameter; and determining a switching decision for the receiver based on the threshold T.

Abstract: A system and apparatus for compensating cable losses in a video signal transmission system includes feedback circuits to determine the spectral attenuation of a received signal and to control an equalizer circuit to amplify selected frequencies of the received signal, and to determine the various times of arrival of two or more video signals and selectively adjust one or more delay lines to reduce the differences in their arrival times.

Abstract: A data processing apparatus communicates data bits on a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processing apparatus comprises a parity interleaver operable to perform parity interleaving on Low Density Parity Check (LDPC) encoded data bits obtained by performing LDPC encoding according to a parity check matrix of an LDPC code including a parity matrix corresponding to parity bits of the LDPC code, the parity matrix having a stepwise structure, so that a parity bit of the LDPC encoded data bits is interleaved to a different parity bit position. A mapping unit maps the parity interleaved bits onto data symbols corresponding to modulation symbols of a modulation scheme of the OFDM sub-carrier signals.

Abstract: A data processing apparatus is arranged to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols are divided into first sets of input data symbols and second sets of input data symbols. The data processing apparatus comprises an interleaver operable to perform an odd interleaving process which interleaves the first sets of input data symbols on to the sub-carrier signals of first OFDM symbols and an even interleaving process which interleaves the second sets of input data symbols on to the sub-carrier signals of second OFDM symbols.

Abstract: A method for communication includes receiving signals at a receiver from one or more sources, including a target signal transmitted by a given transmitter. A channel response is estimated from the given transmitter to the receiver, and a filter response is computed by taking a sum of an autocorrelation of the received signals with an adaptive noise factor, and applying the sum to the estimated channel response. The filter response is applied to the received signals in order to recover the target signal.

Abstract: A data processing apparatus to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of Orthogonal Frequency Division Multiplexed OFDM symbols. The predetermined number of sub-carrier signals is determined in accordance with one of a plurality of operating modes and the input data symbols include first sets of data symbols and second sets of input data symbols. The data processing apparatus includes a controller, an address generator, and an interleaver memory. The controller is configured, when operating in accordance with an even interleaving process, to read out a first set of the input data symbols from the interleaver memory on to the sub-carrier signals of an even OFDM symbol using read addresses generated by the address generator, and to write in a second set of the input data symbols into the interleaver memory using the addresses generated by the address generator.

Abstract: A method, and circuitry, for choosing the correct equalization curve in adaptive equalization uses a feedback loop in which the incoming high-speed serial data are digitized and deserialized for use in the remainder of the device, and also are used by an adaptive state machine to both extract the reference levels for digitization and to control the equalization curve. Detection of the reference level and selection of the equalization curve may be performed at a different rates to avoid interfering with one another. The state machine preferably is programmable. This is useful in any device, but is particularly well-suited for a programmable device, such as a PLD or other programmable integrated circuit device, where conditions may vary according a user logic design.

Abstract: A method for modulating a sequence of data symbols such that the transmit signal exhibits spectral redundancy. Null symbols are inserted in the sequence of data symbols such that a specified pattern of K data symbols and N?K null symbols is formed in every period of N symbols in the modulated sequence, N and K being positive integers and K being smaller than N.

Abstract: A data processing apparatus to map input data symbols to be communicated onto sub-carrier signals of Orthogonal Frequency Division Multiplexed (OFDM) symbols. The number of sub-carrier signals available from each of the OFDM symbols being variable between OFDM symbols and the input data symbols include first sets of data symbols and second sets of input data symbols. The data processing apparatus includes a controller, an address generator, and an interleaver memory. The controller is configured, when operating in accordance with an even interleaving process to read out a first set of the input data symbols from the interleaver memory on to the sub-carrier signals of an even OFDM symbol using read addresses generated by the address generator, and to write in a second set of the input data symbols into the interleaver memory using the addresses generated by the address generator.

Abstract: A data processor maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: An equalizing filter circuit includes a first transmission line in which a plurality of first delay devices 104a are connected in cascade to input terminal 101, a second transmission line in which a plurality of second delay devices 107a are connected in cascade to output terminal 102, a plurality of weighting circuits 105a connected in parallel between the first transmission line and the second transmission line and having a gain which is adjustable by setting coefficients, and variable adjusting circuit 108a arranged at the output side of at least one of weighting circuits 105a for correcting a fluctuation of the output characteristics of the weighting circuits.

Abstract: A transmitter has a transmission modulator including first and second modulators, a phase comparator and a controller. First and second non-inverted local signals supplied to the modulators are set to have a predetermined phase difference. In a calibration action for reducing carrier leakage, the phase comparator is supplied with the first or second local signals, and carrier signals leaking at an output of the transmission modulator. The controller keeps changing the ratio of DC biasing currents to paired transistors of each modulator until the predetermined phase difference is detected with the phase comparator. When the predetermined phase difference is detected, the controller stops changing the ratio of DC biasing currents. The chip footprint of a transmitter on the direct up-conversion (DUC) architecture is reduced, and carrier leakage owing to local signals supplied to the transmission modulator are decreased.

Abstract: An apparatus is disclosed to compensate for non-linear effects resulting from the transmitter, the receiver, and/or the communication channel in a communication system. A receiver of the communication system contains an image cancellation module that compensates for images generated during the modulation and/or demodulation process. The image cancellation module includes a fine carrier correction loop to correct for frequency offsets between the transmitter and receiver. The image cancellation module includes a coarse acquisition mode and a decision directed mode. The decision directed mode allows for a larger signal-to-noise ratio for the receiver when compared against the coarse acquisition mode.

Abstract: A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.

Abstract: An adaptive cable equalizer includes a data signal input unit, a clock signal input unit, a variable equalizer that inputs a data signal input from the data signal input unit, and a transition time measuring portion that measures a transition time of a data signal output from the variable equalizer, with an equalizer control loop being configured that controls characteristics of the variable equalizer based on the output signal of the transition time measuring portion. The adaptive cable equalizer further includes a control circuit that controls response characteristics of the control loop according to the frequency of a clock signal input from the clock signal input unit. This enables a quick response at fast transfer rates by making the relationship between the response time of the control loop and the number of data bits substantially constant even when the transfer rate changes from a slow transfer rate to a fast transfer rate.

Abstract: An enhancement system extracts pitch from a processed speech signal. The system estimates the pitch of voiced speech by deriving filter coefficients of an adaptive filter and using the obtained filter coefficients to derive pitch. The pitch estimation may be enhanced by using various techniques to condition the input speech signal, such as spectral modification of the background noise and the speech signal, and/or reduction of the tonal noise from the speech signal.

Abstract: A semiconductor integrated circuit equipped with an equalizer which has a circuit structure simpler than that of a related equalizer according to an FFE scheme or a DFE scheme and is capable of preventing a noise component from being amplified. The data receiver includes a plurality of receiver units, wherein each receiver unit includes a plurality of level detectors which detect different levels, and an encoder, in which the level detectors receive data according to a clock signal having a predetermined phase difference and perform an amplification operation including an equalization function based on feedback data, thereby outputting an amplification signal, and wherein level detectors of one receiver unit receive an amplification signal, as the feedback data, from level detectors of another receiver unit that receives a first clock signal having a phase more advanced than a phase of a second clock signal received in one receiver unit.

Abstract: A signal processing apparatus includes at least one equalization section, each of the equalization section being capable of setting a center frequency, a gain value at the center frequency, and a Q value and allowing set frequency-amplitude characteristics to be applied to an input signal; and a computation section. The computation section performs a center frequency determination process for computing, for target characteristics of the equalization section, a difference from the target characteristics for each area divided by a frequency portion where the gain of the characteristics of the equalization section is small and a frequency portion where the gain of the characteristics of the equalization section is large, a gain value determination process for determining the gain value at the center frequency of the equalization section, and a Q value determination process for setting the determined center frequency and the determined gain value.

Abstract: A receiving method according to the present invention adjusts a level of an output voltage signal by switching a gain to be used for converting an inputted current signal to a voltage signal, in a preamplifier. Performing offset compensation on the output voltage signal in an offset compensator, in a post amplifier. Adding a reset signal, whose polarity is made opposite to a polarity of the output voltage signal, to the output voltage signal, in the preamplifier. Detecting the reset signal having added to the output voltage signal, and resetting the offset compensator by use of the detected reset signal, in the post amplifier.

Abstract: A likelihood value calculation device includes: likelihood value calculation unit 201 that takes as input an equalization signal of a modulated signal, that, in accordance with a first control signal, calculates from the equalization signal that was received as input a provisional likelihood value for which the bit value of each signal point is “0” for each bit position; arithmetic inversion unit 202 that, in accordance with a second control signal, supplies for each bit position a provisional likelihood value without alteration that was supplied from likelihood value calculation unit 201 or subjects the provisional likelihood value that was supplied from likelihood value calculation unit 201 to arithmetic inversion and supplies the likelihood value following inversion; and operation control unit 200 that holds, for each combination of a radio mode and modulation mode, a control pattern that is used to control the operations of at least likelihood value calculation unit 201 and arithmetic inversion unit 202 a

Abstract: A reconfigurable chip level equalizer having circuitry that restores signal orthogonality and eliminates channel interference for a wireless transmitted signal. In at least some embodiments, the reconfigurable chip level equalizer comprises two or more adaptive equalizers, a plurality of operational blocks that interconnect the two or more adaptive equalizers, and a control mechanism that configures the two or more adaptive equalizers and operational blocks according to different signal delay profiles.

Abstract: In one embodiment, a demapper uses two hybrid-QPSK constellations to demap pairs of equalized data symbols recovered from 16-QAM, DCM OFDM symbols, wherein the equalized data symbols in a pair correspond to the same four-bit group. A first hybrid-QPSK constellation is generated by combining the real components of both 16-QAM mapping constellations onto one coordinate plane. The demapper generates a first set of two decision variables by combining the real components of each equalized data symbol in a pair to correspond to the first hybrid-QPSK coordinate plane. A log-likelihood ratio is then calculated for both decision variables in the set to determine likelihood estimates for the first and second bits of the four-bit group. This process is repeated for the imaginary components of each corresponding pair of equalized data symbols to generate likelihood estimates for the third and fourth bits of the four-bit group.

Abstract: A digital communications receiver includes an input configured to receive, via a communications channel, a received first signal representing a sequence of symbols, each symbol being encoded to be representative of a plurality of data bits. A processor adjusts a magnitude and filters the received signal. An equalizer applies a cyclic prefix restoration to the adjusted and filtered signal, producing a second signal, converts the second signal from time domain to frequency domain to produce a frequency domain signal, and determines a first quantity of values representing a first portion of the symbols by evaluating a relationship of channel values representing characteristics of the communications channel and a second quantity of values representing a portion of the frequency domain signal, the first quantity being smaller than the second quantity.

Abstract: Apparatus, and an associated method, for the receive part of a receiving station, such as a mobile station or other transceiver of a cellular communication system. Selection is made of filter characteristics to be exhibited by an adaptive, input noise whitening filter. A noise estimator estimates a noise component of a noise sequence. An autocorrelation estimator estimates the noise-component autocorrelation. A determination is made as to whether the autocorrelation exceeds a threshold. If so, filter characteristics are selected to cause the input noise whitening filter to operate to inject whitening noise into the received sequence.

Abstract: A communications system receives a modulated communication signal that carries encoded communications data. A signal input receives the communication signal. An adaptive filter circuit is connected to the signal input and comprises N number of parallel adaptive filters. Each adaptive filter has non-adaptive and adaptive taps with weighted coefficients that are different in number from the respective other parallel adaptive filters within the adaptive filter circuit. A selection output circuit is connected to each adaptive filter and selects for output the adaptive filter having the most suppression or least output power or other criterion which can indicate a best choice to use of the N parallel adaptive filters. A demodulator demodulates the signal and a decoder receives the filtered output signal from the demodulator and decodes the signal to obtain the communications data.

Abstract: A method for adaptive selection of floating taps in a decision feedback equalizer including the steps of (A) determining values for a predefined metric for tap positions within a range covered by a decision feedback equalizer (DFE) and (B) setting one or more floating taps of the DFE to tap positions based upon the values of the predefined metric.

Abstract: In time varying OFDM systems, the effect of a non-ideal time synchronization may lead to a poor performance in terms of decoded average bit error rate versus the signal-to-noise ratio. The receiver apparatus (3) of the transmission system (1) estimates a subcarrier-dependent channel frequency response and determines an intercarrier interference spreading on the basis of a cyclic shift in symbols carried by the subcarriers. Therewith, an intercarrier interference included in an OFDM signal can be canceled, even in case of a non-ideal time synchronization.

Abstract: A signal level adjusting device (AD), for RF communication equipment arranged to received primary RF signals, comprises i) a tuner (TU) comprising a gain control means (SI,R), arranged to define a first or second digital command signal respectively each time it receives a first or second digital control signal respectively, and a gain adjusting means (VGA) arranged to decrease or increase respectively its gain by a fixed value when the command signal defined by the gain control means (SI,R) is a first or second command signal respectively, in order to adjust the level of the received primary RF signals, and ii) a demodulator (DEM) comprising a level control means (LCM1) arranged to generate a first or second digital control signal respectively each time it detects an increase or decrease respectively of the level of secondary signals representative of the adjusted signals output by the tuner (TU).

Abstract: The invention is related to a communication terminal, comprising: means (618) for creating at least one channel matrix assuming predetermined interfering signals as a part of a desired signal; means (618) for dividing the at least one channel matrix into multiple sub-matrices; means (618) for diagonalizing the sub-matrices by using a transformation matrix; means (618) for forming at least one block-diagonalized matrix using diagonalized sub-matrices; means (618) for inverting the at least one block-diagonalized matrix; and means (618) for generating channel equalizer coefficients by using at least one inverted block-diagonalized matrix.

Abstract: The present invention provides a cost-effective TEQ hardware architecture to support multiple VDSL2 profiles. It supports variable TEQ tap length programmable through firmware. Larger TEQ tap length at low-speed profiles is supported by the unique design without adding additional multipliers. The maximum number of TEQ taps supported is actually inversely proportional to the profile frequency. This perfectly meets the requirement to have longer TEQ for low-speed profile and shorter TEQ for high-speed profile.

Abstract: Techniques to facilitate estimating the frequency response of a wireless channel in an OFDM system are provided. The method and systems allow for combining signal information across multiple communication channels at one or more channel tap delays in order to determine appropriate taps for channel information.

Abstract: A communications system receives a modulated signal that carries encoded communications data. An adaptive filter circuit has a plurality of adaptive filters each having a plurality of non-adaptive and adaptive filter taps with weighted coefficients. At a selected adaptive filter, an interference reduction circuit is responsive to one of at least a received state of a demodulator, the type of modulation used by communication system and the input and output power of adaptive filter for updating the adaptive gain of the adaptive filter, selecting the number and order of adaptive filter taps, separating the spacing of multipath introduced by adaptive filter, controlling input and output normalizing circuits to adaptive filter(s) and selecting if signal passed to demodulator is original received signal or signal output by adaptive filter. A demodulator and decoder receive the filtered output signal and demodulate and decode the signal to obtain the communications data.

Abstract: Receiving a transmission line estimation sequence, a wireless communication apparatus generates a transmission line characteristic estimation value for each of a plurality of sub-carriers and smoothes the transmission line characteristic estimation value of a target sub-carrier to be processed and the transmission line characteristic estimation value of its adjacent sub-carrier. The apparatus includes a determination unit for determining whether or not the adjacent sub-carrier, is a null sub-carrier and a smoothing unit for smoothing the transmission line characteristic estimation value of the target sub-carrier by excluding the transmission line characteristic estimation value of the adjacent sub-carrier determined as a null carrier by the determination unit.

Abstract: Methods and apparatus are provided for determining receiver filter coefficients for a plurality of phases. One or more coefficients for a receiver filter are determined by determining a first coefficient for a first phase of a data eye; and determining a second coefficient for a second phase of the data eye. The receiver filter may be, for example, a decision-feedback equalizer. The first and second coefficients may be determined by performing an LMS adaptation of decision-feedback equalization coefficients. In another embodiment, the first and second coefficients may be determined by obtaining eye opening metrics from a data eye monitor corresponding to each of the respective first phase and the second phase; and determining the respective first and second coefficients based on the eye opening metrics. The first and second phases can correspond to odd and even phases.

Abstract: A multi-input multi-output (MIMO) radio communication apparatus and method are provided. The MIMO apparatus includes a plurality of reception antennas each having a plurality of antenna patterns; a channel matrix estimation unit for estimating a channel matrix between a plurality of transmission antennas and the plurality of reception antennas; a channel capacity calculation unit for calculating a channel capacity corresponding to a combination of antenna patterns of the plurality of reception antennas by using the estimated channel matrix; and an antenna pattern control unit for changing the antenna patterns of the plurality of reception antennas to maximize the channel capacity. According to the MIMO radio communication apparatus and method, direction can be controlled adaptively to a propagation environment.

Abstract: Decision feedback equalization (DFE) circuits are disclosed for use with fractional-rate clocks of lesser frequency than the data signal. For example, a one-half-rate clocked DFE circuit utilizes two input data paths, which are respectively activated on rising and falling edges of an associated half-rate clock. Each of the input data paths has a pair of comparators with differing reference voltage levels. The comparators in each input data path output to a multiplexer, which picks between the two comparator outputs depending on the logic level of the previously received bit. The output of each input data path is sent as a control input to the multiplexer of the other data path. Thus, the results from previously-detected bits affect which comparator's output is passed to the output of the circuit, even though the synchronizing clock is half the frequency of the data. A quarter-rate DFE circuit is also disclosed which operates similarly.

Abstract: An apparatus generally having a first circuit and a second circuit. The first circuit may be configured to (i) generate an equalizer parameter in response to an input signal, the equalizer parameter causing a cancellation of post-cursor inter-symbol interference from a plurality of symbols in the input signal and (ii) generate an output signal in response to both the input signal and the equalizer parameter. The second circuit may be configured to (i) generate a target parameter signal in response to the input signal, the target parameter signal representing a mean value of a plurality of sample points of the symbols and (ii) generate a control signal in response to the target parameter signal, the control signal causing a reduction of the equalizer parameter, the reduction causing a decrease in the cancellation of the post-cursor inter-symbol interference from the symbols, wherein the apparatus does not cancel pre-cursor inter-symbol interference.

Abstract: A communications system receives a modulated signal that carries encoded communications data. An adaptive filter has a plurality of non-adaptive and adaptive filter taps with weighted coefficients and a input and output normalizing circuit that obtain sample values from a received signal input to or output from the adaptive filter to increase gain recovery based on type of modulation of encoded communication data, on state of demodulator (preamble search, preamble detected, data state) or other signal acquisition information. A demodulator and decoder receive the filtered output signal and demodulate and decode the signal to obtain the communications data.

Abstract: A communications system receives a modulated signal that carries encoded communications data. An adaptive filter has a plurality of non-adaptive and adaptive filter taps with weighted coefficients and an adaptive gain circuit for updating the adaptive gain of the adaptive filter responsive to a received state of a modem or the type of modulation used by communications system. A demodulator and decoder receive the filtered output signal from the adaptive filter and demodulate and decode the signal to obtain the communications data.

Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.

Abstract: In various embodiments, a first and second complex multiplier may be configured to receive an input signal and provide a baseband I component signal and a baseband Q component signal, respectively. A first and second filter may be configured to filter the baseband I component signal and the baseband Q component signal, respectively. An equalizer may be configured to equalize the filtered baseband I component signal and the filtered baseband Q component signal. A carrier recovery portion may be configured to generate a reference signal based on the equalized filtered baseband I component signal and the equalized filtered baseband Q component signal. A first and second multilevel comparator may be configured to receive the equalized filtered baseband I component signal from the carrier recovery portion and provide an output I and receive the equalized filtered baseband Q component signal and provide an output Q signal for further modulation.

Abstract: A decision feedback equalizer (DFE) and method including a branch coupled to an input and including a sample-and-hold element configured to receive and sample a received input signal from the input and a current-integrating summer. The current-integrating summer is coupled to an output of the sample-and-hold element. The summer is configured to receive and sum currents representing at least one previous decision and an input sample. The at least one previous decision and the input sample are integrated onto a node, wherein the input sample is held constant during an integration period, thereby mitigating the effects of input transitions on an output of the summer.

Abstract: Methods and systems for a quadrature local oscillator generator utilizing a DDFS for extremely high frequencies. Aspects of one method may include utilizing the DDFS to generate a first signal that may comprise an in-phase (I) component and a quadrature phase (Q) component. A base signal may be divided to generate a second signal with an in-phase (I) component and a quadrature phase (Q) component. The I and Q components of the first and second signals may be mixed by a plurality of mixers, and the outputs of the mixers may be combined to generate an in-phase component of a local oscillator signal and a quadrature phase component of the local oscillator signal. The frequency of the local oscillator signal may be controlled by inverting or not inverting outputs of one or more of the mixers.

Abstract: A communications device includes a signal input for receiving both wideband and in-band, narrowband communication signals having wideband communications data that is transmitted over a wideband communications channel and narrowband communications data that is transmitted within an in-band, narrowband channels over the same wideband communications channel. A circuit splits the communications signals into a wideband signal channel and narrowband signal channels. A narrowband filter within the wideband signal channel filters the wideband communications signal and removes any narrowband communications signals. A demodulator within the wideband signal channel demodulates the filtered wideband communications signal to obtain any wideband communications data. An in-band, narrowband demodulators are positioned within the narrowband signal channels and demodulate the narrowband communications signals to obtain any narrowband communications data.

Abstract: A system and method of adapting a FIR filter with a mixed minimum-mean-square-error/zero-forcing adaptation is disclosed. A channel response module attempts to approximate a noiseless component of the channel response. The output of the channel response module is utilized to adapt a FIR filter module. In some embodiments, a combination of the output of the channel module and the noiseless channel output is utilized to adapt the FIR filter. In some embodiments, a second FIR filter module is utilized to process the noiseless channel output, which is then compared to the target response to generate an error signal, which may be used to adapt both the first and second FIR filter modules.

Abstract: A search engine selects initial coefficients for a receive equalizer. The search engine may be incorporated into a communication receiver that includes a decision feedback equalizer and clock and data recovery circuit. Here, the search engine may initialize various adaptation loops that may control the operation of, for example, a decision feedback equalizer, a clock and data recovery circuit and a continuous time filter. The receiver may include an analog-to-digital converter that is used to generate soft decision data for some of the adaptation loops.