Abstract: A method which includes steps of providing a state space model of behaviour of a physical system, the model including covariances for state transition and measurement errors, providing a data based regression model for prediction of state variables of the physical system, observing a state vector comprising state variables of the physical system, determining a prediction vector of state variables based on the state vector, using the regression model, and combining information from the state space model with predictions from the regression model through a Bayesian filter, is provided.

Abstract: A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original data signal and outputs a first data signal, the Nth stage LED driver receives a (N?1)th data signal and outputs a Nth data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to the (N?1)th data signal; and a first transmitter outputting the Nth data signal according to the recovery clock signal and the recovery data signal.

Abstract: A decision feedback equalizer includes: a feedforward equalizer, a feedback equalizer, a slicer and a decision adjustment unit. The feedforward equalizer is arranged to generate a feedforward output signal based on an input signal. The feedback equalizer is coupled to the feedforward equalizer and arranged to generate a feedback output signal according to a decision output signal. The slicer is coupled to the feedforward equalizer and the feedback equalizer, and is controllable by a decision adjustment parameter, wherein the slicer is arranged to perform a slicer decision on a sum of the feedforward output signal and the feedback output signal, thereby generating the decision output signal. The decision adjustment unit is coupled to the slicer, and is arranged to adjust the decision adjustment parameter according to a sleep state of a communication device in which the decision feedback equalizer is disposed.

Abstract: Disclosed embodiments include a decision feedback equalizer (DFE) comprising an N-bit parallel input adapted to be coupled to a communication channel and configured to receive consecutive communication symbols, a first DFE path including a first path input configured to receive communication symbols, and a first adder having a first adder input coupled to the first path input. There is a first DFE filter having outputs responsive to the first DFE filter inputs, the outputs coupled to the second adder input. The DFE includes a first path having a first slicer and a first multiplexer, a first path multiplexer output, and a second DFE path including a second path input configured to receive a second communication symbol, a second adder, a second DFE filter, a second slicer, and a second multiplexer.

Abstract: An amplifier output from an amplifier to an SR latch is used as a feedback signal through a buffer. An adder having a combination of an addition unit and an xh block is provided within the amplifier and transmits a feedback signal (analog signal) generated from the feedback signal FBD (digital signal) by the xh block to the addition unit and adds it to an output from a latch block. In the amplifier, the operation for adding the output from the latch block and the feedback signal occurs during a latch operation in the latch block.

Abstract: Various embodiments provide for data sampling with loop-unrolled decision feedback equalization. In particular, some embodiments provide for an unrolled first-tap Decision Feedback Equalizer (DFE) loop that comprises parallel data samplers that each include a tri-state output.

Abstract: A receiver includes an equalizer circuit, a radio frequency interference cancellation circuitry, and a channel estimation circuitry. The equalizer circuit is configured to process a first data signal according to a control signal, in order to generate a second data signal. The radio frequency interference cancellation circuitry is configured to detect a radio frequency interference signal according to the second data signal to generate radio frequency interference information, and to output a correction signal according to the radio frequency interference information, in order to correct the second data signal. The channel estimation circuitry configured to analyze a plurality of sets of signal components in the second data signal, and to utilize a power ratio of one of the plurality of sets of signal components to generate the control signal.

Abstract: Methods and systems are described for obtaining a sequence of data decisions and an error signal generated by one or more samplers operating on a received input signal according to a sampling clock, applying the sequence of data decisions and the error signal to each logic branch of a set of logic branches, and responsively selecting a logic branch from the set of logic branches, the logic branch selected responsive to (i) a detection of a transitional data pattern in the sequence of data decisions and (ii) the error signal, the selected logic branch generating an output current, and providing the output current to a local oscillator controller, the output current sourcing and sinking current to a capacitor through a resistive element to adjust an input voltage of a proportional control circuit relative to a voltage on the capacitor connected to the resistive element.

Abstract: A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

Abstract: A decision feedback equalizer for generating an output signal according to an input signal includes: a feedforward equalizer, a feedback equalizer and a weight coefficient control unit. The feedforward equalizer includes a plurality of tapped delay lines and is controlled by a set of first weight coefficients. The feedback equalizer includes a plurality of tapped delay line and is controlled by a set of second weight coefficients. The weight coefficient control unit is employed to selectively adjust at least one of the set of first weight coefficients and determine a set of first boundary values for at least one of the set of second weight coefficients. When the at least one of the set of second weight coefficients does not exceed the set of first boundary values, the weight coefficient control unit increments the at least one of the set of first weight coefficients.

Abstract: A method of transmitting and receiving a signal, by a base station (BS), in a wireless communication system is provided. The method includes determining whether each of at least one terminal connected to the BS supports nonlinear precoding (NLP) or a modulo operation, determining a plurality of signals that are overlapping-transmitted in a time-frequency resource region from among a control signal, a reference signal (RS), and a data signal transmitted from the BS, based on whether the at least one terminal supports the NLP or the modulo operation, and transmitting, to each of the at least one terminal, information about whether the NLP or the modulo operation is performed in a resource where the plurality of signals are transmitted.

Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.

Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.

Abstract: A signal receiver includes a first preliminary receiver circuit suitable for receiving an input signal and generating a first preliminary reception signal based on a first reference voltage, a second preliminary receiver circuit suitable for receiving the input signal and generating a second preliminary reception signal based on a second reference voltage, a reception circuit suitable for selecting one of the first preliminary reception signal and the second preliminary reception signal in response to a voltage level of a reception signal and generating the reception signal using the selected signal, and a reference voltage generation circuit suitable for adjusting a voltage level of the first reference voltage based on a first offset and adjusting a voltage level of the second reference voltage based on a second offset.

Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

Abstract: A example receiver includes analog circuitry configured to equalize and amplify an input signal and provide an analog signal as output; clock data recovery (CDR) circuitry configured to recover data clocks and edge clocks from the analog signal; a plurality of eye height optimization circuits, each of the plurality of eye height optimization circuits configured to, based on a respective data pattern of a plurality of data patterns, sample the analog signal based on the data clocks and the edge clocks, feed back first information to the analog circuitry for adjusting the eye amplitude, and feed back second information to the CDR circuitry for adjusting the data clocks; and an eye width optimization circuit configured to receive data and edge samples from the plurality of eye height optimization circuits, feed back third information to the CDR circuitry to adjust the edge clocks, and feed back fourth information to the analog circuitry to adjust the equalization.

Abstract: Systems and methods are disclosed for a multiple detector data channel and data detection utilizing different cost functions. For example, a digital data channel system can have multiple data detectors where each data detector implements a distinct cost function for detecting data. A cost function analyzer can then selectively choose decisions from the multiple data detectors to generate a data sequence. In some examples, a dual detector system may have one detector implement a Soft-Output Viterbi Algorithm (SOVA) cost function and another detector implement a peak detection algorithm. Further, in some embodiments, the cost function analyzer can implement multiple selection criteria to determine which decisions to include in a data sequence from the multiple data detectors.

Abstract: This application provides an error correction method and apparatus, relates to the field of communications technologies, so as to reduce a bit error rate of a decision feedback equalizer (DFE) and improve equalization performance. The method includes: obtaining a decision signal of a DFE; obtaining at least one of an input signal, an equalized output signal, and a difference of the DFE, where the difference is a difference between a level value of the decision signal and a level value of the equalized output signal; determining a symbol location of an end of burst error of the decision signal based on detection of at least one of the decision signal, the equalized output signal, and the difference; and when the symbol location is detected, performing error correction on the decision signal based on the at least one of the input signal, the equalized output signal, and the difference.

Abstract: Embodiments are directed to continuous time linear equalization including a low frequency equalization circuit which maintains DC gain. A first all-pass filter is coupled to an integrated filter, the integrated filter having a low-pass filter and a second all-pass filter. A high-pass filter is coupled to the first all-pass filter and the integrated filter, a differential input terminal being coupled to the first all-pass filter, the integrated filter, and the high-pass filter, where a differential output terminal is coupled to the high-pass filter.

Abstract: One embodiment can provide a sampler for a decision feedback equalizer (DFE). The sampler can include a comparator comprising a resolver and a plurality of amplifiers coupled to the resolver. The plurality of amplifiers are to receive an input signal and one or more feedback signals, and the plurality of amplifiers are coupled to each other in parallel, thereby facilitating a summation of the input signal and the one or more feedback signals. The comparator is to generate an output based on the summation of the input signals and the one or more feedback signals. The sampler can further include an inverter to invert the output of the comparator. The inverted output of the inverter is sent to a tap-1 amplifier to generate a tap-1 feedback signal to be sent to the comparator at a next unit interval (UI).

Abstract: Methods and systems are described for obtaining a plurality of BER-specific correction values by comparing a first set of BER values obtained by sampling, at a sampling instant near the center of a signaling interval, a non-DFE corrected received signal with a second set of BER values obtained by sampling a DFE-corrected received signal at the sampling instant. A set of eye-scope BER measurements are obtained, each eye-scope BER measurement having a sampling offset relative to the sampling instant, a voltage offset value representing a voltage offset applied to alter a decision threshold, and an eye-scope BER value. A set of DFE-adjusted eye-scope BER measurements are generated by using BER-specific correction values to adjust the voltage offset values of the eye-scope BER measurements.

Abstract: In some disclosed embodiments, a Decision Feedback Equalizer (DFE) processes multiple symbols in parallel using a novel architecture that avoids violating a timing constraint. The DFE comprises Feed-Back (FB) filters that can be configured to equalizing nonlinear phenomena. Using a Look-Up Table (LUT)-based implementation, the FB filters may implement complex nonlinear functions at low hardware complexity, low latency and low power consumption. A LUT-based implementation of the FB filter supports adaptive FB filtering to changing channel conditions by updating LUT content.

Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

Abstract: A clock and data recovery (CDR) device includes a data sampler configured to output a data signal by sampling an input signal according to a first clock signal; an edge sampler configured to output an edge signal by sampling the input signal according to a second clock signal, the second clock signal having substantially the same frequency as the first clock signal and having substantially an opposite phase to the first clock signal; an error detection circuit configured to identify a plurality of patterns based on the data signal and the edged signal and generate an error signal according to occurrence frequencies of the identified plurality of patterns; and an oscillation control circuit configured to generate a first oscillation control signal to control an oscillator generating the first and second clock signal according to the error signal.

Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including a first equalizer and a clock reproduction circuit. The first equalizer boosts a data signal. The clock reproduction circuit extracts from the boosted data signal information of a pair consisting of a rise edge and a fall edge which are temporarily separated from each other by N or more times (N is an integer of two or higher) as much as a clock cycle, performs a phase adjustment based on the information about the pair of the rise edge and the fall edge, and reproduces a clock.

Abstract: Decision feedback equalizers and equalization methods may employ fractional tap unrolling and/or probability-based decision threshold placement. One illustrative fractional tap unrolling equalization method embodiment includes: tracking preceding symbol decisions; converting an equalized signal into tentative symbol decisions with a precompensation unit; and selecting from the tentative symbol decisions based on the preceding symbol decisions.

Abstract: A jitter determination method for determining at least one jitter component of an input signal is described. The input signal is generated by a signal source, including: receiving the input signal; determining a step response based on the decoded input signal, the step response being associated with at least the signal source; and determining the at least one jitter component of the input signal based on at least one of the input signal and the determined step response. Further, a measurement instrument is described.

Abstract: Methods and systems are described for sampling a data signal using a data sampler operating in a data signal processing path having a decision threshold associated with a decision feedback equalization (DFE) correction factor, measuring an eye opening of the data signal by adjusting a decision threshold of a spare sampler operating outside of the data signal processing path to determine a center-of-eye value for the decision threshold of the spare sampler, initializing the decision threshold of the spare sampler based on the center-of-eye value and the DFE correction factor, generating respective sets of phase-error signals for the spare sampler and the data sampler responsive to a detection of a predetermined data pattern, and updating the decision threshold of the data sampler based on an accumulation of differences in phase-error signals of the respective sets of phase-error signals.

Abstract: The present disclosure provides a non-linear receiver, an asymmetric decision feedback equalization circuit and method, including: converting an optical signal emitted by a laser device into an electrical signal; obtaining a compensation amplitude of a current data in the electrical signal by obtaining an actual amplitude of the current data, and compensating the current data based on a logic value of k prior data of the current data and a feedback coefficient corresponding to the prior data; comparing the compensation amplitude of the current data with a decision threshold to determine the logic value of the current data; the feedback coefficient is an absolute value of an influence amount of the prior data on an amplitude of the current data, and k is a positive integer. The present disclosure can overcome the bit error problem of the receiver and reduce jitter of the clock recovered by the clock recovery circuit.

Abstract: An equalization circuit includes a feed-forward equalization (FFE) circuit and a decision feedback equalization (DFE) circuit. The FFE circuit includes a first FFE tap, a second FFE tap coupled to the first FFE tap, and a variable gain amplifier. The variable gain amplifier includes an input and a programmable capacitor. The input is coupled to the first FFE tap and the second FFE tap. The programmable capacitor is coupled to the input. The DFE circuit includes an input and a DFE tap. The input is coupled to the variable gain amplifier. The DFE tap is coupled to the input of the variable gain amplifier.

Abstract: An apparatus includes a first half-cell, a second half-cell, a multiplexer and a decision feedback equalizer. The first input stage may be configured to present a first differential input to the first auto-zero stage and the second auto-zero stage. The second input stage may be configured to present a second differential input to the third auto-zero stage and the fourth auto-zero stage. The multiplexer may be configured to receive a first output from the first auto-zero stage, receive a second output from the third auto-zero stage and present a decision feedback input comprising one of the first output and the second output. The decision feedback equalizer may be configured to generate a feedback signal in response to the decision feedback input and present the feedback signal to the first feedback buffer and the second feedback buffer.

Abstract: Methods and systems are described for receiving an input data voltage signal at a first data decision circuit of set of pipelined data decision circuits, receiving an aggregate decision feedback equalization (DFE) correction current signal from a first analog current summation bus, the aggregate DFE correction current signal comprising a plurality of DFE tap-weighted currents from respective other data decision circuits of the set of pipelined data decision circuits, determining a data output decision value based on the received input data voltage signal and the received aggregate DFE correction current signal, and generating at least one outbound DFE tap-weighted current on at least one other analog current summation bus connected to at least one other data decision circuit of the set of pipelined data decision circuits.

Abstract: The present invention is directed to communication methods and systems thereof. In a specific embodiment, a noise cancelation system includes a slicer that processes a data stream generates both PAM symbols and error data. An RIN estimator generates RIN data based on the PAM symbols and the error data. A filter removes non-RIN information from the RIN data. The filtered RIN data includes an offset term and a gain term, which are used to remove RIN noise from the data stream. There are other embodiments as well.

Abstract: A receiver in the present disclosure includes: a first input end, N first output ends, N baseband signal recovery modules, and a multiple-input multiple-output equalization module. Each baseband signal recovery module includes two second output ends; one second output end of each baseband signal recovery module is configured to output a baseband signal; and the other second output end is configured to output data enabling control information. The multiple-input multiple-output equalization module is configured to: control, based on N pieces of data enabling control information, a time sequence of N baseband signals entering the multiple-input multiple-output equalization module for equalization filtering processing, and perform equalization filtering processing on the N baseband signals by using N transmitters as references to obtain recovered data of the N transmitters. According to the embodiments of the present disclosure, asynchronous multi-transmitter data is received.

Abstract: A noise reduction system for a digital receiver reduces noise in signals received at the digital receiver. The digital receiver includes an input for receiving an analogue signal, analogue signal processing circuitry for processing an analogue signal, and an output for providing the processed signal to a digital signal processor. The noise reduction system is located between the input and the analogue signal processing circuitry, and includes a first component that outputs results of a noise signal identification and a second component that applies one or more counter-measures to the received analogue signal to produce a modified analogue signal. The modified analogue signal has a reduced level of noise compared to the received analogue signal, wherein the noise reduction system is arranged to assess the effectiveness of the one or more counter-measures applied by the second component to determine whether any further counter-measures are required.

Abstract: An apparatus includes an FFE circuit, including a clock generator creating multiple sub-rate phases of an input clock, and a multi-phase sampler responsive to a data signal and to the multiple sub-rate phases generated by the clock generator. The sampler is configured to sample the data signal and to generate held sample outputs corresponding to the multiple sub-rate phases. A SC equalization circuit in the FFE circuit has two states and is responsive to inputs from the multi-phase sampler output and the clock generator. The SC equalization circuit is configured to form outputs using the two states. A variable gain output stage in the FFE circuit is responsive to the outputs from the SC equalization circuit and is responsive to gain control signal(s) to provide variable gains to corresponding outputs of the SC equalization circuit to form equalized outputs based on the data signal.

Abstract: This application discloses a soft value extraction method and device applicable to an OvXDM system, and the OvXDM system. In the method, waveform coding is performed on all symbols in a hard value sequence, to generate a predictive value after overlapped coding; the symbols in the hard value sequence are reversed one by one, and overlapped coding is performed on each reversed symbol and associated symbols before and after the reversed symbol, to generate a predictive value of the reversed symbol; and for each symbol in the hard value sequence, a soft value of the current symbol is calculated based on A×(+1??1), where A is a coefficient related to a channel type, +1=?yrx?y+1?, and ?1=?yrx?y?1?2; if y+1 is a predictive value of the symbol obtained after overlapped coding and before reversing, y?1 is a predictive value of the symbol obtained after overlapped coding and reversing; and yrx is a received signal sequence.

Abstract: A random access memory (RAM) including a deserializer is disclosed. The RAM further comprises a continuous-time linear equalizer (CTLE) including a first input terminal that receives an input signal for the RAM and a first output terminal communicatively connected to the deserializer, the CTLE configured to perform a channel gain compensation on the input signal received by the first input terminal and to transmit the compensated input signal to the deserializer. The RAM may further comprise a decision feedback equalizer (DFE) including a second input terminal communicatively connected to the CTLE and a second output terminal communicatively connected to the deserializer, the DFE configured to reduce an inter-symbol interference (ISI) of the input signal.

Abstract: An equalizer circuit includes a first arithmetic circuit, a second arithmetic circuit, a data sampling circuit, and an edge sampling circuit. The first arithmetic circuit is configured to compensate an equalization sequence by secondary feedback sequences to output a first added sequence. The second arithmetic circuit is configured to compensate the first added sequence by a primary feedback sequence to output a second added sequence. The data sampling circuit samples, according to data clock, the second added sequence to output a primary sequence, and gains the primary sequence to output the primary feedback sequence. The data sampling circuit sequentially samples, according to the data clock, the primary sequence to output secondary sequences. The data sampling circuit gains the corresponding secondary sequences to output the secondary feedback sequences. The edge sampling circuit is configured to sequentially sample, according to an edge clock, the first added sequence to output an edge sequence.

Abstract: A method for adaptive signal processing is provided. In the method, a second vector is obtained by initializing a first vector without regularization of a cost function. The cost function is regularized with the first vector and the second vector as variables. The first vector is updated based on an input signal, according to the regularized cost function. Then, an output signal is provided based on the updated first vector. The second vector is updated based on the update of the first vector. An apparatus for adaptive signal processing is provided accordingly. The method and the apparatus are well compatible with existing adaptive signal processing. The convergence coefficients of the adaptive filter system become more stable. Moreover, impact of an extra penalty added to the cost function on a bias can be minimized, and the increased complexity of the system is very limited.

Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

Abstract: An apparatus includes a clockless delay adaptation loop configured to adapt to random data. The apparatus also includes a circuit coupled to the clockless delay adaptation loop. The clockless delay adaptation loop includes a cascaded delay line and an autocorrelation control circuit coupled to the cascaded delay line, wherein an output of the autocorrelation control circuit is used to generate a control signal for the cascaded delay line.

Abstract: A speculative decision feedback equalizer with split unroll multiplexers is provided. The speculative decision feedback equalizer splits an unroll multiplexer into two multiplexers. One split multiplexer provides a data path for the unroll selection signal, and the other split multiplexer provides a separate data path for the summer differential tap. In this way, the loading of an input stage of the summer circuit and the loading from the h1 unrolling loop are decoupled, allowing each split multiplexer to be configured according to a specific timing requirement along a respective data path. Thus, timing performance of the speculative decision feedback equalizer is improved.

Abstract: Embodiments include apparatuses, methods, and systems including a decision feedback equalizer (DFE). The DFE includes a first summer circuit, a second summer circuit, a decision circuit, and a tap-delay line including a number of delay elements. The first summer circuit is to add together an analog signal and a first set of weighted feedback taps {h(j+1), . . . h(m)} of time delayed signals of a detected symbol to generate a first summand. The second summer circuit is to add together a second set of weighted feedback taps {h(k+1), h(n)} of time delayed signals of the detected symbol to generate a second summand. The decision circuit is to receive at least the first summand and the second summand, to generate the detected symbol based on a sum including the first summand and the second summand. Other embodiments may also be described and claimed.

Abstract: This disclosure provides a split-path equalizer and a clock recovery circuit. More particularly, clock recovery operation is enhanced, particularly at high-signaling rates, by separately equalizing each of a data path and an edge path. In specific embodiments, the data path is equalized in a manner that maximizes signal-to-noise ratio and the edge path is equalized in a manner that emphasizes symmetric edge response for a single unit interval and zero edge response for other unit intervals (e.g., irrespective of peak voltage margin). Such equalization tightens edge grouping and thus enhances clock recovery, while at the same time optimizing data-path sampling. Techniques are also disclosed for addressing split-path equalization-induced skew.

Abstract: Methods and devices include an input buffer configured to receive data. Decision feedback equalizer (DFE) circuitry includes a DFE configured to interpret levels of the data from the input buffer and a DFE buffer that stores previous values to control the DFE based on the previous values. Moreover, the DFE circuitry also includes reset circuitry configured to reset the DFE buffer to an initial state. Furthermore, the DFE circuitry includes suppression circuitry configured to suppress resets using the reset circuitry for an interval between write operations to the memory device.

Abstract: Apparatus and methods are provided for noise-whitening post-compensation in a receiver. A first apparatus includes a first whitening filter configured to filter a received signal comprising symbols to generate a first filtered signal. The first apparatus further includes a first decision feedback equalizer having an input coupled to an output of the first whitening filter to receive the first filtered signal. The first decision feedback equalizer is configured to apply decision feedback equalization to the first filtered signal to generate estimates for the symbols of the received signal. A second apparatus includes a decision device configured to generate a symbols decision based on a received signal comprising symbols, a noise predictor configured to predict noise in the received signal, and a subtractor configured to subtract the predicted noise from the received signal to generate a symbols estimate.

Abstract: A receiver includes a sampler that samples first voltage levels corresponding to a first logical value of data and second voltage levels corresponding to a second logical value of the data, based on a sampling clock. An equalizer receives and adjusts the first and second voltage levels. A clock and data recovery circuit recovers the sampling clock, based on the first and second voltage levels from the equalizer. An eye opening measurement circuit: (1) tracks a first sigma level by a first step unit depending on upper voltage levels greater than a first reference voltage level among the first voltage levels, (2) tracks a second sigma level by a second step unit depending on lower voltage levels less than a second reference voltage level among the second voltage levels, and (3) calculates a difference between the first sigma level and the second sigma level.

Abstract: Several methods and systems for chroma residual data prediction for encoding blocks corresponding to video data are disclosed. In an embodiment, at least one coefficient correlating reconstructed luma residual samples and corresponding reconstructed chroma residual samples is computed for one or more encoded blocks of video data. Predicted chroma residual samples are generated for encoding a block of video data based on corresponding reconstructed luma residual samples and the at least one coefficient.

Abstract: A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.