Abstract: The present invention is directed to communication methods and systems thereof. In a specific embodiment, a noise cancelation system includes a slicer that processes a data stream generates both PAM symbols and error data. An RIN estimator generates RIN data based on the PAM symbols and the error data. A filter removes non-RIN information from the RIN data. The filtered RIN data includes an offset term and a gain term, which are used to remove RIN noise from the data stream. There are other embodiments as well.

Abstract: A phase noise compensation apparatus is used for a demodulation apparatus for demodulating a transmission signal modulated by a modulation scheme that uses phase information for data identification. A phase detector detects a phase error of a reception pilot symbol sequence included in a reception symbol sequence. A first filter refers to the phase error detected in a time series manner and sequentially estimates first phase noise components. A second filter refers to the phase error detected in a reverse time series manner and sequentially estimates second phase noise components. The synthesis processing unit estimates a phase noise component of a reception symbol based on an estimated value of the first phase noise component, an estimated value of the second phase noise component, and the phase error. The phase rotator rotates a phase of the reception symbol based on the estimated phase noise component of the reception symbol.

Abstract: Disclosed herein are related to a system and a method for high speed communication. In one aspect, the system includes a set of slicers configured to generate a slicer output signal digitally indicating a level of an input signal received by the set of slicers. The system includes a speculative tap coupled to the set of slicers, where the speculative tap is configured to select bits of the slicer output signal based on selected bits of a prior slicer output signal. The system includes a decoder coupled to the speculative tap, where the decoder is configured to decode the selected bits of the slicer output signal in a first digital representation into a second digital representation. The system includes a feedback generator coupled to the decoder, where the feedback generator is configured to generate a feedback signal according to the decoded bits of the slicer output signal.

Abstract: A receiver embodiment has an equalizer that includes: an array of sample and hold elements, an array of linear equalizers, and an array of decision elements. Each sample and hold element in the array periodically samples an analog receive signal with a respective phase to provide an associated held signal. Each linear equalizer in the array forms a periodically-updated weighted sum of the held signals from the array of sample and hold elements. Each decision element in the array derives at least one sequence of symbol decisions based on at least one of the periodically-updated weighted sums. The resulting sequences of symbol decisions are output in parallel.

Abstract: Apparatus and methods for training and operating of robotic devices. Robotic controller may comprise a predictor apparatus configured to generate motor control output. The predictor may be operable in accordance with a learning process based on a teaching signal comprising the control output. An adaptive controller block may provide control output that may be combined with the predicted control output. The predictor learning process may be configured to learn the combined control signal. Predictor training may comprise a plurality of trials. During initial trial, the control output may be capable of causing a robot to perform a task. During intermediate trials, individual contributions from the controller block and the predictor may be inadequate for the task. Upon learning, the control knowledge may be transferred to the predictor so as to enable task execution in absence of subsequent inputs from the controller. Control output and/or predictor output may comprise multi-channel signals.

Abstract: An apparatus and a method. The apparatus includes a receiver including an input for receiving a codeword of length mj, where m and j are each an integer; a processor configured to determine a decoding node tree structure with mj leaf nodes for the received codeword and receive an integer i indicating a level at which parallelism of order m is applied to the decoding node tree structure; and m successive cancellation decoders (SCDs) configured to decode, in parallel, each child node in the decoding node tree structure at level i.

Abstract: An amplifier circuit includes: an amplifier configured to receive at least one input signal and generate an output voltage in response to the at least one input signal and a gain control voltage; a voltage detector configured to generate a detector voltage based on the output voltage; a gain control summation circuit configured to generate an error signal by subtracting the detector voltage from a reference voltage; a loop filter configured to generate the gain control voltage based on the error signal and adjust the loop bandwidth in response to a loop filter adjust signal; and an analog automatic gain control bandwidth controller configured to monitor the detector voltage and the gain control voltage, to provide the reference voltage and the loop filter adjust signal, and to control a loop bandwidth of the output signal.

Abstract: A contactless communication device is capable of communicating in a contactless way with a reader by using active load modulation. Each frame is preceded by a reception period. An antenna is configured to receive a reader signal during each reception period, and to receive a reader carrier signal and transmit a modulated device carrier signal to the reader during each frame. A processor is configured to carry out, in each reception period, a first synchronization between a signal originating from the reader signal received at the antenna and a device carrier clock signal device generated in the device. The processor is also configured to carry out, within each frame, a modulated device carrier signal suppression process in order to obtain a processed signal, and a second synchronization between the processed signal and the device carrier clock signal.

Abstract: Methods and systems for analyzing data are disclosed. An example method can comprise receiving a first data signal, decoding the first data signal, determining a second data signal based on the decoded first data signal, and determining a modulation error ratio based on a difference between the first data signal and the second data signal.

Abstract: A communication system receives a binary sequence from a sensor, identifies a power consuming characteristic of the binary sequence, and determines an error component configured to reduce the power consuming characteristic of the binary sequence. The system compares the error component to an error tolerance deviation, and if the error component is below the error tolerance deviation, combines the error component with the binary sequence to produce an output sequence and transmits the output sequence via a serial interface to a receiver configured to receive the output sequence. The error threshold is based in part on an error tolerance characteristic of the receiver.

Abstract: A communication device includes a receiver configured to receive a signal, a sampler configured to sample the signal for each digital value of the predefined sequence of digital values in the signal, a memory configured to store a table giving, for each of a plurality of combinations of one or more preceding first digital values and a following second digital value, a threshold for a signal level to detect the second digital value, an initializer configured to, for a combination in a subset of the plurality of combinations, initialize the table based on a sample of the signal for the second value, and for a combination outside of the subset, select a combination from the subset and initialize the table based on a sample of the signal for the second value of the selected combination.

Abstract: Various embodiments provide for data communications using decision feedback equalization (DFE) and Tomlinson-Harashima precoding (THP).

Abstract: A decision feedback equalizer (DFE) comprises two charge-steering (CS) input latches driven by complementary ½-rate clocks, two pairs of CS primary latches, and two pairs of taps. The primary latches are driven by ¼-rate clocks. In a first aspect, each one of the input latches and the primary latches includes a respective differential pair of n-channel output transistors, and each tap includes a respective differential pair of p-channel input transistors. In a second aspect, each one of the input latches and the primary latches includes a respective differential pair of p-channel input transistors, and each tap includes a respective differential pair of n-channel output transistors. In some implementations, no element of any one of the taps is driven by any ½-rate clock. In some implementations, every switch of at least one of the taps is driven by one of the ¼-rate clocks.

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

Abstract: A receiver is provided that generates a data sampling clock that is offset by clock offset that is a function of a decision feedback equalizer gain to account for a data sampling timing error that would occur without the clock delay.

Abstract: A device includes a combinational circuit configured to create a one or more distortion correction factors used offset inter-symbol interference from a data stream on a distorted bit. The device also includes a selection circuit coupled to the combinational circuit. The selection circuit includes a feedback pin configured to receive a control signal and an output, wherein the selection circuit is configured to select a first distortion correction factor of the one or more distortion correction factors based upon the control signal and transmit the first distortion correction factor from the output.

Abstract: A PAM reception circuit includes a first comparison circuit that outputs a first bit value in two-bit values based on a result of a comparison between a reception signal of pulse amplitude modulation 4 in which the two-bit values are associated with four potential levels divided by three threshold values by gray codes and a first threshold value which is a center of the three threshold values, an absolute value circuit that outputs an absolute value of a difference between the reception signal and the first threshold value or a negative value obtained by inverting a sign of the absolute value from a positive sign to a negative sign, and a second comparison circuit that outputs a second bit value in the two-bit values based on a result of a comparison between a second threshold value which is larger than the first threshold value in the three threshold values.

Abstract: The present invention provides a semiconductor device capable of properly performing equalization even when the transfer rate of serial data is changed. A semiconductor device includes: an addition circuit of adding input data and feedback data and outputting addition data; a first sampling circuit of sampling the addition data from the addition circuit and outputting sampling data; a multiplication circuit of multiplying the sampling data from the first sampling circuit by a tap coefficient to generate the feedback data; a tap coefficient determination circuit determining the tap coefficient on the basis of the sampling data from the first sampling circuit; and a calibration circuit of adjusting a delay time since the first sampling circuit outputs the sampling data until the addition data corresponding to the output sampling data is supplied to the first sampling circuit.

Abstract: A two-stage decision feedback equalizer. The decision feedback equalizer is configured to receive serial data, at an analog input, at a first data rate. The two-stage decision feedback equalizer has an analog input and four digital outputs, and includes a first stage and a second stage. The first stage is connected to the analog input, and includes a half-rate predictive decision feedback equalizer consisting of current mode logic circuits. The second stage is connected to the first stage, and consists of complementary metal oxide semiconductor circuits.

Abstract: A high-speed serial data system includes a transmitter and a receiver. The receiver includes a compensation module, a memory, and a control module. The compensation module includes a setting that selects a compensation value from among a plurality of compensation values for a characteristic of the receiver. The memory stores a whitelist value from among the compensation values. The control module determines that a performance level of the receiver is below a performance level threshold. In response to determining that the performance level is below the performance level threshold, the control module uses the whitelist value to reevaluate the performance level of the receiver, and applies the whitelist value to the compensation module when the reevaluated performance level is above the performance level threshold.

Abstract: The invention relates to a quantized detection in uplink mimo with oversampling that is a temporal oversampling in quantized uplink MIMO systems.

Abstract: A receiver capable of receive and process data signals of multiple baud rates by using an equalizer that is disposed upstream of a decimator. The receiver includes an equalizer coupled to an output of an analog-to-digital converter (ADC), and a decimator couple to the output of the equalizer. The ADC and the equalizer both operate in full rates even in the case of lower data rate, e.g., half or quarter data rate. As the equalizer inherently can inherent remove high frequency noise as well as perform equalization, it practically functions as a low pass filter (LPF). Thereby, there is no need to introduce an extra dedicate LPF upstream of the decimator. This can advantageously and significantly simplify circuitry design and reduce latency.

Abstract: Disclosed are an adaptive RLS decision feedback equalizing system, characterized by comprising: an error code cross-correlation module, an equalization module, a decision feedback unit, a coefficient updating unit and an autocorrelation estimation module. Also disclosed are an implementation method of the adaptive RLS decision feedback equalizing system, comprising the following steps: 1) setting an initial value of c0 for a filtering coefficient; 2) generating a filtering output signal yk; 3) computing an error code cross-correlation result Ik; 4) updating the filtering coefficient ck?1 to ck; 5) updating an autocorrelation inverse matrix estimation result Pk?1 to Pk according to a forget constant factor w and an equalizer input signal sequence rk; 6) repeating step 2) to step 5), until the equalizer coefficient converges.

Abstract: A system for optimum phase searching in an Ethernet physical layer includes a time recovering circuit and an equalizer. The time recovering circuit includes a loop filter and a time error detector, and the equalizer includes a feed forward equalizer, a slicer and a feed backward equalizer. An optimum phase searching method includes obtaining optimum phases when mean squared errors calculated by the slicer are less than a first threshold, absolute values of mean values of outputs calculated by a time error detector are less than a second threshold, and the outputs are monotonic.

Abstract: To improve on power and bandwidth limitations associated with conventional feedforward equalizer (FFE) implementations, the present disclosure provides intersymbol interference (ISI) compensation circuits that do not use delay cells common to FFE structures. In one example, the compensation circuit of the present disclosure comprises a two stage amplifier. Each stage of the amplifier is implemented using a differential pair with degeneration. One of the amplifier stages has a transfer function with a zero in the left half of the s-domain, also called the s-plane, and the other amplifier has a transfer function with a zero in the right half of the s-domain. The amplifier stage with the zero in the left half of the s-domain can be used to provide post-cursor ISI compensation, and the amplifier stage with the zero in the right half of the s-domain can be used to provide pre-cursor ISI compensation.

Abstract: Methods and systems are described for receiving an input data voltage signal at a first data decision circuit of set of pipelined data decision circuits, receiving an aggregate decision feedback equalization (DFE) correction current signal from a first analog current summation bus, the aggregate DFE correction current signal comprising a plurality of DFE tap-weighted currents from respective other data decision circuits of the set of pipelined data decision circuits, determining a data output decision value based on the received input data voltage signal and the received aggregate DFE correction current signal, and generating at least one outbound DFE tap-weighted current on at least one other analog current summation bus connected to at least one other data decision circuit of the set of pipelined data decision circuits.

Abstract: A circuit and method for reducing intersymbol interference due to pre-cursor distortion. A first set of circuit elements located along a first circuit path of a receiver device process an analog input signal of the receiver to form an equalized representation of the input signal. A second set of circuit elements are located along a second circuit path that has lower latency than the first circuit path. The second set of circuit elements form a scaled signal as one of the following: a scaled representation of the input signal, an inverted scaled representation of the input signal, a scaled derivative of the input signal, and an inverted scaled derivative of the input signal. The scaled signal is combined with the equalized representation to cancel out a pre-cursor portion of the equalized representation.

Abstract: Methods and systems are described for receiving a plurality of signals in a signaling interval at a multi-input comparator (MIC), and responsively generating an analog linear combination of the received signals, amplifying the analog linear combination of the received signals using an integration stage, receiving the amplified differential voltage at two multi-phase receivers, each multi-phase receiver comprising one or more processing slices, each multi-phase receiver operating in a multi-phase processing path for processing the amplified differential voltage, wherein processing the amplified differential voltage includes generating output data decisions and phase-error information using a first multi-phase receiver of the two multi-phase receivers and selectively adjusting local speculative decision feedback equalization (DFE) slicing offsets of a second multi-phase receiver of the two multi-phase receivers according to the output data decisions generated by the first multi-phase receiver.

Abstract: Provided are a communication system, an abnormality detection device and an abnormality detection method that detects abnormality concerning communication such as information forged by utilizing a difference in timings of sampling between multiple communication devices. For the system configuration where ECUs transmit and receive information through a common communication line, abnormality detection related to communication is performed by a monitoring device connected to the communication line. Each ECU receives information by sampling once at a predetermined timing during a transmission period of one-bit information. The ECUs may also be allowed to perform sampling at different timings.

Abstract: A receiver module includes a clock recovery circuit and a decision feedback equalizer (DFE) circuit. The DFE circuit includes a data feedback loop configured to sample an input data stream combined with equalization values based on a first clock signal. The DFE circuit also includes an edge feedback loop configured to sample the input data stream combined with equalization values based on a second clock signal. The clock recovery circuit is configured to determine a phase error between a receiver clock signal and a target clock signal based on output samples from the data feedback loop and the edge feedback loop.

Abstract: A system and method for Feed Forward Equalizer (FFE)-Aided Clock Data Recovery (CDR) to calibrate phase offset and enhance gain in baud rate sampling phase detector is provided. In an embodiment, a clock data recovery (CDR) apparatus includes an incremental feed forward equalizer (INC-FFE) in a CDR path and a calibration component in an equalization path, the calibration component connected to the INC-FFE, the calibration component configured to adjust FFE coefficients for the INC-FFE according to a phase code (PC) index in a PC index table and one of a signal-to-noise-ratio (SNR) and a bit error rate (BER) of a sampled signal, wherein the PC index table comprises adjustment values for the FFE coefficients, and wherein the PC index is linearly related to a sampling phase.

Abstract: A symbol interference cancellation circuit may be provided. The symbol interference cancellation circuit may include an interference cancellation circuit configured for generating an interference-cancelled signal based on weight application signals, sampling output signals, and a clock signal.

Abstract: A system and method for decision feedback equalizer (DFE) tap adaptation. An input signal is received at a DFE of a receiver, wherein the input signal comprises a serial bit stream of encoded symbols. Data samples and error samples are taken from the input signal and the data samples and the error samples are aligned establish a plurality of pairs of data samples and error samples, wherein the data sample and error sample of each of the plurality of pairs of data samples and error samples are from locations in the serial bit stream of encoded symbols that are known to be uncorrelated with each other. The DFE tap weights are then adjusted based upon the plurality of pairs of data samples and error samples.

Abstract: This invention relates to decorrelation of signals in order to improve coding gains of wireless communications. To this end a branch signal processor includes a summer to determine a sum of a first branch signal and a second branch signal to produce a sum signal. A conjugate swapper to determine a conjugate swap of the first branch signal and a conjugate swap of the second branch signal to produce two swapped signals, wherein the conjugate swapper takes an imaginary part of the first branch signal to become a real part and a real part of the first branch signal to become an imaginary part of a new complex signal which new complex signal becomes a first swapped signal, and wherein the conjugate swapper takes an imaginary part of the second branch signal to become a real part and a real part of the second branch signal to become an imaginary part of a second complex signal which second complex signal becomes a second swapped signal.

Abstract: A method is for processing a channel analog signal coming from a transmission channel. The method may include converting the channel analog signal into a channel digital signal, and detecting a state of the transmission channel based on the channel digital signal to detect whether the transmission channel is, over an interval of time, one or more of linear and time invariant and linear and cyclostationary.

Abstract: To improve on power and bandwidth limitations associated with conventional feedforward equalizer (FFE) implementations, the present disclosure provides intersymbol interference (ISI) compensation circuits that do not use delay cells common to FFE structures. In one example, the compensation circuit of the present disclosure comprises a two stage amplifier. Each stage of the amplifier is implemented using a differential pair with degeneration. One of the amplifier stages has a transfer function with a zero in the left half of the s-domain, also called the s-plane, and the other amplifier has a transfer function with a zero in the right half of the s-domain. The amplifier stage with the zero in the left half of the s-domain can be used to provide post-cursor ISI compensation, and the amplifier stage with the zero in the right half of the s-domain can be used to provide pre-cursor ISI compensation.

Abstract: The present disclosure relates to a 1/K-rate decision feedback equalizer (DFE) and to a decision feedback equalization method. The DFE comprises: (i) a summing circuit configured to combine K intersymbol interference (ISI) cancellation signals with an input signal of the DFE, (ii) K branches each including a reset-to-zero (RZ) latch configured to receive an output signal of the summing circuit according to a clock signal and to produce a RZ signal, and (iii) a feedback circuit including K filters each configured to receive a respective RZ signal from a respective RZ latch and to produce a respective ISI cancellation signal. The method comprises: (i) producing an output signal for K branches based on K cancellation signals and on an input signal, (ii) producing K RZ signals based on the output signal and on a clock signal, and (iii) producing the K ISI cancellation signals based on the K RZ signals.

Abstract: An apparatus is described that includes a receiver. The receive includes a data sampler, a positive error sampler and a negative error sampler each having respective inputs coupled to a same differential channel. The receiver also includes circuitry to drive the respective inputs, the circuitry to place a same calibration voltage on the differential channel to calibrate each of the data sampler, positive error sampler and negative error sampler with the same calibration voltage.

Abstract: There is provided a decision feedback equalizer including a comparison circuit configured to compare a value indicated as 2n of a pulse amplitude modulated signal with a threshold value, wherein n is an integer of 2 or more, a latch circuit configured to retain data of a comparison result of the comparison circuit, a decoder configured to decode the retained data by the latch circuit, and a setting circuit configured to set the threshold value based on the retained data fed back from the latch circuit.

Abstract: Apparatus and methods for training and operating of robotic devices. Robotic controller may comprise a predictor apparatus configured to generate motor control output. The predictor may be operable in accordance with a learning process based on a teaching signal comprising the control output. An adaptive controller block may provide control output that may be combined with the predicted control output. The predictor learning process may be configured to learn the combined control signal. Predictor training may comprise a plurality of trials. During initial trial, the control output may be capable of causing a robot to perform a task. During intermediate trials, individual contributions from the controller block and the predictor may be inadequate for the task. Upon learning, the control knowledge may be transferred to the predictor so as to enable task execution in absence of subsequent inputs from the controller. Control output and/or predictor output may comprise multi-channel signals.

Abstract: Various illustrative embodiments pertain to a signal quality evaluation system having a decision feedback equalizer (DFE) and a signal quality evaluator. The DFE receives an input signal containing symbols that represent digital data and uses the symbols to generate multiple detection thresholds. Each detection threshold is one of several detection thresholds that can be generated by the DFE by processing one or more symbols present in the input signal prior to a current clock cycle of a clock that is recovered from the input signal. The signal quality evaluator uses the detection thresholds provided by the DFE to detect transitions in the input signal. The signal quality evaluator may execute jitter measurements and/or time interval error (TIE) measurements by evaluating the transitions in the input signal.

Abstract: In the subject system, a receiver includes a feed forward circuit, a phase recovery circuit, and a feedback circuit. The feed forward circuit compensates for near reflections and provides an input to the phase recovery circuit and the feedback circuit. The phase recovery circuit performs phase recovery and provides phase recovery information to the feedback circuit. The feedback circuit adjusts and/or corrects a received symbol based at least in part on the received phase recovery information.

Abstract: System and method of timing recovery for recovering a clock signal with reduced interference with clock phase correction by an adaptive equalizer. The equalizer in the timing recovery loop is dynamically adapted to the current channel characteristics that vary over time. The equalizer includes compensation logic operable to detect and compensate a correction of clock phase ascribed to the equalization adaptation. The compensation logic can calculate the offset between a center of filter (COF) value and a COF nominal value, the offset indicative of the amount and direction of clock phase correction contributed by the equalizer. Based on the offset, the compensation logic adjusts the equalized signal by adjusting the tap weights of the equalizer to correct the offset, thereby compensating the clock phase correction.

Abstract: A symbol interference cancellation circuit may include a CTLE (continuous time linear equalizer) configured for cancelling a first post cursor component of an input signal according to a first weight application signal, and generating a pre-interference-cancelled signal; an interference cancellation circuit configured for cancelling second to fourth post cursor components of the pre-interference-cancelled signal according to second to fourth weight application signals, a sampling signal and output signals of shift registers, and generating an interference-cancelled signal; a sampling circuit configured for sampling the interference-cancelled signal based on a clock signal, and outputting the sampled interference-cancelled signal as the sampling signal; and the shift registers configured for shifting the sampling signal by a predetermined cycle of a clock bar signal which has a phase opposite to the clock signal, shifting the sampling signal by a predetermined cycle of the clock signal, and thereby providing s

Abstract: A method and system of equalizing in a decision feedback equalizer is provided. A plurality of adder circuits receives a digital code representing a previously decided symbol from an output of a prior path of a plurality of paths. A decision-making slicer circuit receives an input voltage and a first clock signal. The plurality of adder circuits receives a second clock signal and injects an offset current proportional to the digital code representing the previously decided symbol into a current injection input of the decision-making slicer circuit, at a first edge of the second clock signal. There is a predetermined skew between the first clock and the second clock to control a timing between the injection of the offset current of the plurality of adder circuits and the initiation of a decision-making phase of the decision-making slicer circuit.

Abstract: Apparatuses and method relating to DFE include a decision feedback equalizer with first and second integrating summers configured to receive an input differential signal. A bias current circuit is configured to alternate biasing of the first and second integrating summers. The first and second integrating summers alternately integrate, during clock signal phases of a clock signal and its complement, for transconductance of the input differential signal to a first output differential signal and a second output differential signal, respectively. The first and second integrating summers alternately drive, during other clock signal phases of the clock signal and its complement, residual voltages of the first output differential signal and the second output differential signal, respectively, to a same voltage level. A first clock signal and a second clock signal are out of phase with respect to one another for interleaving the first output differential signal and the second output differential signal.

Abstract: Described is an apparatus which comprises: samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE); and logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same. Described is an equalization scheme which comprises a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.

Abstract: Systems and methods disclosed herein provide for preventing the mis-equalization of signals transmitted over short transmission channels. Embodiments of the systems and methods provide for a receiver including a digital receiver equalization circuit that selectively provides a correction signal to a DFE tap weight based on the value of the current DFE tap weight as well as the logical values of the in-phase and error data samples associated with received signal.

Abstract: An equalizer and an equalization method. The method includes receiving a data signal over a channel. The method further includes equalizing the data signal, by a blind partial response equalizer circuit, to provide an equalized output of the data signal. An estimation of partial response equalizer taps employed to determine the equalized output, by the blind partial response equalizer circuit, is carried out independently of true channel input symbols and detected symbols corresponding to the data signal.