Abstract: A system for reduced-rate predictive DFE. In one embodiment a plurality of sampler-multiplexer blocks, each including two samplers and a multiplexer-latch, controlled by a multi-phase clock, sample the received analog signal one at a time, and the output of each multiplexer-latch, which may represent the value of the last received bit, is used to control the select input of another multiplexer-latch, so that the other multiplexer-latch selects the appropriate one of two samplers, each applying a different correction to the received analog signal before sampling. Each multiplexer-latch is a clocked element that tracks the data input when the signal at its clock input has a first logic level and retains its output state when its clock input has another (i.e., a second) logic level.

Abstract: A decision feedback equalizer for N-level amplitude modulated signal, includes: (N?1) level conversion circuits to add (N?1) shifting voltages to the amplitude modulated signal respectively; (N?1)×N determination feedback equalization-correction circuits to perform N types of decision feedback equalization processing, each of which adding each of N-level offset voltages corresponded to any one of N levels of a reception data ahead of one data cycle, on each of the (N?1) level shifted signals to generate (N?1) sets of N equalization correction signals; (N?1)×N comparison circuits; (N?1)×N first latch circuits; (N?1) selection circuits to select a comparison result of the N comparison circuits in each (N?1) sets; (N?1) second latch circuits; and a decoder, wherein each of the (N?1) selection circuits selects an equalization-correction signal among the N equalization-correction signals in each (N?1) set according to outputs latched by the (N?1) second latch circuits.

Abstract: An embodiment includes a receiver circuit, a feedback circuit and a control circuit. The receiver circuit is configured to receive each data bit of a plurality of data bits. The feedback circuit is configured to measure a first interference level generated by a first data bit of a first subset of the plurality of data bits on a second data bit of the plurality of data bits to generate one of a first plurality of feedback values. The feedback circuit is also configured to measure a second interference level generated by a third data bit of a second subset of the plurality of data bits on a fourth data bit of the plurality of data bits to generate one of a second plurality of feedback values. The control circuit is configured to determine a duty cycle dependent upon a comparison of the first plurality to the second plurality.

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide an offset correction technique for a SERDES system. A CTLE module for receiving input data signal is set to an isolation mode, and one or more sense amplifiers perform data sampling asynchronously during the isolation mode. During the isolation mode, CLTE(s) that are not directly connected to the sense amplifiers are shut. Data sampled during the isolation mode are used to determine an offset value that is later used in normal operation of the SERDES system. There are other embodiments as well.

Abstract: A continuous time linear equalizer and method of operation. The equalizer includes circuitry configured to provide a high-pass transfer function having a peaking frequency to equalize an input signal into an output signal. The circuitry includes an input gain stage configured to receive an input signal and to provide a gain; and an active peaking stage configured to set the gain at a peaking frequency. A bandwidth extension unit is configured to shift the peaking frequency of the continuous time linear equalizer to a higher frequency.

Abstract: Circuits, apparatus, and methods are disclosed for decision feedback equalization. In one embodiment, an apparatus includes a plurality of time-interleaved slices for processing an input data stream. Each of the slices includes a sampler circuit, a multiplexer, and a latch. In each slice, the multiplexer and the sampler circuit provide sampled output data corresponding to one of a plurality of different versions of the input data stream at times designated uniquely for the slice, according to one or more selection signals. The selection signals are derived from a output of the multiplexer of at least one other of the time-interleaved slices. The latch provides a controlled output in response to the multiplexer and the sampler circuit, as a function of the designated unique times.

Abstract: A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.

Abstract: A circuit for enabling an adaptation of an equalization circuit is described. The circuit comprises a continuous time linear equalizer configured to receive an input data signal and generate an equalized input data signal; a decision circuit configured to receive the equalized input data signal, wherein the decision circuit generates an estimate of the input data signal; channel estimation circuit configured to receive the estimate of the input data signal and an error signal to generate an impulse response estimate of an equivalent channel; a frequency response computation circuit configured to receive the impulse response estimate of the equivalent channel and generate a channel frequency response; and a continuous time linear equalizer control circuit configured to receive the channel frequency response and to generate a CTLE adaptation signal for controlling the continuous time linear equalizer.

Abstract: Vector signaling code communications systems rely on group transmission of code symbols using multiple signaling channels that must be actively monitored and adjusted to minimize differential signal characteristics. Information obtained during receive detection may be analyzed to identify channel operational characteristics during normal operation and perform non-disruptive channel adjustments. Initialization or start-up adjustment may also be performed using intentionally transmitted patterns.

Abstract: A signal processing system includes a variable gain amplifier, an analog-to-digital converter (ADC), a gain compensation module and a signal processing module. The variable gain amplifier applies a variable gain to an analog input signal to generate an amplified analog signal. The ADC converts the amplified analog signal to an amplified digital signal. The gain compensation module applies a compensation gain to the amplified digital signal to generate a compensated signal. The compensated signal has an instantaneous change lower than a predetermined threshold. The signal processing module performs a signal processing procedure on the compensated signal.

Abstract: A receiver is provided. The receiver includes a CTLE receiving a received signal, and generating a first equalized signal by processing the received signal according to a pole and a boost level; a slicing circuit coupled to the CTLE, generating a data signal according to the first equalized signal and a feedback equalization signal; a DFE coupled to the slicing circuit, generating the feedback equalization signal by processing the data signal according to a DFE coefficient set. Furthermore, the boost level is adjusted according to a first DFE coefficient of the DFE coefficient set, while the pole is adjusted according to the second and third DFE coefficients.

Abstract: A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs.

Abstract: A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery and DFE tap adaption; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at h0=h1+h2; and a phase mixer for transmitting a delay in response to receiving the phase and the delay is transmitted to the clocked-data comparators and the clocked-error comparators.

Abstract: Multiple input single output (MISO) systems and processes are presented that can adaptively equalize multiple signals to produce an output. In some examples, the MISO systems can include a fast transversal recursive least square (RLS) algorithm to produce the output. Fast transversal RLS algorithms can be less complex than other RLS algorithms. In some examples, the fast transversal RLS algorithm may be optimized to have no division operations. The MISO system may have two or more inputs.

Abstract: A solution for compensating a magnetic field sensor to permit detection of a small magnetic field in the presence of a large magnetic field is disclosed. A magnetic field sensor detects the magnetic field which produces an analog signal then encoded by an analog to digital converter (ADC) into a digital stream. A controller operating on the digital stream incorporates additional sensor data to create a compensation signal which is sent to a digital to analog (DAC) converter. This compensation signal then modifies the output of the magnetic field sensor before entering the ADC. Compensation is software controlled, and is thus adaptable to numerous conditions requiring compensation. Apart from being easily tunable, the compensation may respond dynamically to changing conditions. The invention has particular application to airborne electromagnetic surveying where small fields scattered from the Earth are measured in the presence of a large transmitted field.

Abstract: In a receiver, a decision feedback equalizer (“DFE”) receives an analog input signal. The DFE includes a subtraction block for subtracting weighted postcursor decisions from an analog input signal to provide an analog output signal. A postcursor decision block coupled to the DFE compares the analog output signal against positive and negative values of a postcursor coefficient to provide first and second possible decisions for selecting a current postcursor-based decision therebetween responsive to a previous postcursor-based decision. A precursor cancellation block receives the analog output signal, the previous postcursor-based decision and the current postcursor-based decision for providing a digital output signal for a previous sample of the analog input signal.

Abstract: Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.

Abstract: Methods and apparatus for provision of equalization effort-balancing of transmit (TX) Finite Impulse Response (FIR) and receive (RX) Linear Equalizer (LE) or RX Decision Feedback Equalizer (DFE) structures in high-speed serial interconnects are described. In some embodiments, data corresponding to a plurality of transmit equalization values and a plurality of receive equalization values for each lane of a link having a plurality of lanes is detected. At least one of the plurality of the transmit equalization values and at least one of the plurality of the receive equalization values are selected for each lane of the plurality of lanes of the link based on detection of saturation in a Decision Feedback Equalizer (DFE) tap of a corresponding lane of the link. Other embodiments are also claimed and/or disclosed.

Abstract: A data receiver implemented in an integrated circuit is described. The data receiver comprises an input receiving a data signal; a first equalization circuit coupled to receive the data signal, wherein the first equalization circuit is used to receive the data of the data signal; and a second equalization circuit coupled to receive the data signal, wherein the second equalization circuit is used to adjust a clock phase offset.

Abstract: A decision feedback equalizer system is disclosed. The decision feedback equalizer system includes a current summer core that in current mode, removes inter-symbol interference from a signal, and, a CMOS latch component, that is coupled to the current summer core, that receives a current mode signal and outputs a CMOS compatible signal. The components of the decision feedback equalizer system are controlled by a single clock.

Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.

Abstract: Apparatus and methods for wireless communications include determining a first echo cancellation metric indicative of a first amount of echo cancellation as a first function of a first transmit power of a first wireless communications device; and providing the first echo cancellation metric to a scheduling entity for scheduling full duplex (FD) or half duplex (HD) communication resources for the first wireless communications device.

Abstract: A transceiver includes a transmitter and a receiver. The transmitter includes a precoder stage, an encoder stage and a first converter stage. The precoder stage receives an input binary signal and a previously processed binary signal. The encoder stage is electrically coupled to the precoder stage and the first converter stage and includes a feed forward equalizer (FFE). The first converter stage generates a modulated signal. The receiver includes a second converter stage, an amplifier stage, a first equalizer stage and a second equalizer stage. The second converter stage receives the modulated signal. The first equalizer stage is electrically coupled to the amplifier stage. The second equalizer stage is electrically coupled to the first equalizer stage. The second equalizer stage includes a decision feedback equalizer (DFE) that converts the modulated signal into an output binary signal.

Abstract: Provided are an adaptive equalizer for adaptively controlling an equalization coefficient until two comparators outputs a same value, after generating a sensitivity difference between signals at a front end of each comparator for performing sampling, and a method of controlling the adaptive equalizer.

Abstract: A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to data processing including adjacent track interference detection and/or characterization.

Abstract: In a receiver, there is a precursor iterative canceller (“PIC”) having first and second paths. A postcursor decision block is coupled to the PIC to provide a decision signal thereto. The PIC includes: comparators for receiving an input signal and corresponding threshold inputs for precursor ISI speculation; and select circuits for selecting a first speculative input for the first path and a second speculative input for the second path, respectively associated with a negative precursor contribution and a positive precursor contribution. The first path and the second path in combination include at least a first stage and a second stage for processing the first speculative input and the second speculative input. The decision signal is provided to the first stage and to the select circuits. The select circuits are coupled to receive the decision signal for selection of the first speculative input and the second speculative input.

Abstract: An exemplary receiver equalizer includes a first decision feedback equalizer (DFE) sampler coupled to a summer, the first DFE to latch an equalized output of the summer. The first branch includes a second DFE sampler coupled to the first DFE sampler, the second DFE to latch an output of the first DFE sampler. The first branch includes a third DFE sampler coupled to the second DFE sampler, the third DFE to latch an output of the second DFE sampler. The summer coupled to the first, second, and third DFE samplers of the first branch, the summer to integrate the output of said DFE samplers, the received signal, and equalized outputs from one or more other branches, wherein the integrating occurs over a plurality of unit intervals (UIs).

Abstract: Systems and methods for optical multi-path interference (MPI) compensation are provided. In an embodiment, a mean MPI signal representing a mean amplitude of the MPI in an input signal is generated and subtracted from a first estimate of transmitted amplitude of the input signal to generate a mean MPI compensated estimate of transmitted amplitude. The mean MPI compensated estimate of transmitted amplitude is sliced to generate a decision of transmitted amplitude of the input signal. The mean MPI signal can be generated using a mean MPI feedback loop or using an iterative feed-forward process. In another embodiment, mean MPI levels corresponding to respective transmitted intensity levels are generated and used to control slice levels of a slicer in order to compensate for MPI.

Abstract: A method relates generally to data reception for any of a plurality of data rates. In such a method, information and phases of a clock signal are obtained by a decision feedback equalizer. The information is equalized using the phases of the clock signal with the decision feedback equalizer to provide equalized sample streams. The equalized sample streams and the phases of the clock signal are provided to a selection circuit block. A first and a second phase of the phases are swapped, along with swapping a first and a second equalized sample stream corresponding to the first phase and the second phase, responsive to a data rate of the plurality of data rates.

Abstract: A decision feedback equalizer (DFE) is provided. The DFE includes an analog front end, configured to receive a digital communication signal having amplitude modulation greater than two-level, and to output a feedforward signal based on the digital communication signal. The DFE includes a summing block, configured to receive the feedforward signal, a plurality of delayed data decisions as digital signals, and a plurality of adapted coefficients. The summing block is configured to produce an analog feedback signal as an analog subtraction from the feedforward signal of each of the plurality of delayed data decisions multiplied by a corresponding one of the plurality of adapted coefficients. The DFE includes a delay chain configured to produce the plurality of delayed data decisions based on the analog feedback signal, each of the plurality of delayed data decisions having two or more bits, corresponding to the amplitude modulation being greater than two-level.

Abstract: An adaptive equalization system and operating method thereof are disclosed herein. According to an embodiment, an apparatus comprises a plurality of equalizers and control logic to selectively enable one or more equalizers of the plurality of equalizers and disable one or more other equalizers of the plurality of equalizers based, at least in part, on a quality of the channel over which the signal is received. In another embodiment, the apparatus includes first control logic to select an equalizer for a header of a packet and second control logic to select an equalizer for a data payload of the packet.

Abstract: Embodiments of the present invention provide a decision feedback equalizer, which includes: a receive end, configured to receive a first differential signal, and input the first differential signal to the superimposer; a superimposer, configured to superimpose the first differential signal on a square-wave signal output by a adjusting unit to obtain a second differential signal; the adjusting unit, configured to perform phase and/or amplitude adjustment for a second square-wave signal; the first decision device is configured to compare a voltage amplitude of the second differential signal with a set value, and output a first square-wave signal; the second decision device is configured to compare the voltage amplitude of the second differential signal with a voltage amplitude of a signal adjusted by the adjusting unit, and input an obtained second square-wave signal to the adjusting unit. The embodiments of the present invention can reduce data edge jitter.

Abstract: Described are apparatuses and methods for generating floating taps for decision feedback equalizers. An apparatus may include a first delay cell including a first group of binary weighted sets of flip-flops to output a first signal, and a second delay cell including a second group of binary weighted sets of flip-flops to output a second signal. The apparatus may further include a multiplexer coupled to the first delay cell and the second delay cell to output a tap signal based on the first signal and the second signal. Other embodiments may be described and/or claimed.

Abstract: An embodiment of the present invention implements a linear feedback shift register (LFSR) as a counting device for an integrator of a DFE circuit. In embodiments of the present invention, the particular count sequence need not be known, instead only boundary values need be known. For example, for a LFSR having a predetermined count sequence, a digital integrator controller need not know every value of the count sequence. Instead, the digital integrator controller detects predetermined boundary values such as a minimum or maximum count.

Abstract: A two stage adaptive filter for use in a batch receiver includes an equalizer filter having as inputs an acquired signal representing a batch of data points and an equalizer filter value. The filtered signal is batch processed to produce reference and data symbols, which symbols are input to a residual filter to generate iteratively over the batch an error value. The error value is convolved with the equalizer filter value to produce a new equalizer filter value for use by the equalizer filter when a next batch of data points is processed.

Abstract: A method and apparatus are provided for channel equalization in a communication system. The channel equalization method includes calculating, using processing circuitry, filter coefficients of an adaptive equalizer in a frequency domain using particle swarm optimization (PSO) and filtering the signal using the computed filter coefficients.

Abstract: An equalizer includes a first discrimination circuit to receive an input signal corresponding to a signal output from a transmit-side equalizer to binarize the input signal by a first threshold value in unit time, a second discrimination circuit to binarize the input signal by a second threshold value in unit time, a first delay circuit to delay an output signal of the first discrimination circuit and that includes N-number (N>=2) of stages of unit delay circuits connected in cascade and operating in unit time, a second delay circuit to receives an output signal of the second discrimination circuit and that includes not less than an (N+1)-number of stages of unit delay circuits connected in cascade and operating in unit time, and a control unit that receives an output of the first delay circuit, and a second output signal output from the second delay circuit.

Abstract: Computationally efficient methods and related systems, for use in a test and measurement instrument, such as an oscilloscope, optimize the performance of DFEs used in a high-speed serial data link by identifying optimal DFE tap values for peak-to-peak based criteria. The optimized DFEs comply with the behavior of a model DFE set forth in the PCIE 3.0 specification.

Abstract: A method, receiver and program for equalising a radio signal comprising a sequence of data samples multiplexed with a sequence of pilot samples. The method comprises; calculating equaliser coefficients by computing cross-correlations of the received signal and known pilot samples available at the receiver and auto-correlations of the received signal; and equalising the received signal using the calculated coefficients.

Abstract: An eye diagram construction display apparatus includes an amplifier, a first equalizer, an addition unit, a second equalizer, a bit error rate check unit, a clock recovery unit, a clock synthesizer, a processing unit and a display unit. The first equalizer is electrically connected to the amplifier. The addition unit is electrically connected to the first equalizer. The second equalizer is electrically connected to the addition unit. The bit error rate check unit is electrically connected to the addition unit. The clock recovery unit is electrically connected to the addition unit and the bit error rate check unit. The clock synthesizer is electrically connected to the clock recovery unit. The processing unit is electrically connected to the addition unit, the bit error rate check unit and the clock recovery unit. The display unit is electrically connected to the processing unit.

Abstract: Systems and methods are provided for fast and precise estimation of frequency with relatively minimal sampling and relatively high tolerance to noise.

Abstract: A method and apparatus to align data blocks in a data signal and a reference signal to increase cross-correlation between the data signal and the reference signal as compared to the unaligned data and reference signals and cancel interference in the data signal in the frequency-domain under changing conditions and in the presence of the data signal.

Abstract: A receiver including recovery, error, and control modules. The recovery module: receives a data signal and an offset value; based on a coefficient, equalizes the data signal to generate an equalized signal; and generates a recovered signal based on the equalized signal. The recovered signal includes data recovered by the recovery module. The error module generates an error value based on a difference between the equalized signal and a threshold. The control module, based on the offset value, the recovered signal, and the error value: generates the coefficient; determines the threshold; and determines a characteristic of an eye diagram of the recovered signal. The recovered signal has a non-repeating pattern such that overlaid traces of the recovered signal are in a shape of an eye and provide the eye diagram. The overlaid traces include jitter. The control module generates the coefficient to reduce an amount of the jitter.

Abstract: A decision feedback equalizer (DFE) circuit includes a first equalization path and a second equalization path. Each equalization path includes a summing node, a first latch, a second latch, a first feedback path, and a second feedback path. The first latch is configured to latch data received from the summing node. The second latch is configured to latch data received from the first latch. The first feedback path is configured to receive data from the second latch and to provide data to the summing node of the equalization path. The second feedback path is configured to receive data from the first latch and to provide data to the summing node of the other equalization path. The second feedback path provides up to a symbol interval for propagation of data between the summing nodes.

Abstract: Methods and apparatus are provided for soft-decision maximum likelihood demodulation to decode a data vector transmitted in a multiple-input multiple-output (MIMO) communications channel. Soft-decision demodulators are disclosed that implement sphere decoding to reduce complexity of demodulation while preserving optimal performance. Candidate signal values associated with the transmitted data vector may be obtained and partitioned into signal bit groups. A sphere search may be performed over the candidate signal values within a search radius value to determine a smallest distance metric for each signal bit group. The search radius value may be updated based on a current smallest distance metric for each signal bit group. A log-likelihood ratio (LLR) may be computed from the determined smallest distance metrics for each signal bit group using a soft-decision demodulator.

Abstract: An interleaved track-and-hold front-end with multiphase clocks computes and propagates unrolled decision feedback equalization results along a pipeline with the final outputs selected from one of the interleaved previous output bits with a multiplexer operating over multiple unit intervals instead of one unit interval. An n-way interleaved serializer/deserializer utilizes an n unit interval multiplexer or n one unit interval multiplexers. Pipelined decision feedback equalization allows multiple, slower multiplexers.

Abstract: A magnetic recording system includes an array of analog inputs operable to receive an array of analog signals retrieved from a magnetic storage medium, where one of the array of analog signals corresponds with a reference channel, a timing recovery circuit operable to generate a clock signal based on the analog signal for the reference channel, a number of analog to digital converters each operable to sample one of the array of analog signals based on the clock signal to yield a number of digital channels, and a joint equalizer operable to filter the digital channels to yield an equalized output.

Abstract: An apparatus for reading data includes an array of analog inputs operable to receive analog signals retrieved from a magnetic storage medium, wherein the analog inputs correspond to multiple data tracks on the magnetic storage medium, and wherein the number of analog inputs in the array of analog inputs is greater than the number of data tracks being read, at least one joint equalizer operable to filter the analog inputs to yield an equalized output for each of the data tracks being read, and at least one data detector operable to apply a detection algorithm to the equalized output from the joint equalizer to yield detected values for each of the data tracks being read.

Abstract: Systems, methods, and other embodiments associated with adaptively determining settings of a transmit equalizer are described. According to one embodiment, a method includes removing, from a signal received from a first device, a signal contribution of a transmit equalizer to produce a residual signal. The method includes generating revised tap coefficients based, at least in part, on the residual signal. The method includes providing settings that are based, at least in part, on the revised tap coefficients to the transmit equalizer in the transmitter of a second device that is across a channel on which the signal is provided.