Abstract: A PPM transmitter includes an optical clock generator for generating equally-spaced optical pulses with a sampling period T; an encoder for transforming an incoming waveform U(t) into a linear combination V(t) of U(t) and a delayed output V(t?kT) according to a rule V(t)=U(t)+aV(t?kT), where k is a positive integer, V(t) is voltage generated by the encoder and a is a coefficient; and an optical delay generator for delaying optical pulses generated by the optical clock generator in proportion to the voltage V(t), such that ?tn=bV(t), where b is another coefficient and where ?tn is the amount of delay imposed by the optical delay generator. The PPM transmitter functions with a PPM receiver for communicating data without the need to transmit or otherwise provide a clock signal. The PPM receiver decodes an original series of the delayed optical pulses Q(t) and a second series Q(t?ckT) delayed by ckT where c is a coefficient.

Abstract: Provided is a radio communication mobile station device which can reduce the number of blind decoding processes at a mobile station without increasing the overhead by report information. The device includes: a judgment unit (210) which judges a particular PUCCH to which a response signal corresponding to the downstream line data is to be allocated among a plurality of PUCCH, according to a CCE occupied by PDCCH allocated to a particular search space corresponding to a CCE aggregation size of the PDCCH to which allocation information destined to the local station is allocated among search spaces changing in accordance with the CFI value; and a control unit (211) which controls a cyclic shift amount of a ZAC sequence of the response signal and a block-wise spread code sequence according to a correspondence between CCE occupied by PDCCH allocated to a particular search space and a particular PUCCH resource, the correspondence changing in accordance with the CFI value.

Abstract: Provided is a transmitter which is small in size and operates with high efficiency and compensates a delay error with high accuracy. A signal generation section 11 outputs a PM test signal and an AM test signal. The AM test signal is inputted to a multiplier 16 via a delay adjustment section 12 and a regulator 14. The PM test signal is inputted to the multiplier 16 via the delay adjustment section 12. A power measurement section 17 measures an average power of a multiplication signal which is outputted from the multiplier 16 and outputs a measured value to a control section 18. The control section 18 determines an amplitude delay time and a phase delay time on the basis of the inputted measured value and sets the determined delay times in the delay adjustment section 12.

Abstract: A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data channels, and differential skew within a differential signal are compensated by analog circuits which are automatically tuned for best performance by observing the quality of the recovered analog signal. Oversampling is used to provide a 24-bit digital representation of the analog signal for determining the quality of the signal.

Abstract: In a sending apparatus, a storage section stores information which associates a first communication quality and a second communication quality with hierarchical modulation methods each using a plurality of channels. On the basis of the information stored in the storage section, a control section selects a hierarchical modulation method corresponding to the first communication quality which is a communication quality for a receiving apparatus and the second communication quality which is a communication quality for a receiving apparatus. A sending section maps data a destination of which is the receiving apparatus and data a destination of which is the receiving apparatus to the plurality of channels according to the hierarchical modulation method selected, and transmits the data.

Abstract: Hardware and processes are provided for efficient interpretation of multi-value signals. The multi-value signals have a first voltage range with is used to indicate multiple numerical or logical values, and a second voltage range that is used to provide control functions. In one example, the multi-value circuitry is arranged as a set of rows and columns, which may be cascaded together. The control function can be implemented to cause portions of rows, columns, or cascaded connections to be powered off, thereby saving power and enabling more efficient operation.

Abstract: A method for detecting signals in a TMDS transmission system having a channel established between a receiver and a transmitter includes separating loadings of the receiver from the channel, providing a first reference current in a first differential line of the channel, providing a second reference current in a second differential line of the channel, computing a difference between the first reference current and a current provided by the transmitter via the first differential line to obtain a first current difference, computing a difference between the second reference current and a current provided by the transmitter via the second differential line to obtain a second current difference, and determining an operating state of the transmitter according to the first current difference and the second current difference.

Abstract: Disclosed is a bits-to-symbol mapping method of 4+12+16 amplitude phase shift keying (APSK) having excellent performance against the non-linearity of a high power amplifier. According to the present invention A bits-to-symbol mapping method of 4+12+16 APSK modulation, comprising: representing 32 symbols of the 4+12+16 APSK modulation by a polar coordinate and arranging the 32 symbols by a size of ? while giving priority to a symbol having a small signal size when the size of ? of two or more symbols are same; grouping the arranged 32 symbols into 4 groups according to quadrant regions where the symbols are located; and allocating bits so that the same bits are allocated to the symbols belonging to the same region for each region with respect to each of the first to fifth bits of the symbols grouped into four regions.

Abstract: A system and method are provided for calibrating the IQ-imbalance in a low-IF receiver. A Test Signal can be generated in a mirror frequency and conveyed to the receiver. The power of the signal produced in the receiver from the conveyed Test Signal can be measured. In the absence of an IQ-imbalance, the Test Signal can be completely eliminated in the receiver and the corresponding measured power of the produced signal can be minimized. Accordingly, a two dimensional algorithm is described for calibrating a receiver and correcting the IQ-imbalance by adjusting the phase and gain difference between the I and Q channels in the receiver based on the measured power of the signal produced in the receiver.

Abstract: Methods and systems for signal quantization may include, but are not limited to: receiving a complex signal characterized by a real portion and an imaginary portion; computing a vector magnitude of a sample of the complex signal; comparing the vector magnitude of the sample to a quantization threshold value; and associating a quantized magnitude with the sample according to a comparison between the vector magnitude of the sample and the quantization threshold value.

Abstract: Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.

Abstract: A system and method for identifying minor echoes present in an input signal in the situation where a set of major echoes has already been identified from the input signal. The method includes: computing a spectrum F corresponding to a sum of the major echoes; computing a weighted power spectrum SM of the spectrum F; subtracting the weighted power spectrum SM from a weighted power spectrum PIN of the input signal to obtain a difference spectrum; performing a stabilized division of the difference spectrum by a conjugate of the spectrum F to obtain an intermediate spectrum; computing an inverse transform of the intermediate spectrum to obtain a time-domain signal; and estimating parameters one or more of the minor echoes from the time-domain signal. The echo parameters are usable to remove at least a portion of the one or more estimated minor echoes from the input signal.

Abstract: A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.

Abstract: An impulse radio communication device includes a short pulse generator configured to change a shape of an impulse to be output; a bandpass filter configured to receive the impulse and output the impulse as a wave packet; an amplifier configured to amplify an output from the bandpass filter; and an antenna configured to output the wave packet, output from the amplifier, as a wireless signal, the short pulse generator includes a control section configured to change the shape of the impulse to be output, in response to an environmental condition of a transmission path for wireless communication.

Abstract: A method of communicating on a single serial line between two devices is disclosed. The method includes combining a data stream and a clock to form a three-voltage level stream such that the third voltage level records the transitions of the clock while the serial data is either high or low. Either the first or the second device can send a combined stream on the line. The method further includes, in some embodiments, the second device driving the same voltage levels as those transmitted by the first device and the first device sensing current on the single serial line to determine that the second device has received data from the first device.

Abstract: The present invention relates to information processing technologies and discloses an encoding and decoding method and device to solve the poor decoding quality problem. The technical solution of the present invention includes: encoding each sample of an input signal to generate an encoded signal of a core layer; comparing residuals of all or a part of the samples of the input signal with encoding thresholds, where the residuals are generated by core layer encoding, and performing encoding according to comparison results to generate an encoded signal of an enhancement layer; and writing the encoded signal of the core layer and the encoded signal of the enhancement layer into a bitstream to generate an encoded signal of the input signal.

Abstract: Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.

Abstract: Provided is a signal processing device including a signal receiving unit for receiving a multilevel signal having a signal waveform that is obtained by synchronously adding an encoded signal generated based on a specific coding rule and a clock which has an amplitude larger than the encoded signal and for which the transmission speed is half that of the encoded signal, an amplitude level detection unit for detecting an amplitude level of the multilevel signal received by the signal receiving unit, a violation detection unit for detecting a bit position at which rule violation of the specific coding rule occurred, based on a change pattern of the amplitude level detected by the amplitude level detection unit, and an error correction unit for correcting a detection value of the amplitude level corresponding to the bit position detected by the violation detection unit so that the rule violation is resolved.

Abstract: Wireless devices and techniques providing improved system acquisition in an environment of multiple co-existing technologies over a common frequency band are disclosed. In one aspect, at a remote terminal, a power spectral distribution (PSD) of received signals is sequentially measured in contiguous segments of a frequency band of interest. One or more characteristics of the measured PSD is compared to at least one predetermined metric to identify the presence or absence of at least one technology type of the received signals in frequency locations across the band. A system acquisition operation is performed in accordance with the identification, such as a tailored scan of channels at locations where a desired technology is identified.

Abstract: Provided are a signal amplifying apparatus and method and a wireless transmitter using the same. The signal amplifier includes a polar coordinate converter configured to output an envelope signal and a phase signal by converting a signal to a polar coordinate, a multilevel quantizer configured to output a multilevel quantized signal by quantizing the envelope signal to multiple levels, an amplification state controller configured to control an amplification state using the multilevel quantized signal, and a power amplifier configured to amplify the phase signal according to the controlled amplification state.

Abstract: A method of processing data is provided that includes receiving a plurality of binary electronic signals and generating an optical signal by a number of lasers that is equal to or greater than the number of binary electronic signals. The optical signal is generated at one of a plurality of intensity levels, and each intensity level represents a particular combination of bit values for the plurality of binary electronic signals. The optical signal is converted into an electronic signal having the plurality of intensity levels. An apparatus for processing data is provided that includes a plurality of lasers configured to emit light at a plurality of frequencies, and a plurality of modulators configured to receive a plurality of binary electronic signals and to modulate the light emitted by the lasers. An apparatus for transmitting data is provided that includes a photo receiver and an electronic signal generator.

Abstract: Method and apparatus for generating ternary and multi-valued Gold sequences, are disclosed. Also methods to detect ternary and multi-valued sequences are disclosed. The detection can be performed by a ternary or multi-valued LFSR descrambler when the sequences are generated by an LFSR based sequence generator. A wireless system which can assign additional sequences to designated users is also disclosed. The wireless system can also transfer information to user equipment that enables methods for sequence generation and sequence detection.

Abstract: A multi-level point-to-point transmission system including at least one terminal resistor, a transmitter circuit, and a receiver circuit is disclosed. The transmitter circuit includes a first external resistor and a transmitter. The transmitter generates a first reference current according to the first external resistor and determines a current flowed through an output terminal thereof according to a transmission data and the first reference current. The receiver circuit includes a second external resistor, a third external resistor, and at least one receiver. The receiver generates a second reference current according to the second external resistor and generates a reference voltage difference according to the second reference current and the third external resistor. The receiver judges a voltage at the receiving terminal thereof according to the reference voltage difference so as to receive the transmission data correctly.

Abstract: The present invention discloses a single-wire asynchronous serial interface, and a method for transmitting commands and data through one transmission wire, wherein the transmission wire is capable of transmitting signals of three level states. The disclosed interface comprises a signal level extraction circuit receiving signals transmitted through the wire and outputting logic or functional bits according to the received signals; a clock extraction circuit generating clock signals according to the functional bits, and a memory circuit controlled by the clock signals and storing the logic bits. The disclosed method comprises: using two of the level states to represent logic 0 and logic 1, and the third of the states as a functional bit; and determining whether a group of signals is a command or data by the existence of a functional bit within the group.

Abstract: The disclosure relates to a method and apparatus for providing efficient signal transmission. Conventional linear amplifiers are most efficient when operated in compressed mode. In the compressed mode, the digital power amplifier switches between the on and off modes. A digital power amplifier operates in compressed mode only if the incoming signal is an on-off constant envelop signal. In one embodiment, the disclosure provides a method and apparatus for converting a digital baseband signal to on-off constant envelop signals for processing through binary-weighted or thermometer-weighted amplifier which are operated in compressed mode.

Abstract: Systems, apparatuses, and methods are provided for detecting corrupted data for a system having non-volatile memory, such as NAND Flash memory. In some embodiments, a non-volatile memory (“NVM”) package is provided, which can include a NVM controller and one or more NVM dies. Each NVM die can include one or more blocks, where each block can further include an array of memory cells. One or more of these memory cells can be configured as “multi-level cells” (“MLCs”). In some embodiments, in order to avoid transmitting data obtained from an improperly programmed page of a MLC, a NVM controller can be configured to detect if data obtained from the page is in fact data stored in a different page.

Abstract: An information processing device is provided that includes a signal receiving portion, an absolute value conversion portion, and an input data decoding portion. The signal receiving portion receives a signal that is encoded such that mutually distinct first and second bit values are respectively expressed by pluralities of mutually distinct first amplitude values and second amplitude values, the first and second bit values also being encoded such that the same amplitude value does not occur twice in succession and such that the polarities of the amplitude values are inverted with each cycle. The absolute value conversion portion converts into absolute values the amplitude values of the signal that has been received by the signal receiving portion. The input data decoding portion decodes the first and second bit values based on the amplitude values in the signal that have been converted into absolute values by the absolute value conversion portion.

Abstract: A system and method are shown for generation of at least one reference voltage level in a bus system. A reference voltage generator on a current driver includes at least one reference voltage level, at least one control signal, and an active device. The active device is coupled to the at least one control signal, such as a current control signal, and a selected reference voltage of the at least one reference voltage level. The active device is arranged to shift the at least one reference voltage level based on the at least one current control signal such as an equalization signal, a crosstalk signal, or the combination thereof, employed on the current driver.

Abstract: A Signal Conditioning Filter (SCF) and a Signal Integrity Unit (SIU) address the coupled problem of equalization and noise filtering in order to improve signal fidelity for decoding. Specifically, a received signal can be filtered in a manner to optimize the signal fidelity even in the presence of both significant (large magnitudes of) ISI and noise. The present invention can provide an adaptive method that continuously monitors a signal fidelity measure. Monitoring the fidelity of a multilevel signal can be performed by external means such as by the SIU. A received signal y(t) can be “conditioned” by application of a filter with an electronically adjustable impulse response g(t). A resulting output z(t) can then be interrogated to characterize the quality of the conditioned signal. This fidelity measure q(t) can be used to adjust the filter response to maximize the fidelity measure of the conditioned signal.

Abstract: An asynchronous master-slave serial communication system, a data transmission method, and a control module using the same are disclosed. The asynchronous master-slave serial communication system comprises a master control module and a slave control module. The master control module generates a check code according to an address information and a data information, and generates a data package according to the address information, the data information, the check code and the master clock signal. The slave control module generates a decoding data according to the data package and a slave clock signal, and generates the address information, the data information and the check code according to the decoding data.

Abstract: Methods and devices are provided for intersymbol interference encoding in a solid state drive. In an illustrative embodiment, an nth data signal is received as input to a processing component. An intersymbol interference signal applicable to the nth data signal is provided, based on a set of prior-written data in a data storage array and a set of intersymbol interference behavior of the set of prior-written data in the data storage array, the data storage array being communicatively connected to the processing component. The nth data signal and the intersymbol interference signal applicable to the nth data signal are combined into an intersymbol-interference-corrected encoding of the nth data signal. The intersymbol-interference-corrected encoding of the nth data signal is provided as output from the processing component.

Abstract: Some aspects of the present disclosure provide for polar modulation techniques that utilize an 180° phase shift module disposed downstream of a VCO-DCO. In some embodiments, this configuration allows a polar modulator to use the VCO-DCO to achieve small phase shifts (e.g., less than or equal to) 90°, while carrying out 180° phase shifts in the 180° phase shift module downstream of the VCO-DCO.

Abstract: A receiver (13) of user equipment, UE, (10) of a Universal Mobile Telecommunications System, UMTS, network receives a digitally encoded radio signal over a downlink (11) from a base station (12). A Digital Signal Processor, DSP, (14) of the UE (10) estimates BER of data bits of power control commands received in the signal during an out of synchronisation procedure. More specifically, the DSP (14) samples the amplitude with which the data bits are received and determines a ratio of functions of one or more moments of the sampled amplitudes. The DSP (14) then compares the determined ratio to one or more values of BER for different ratios in a look-up table to estimate BER.

Abstract: A transmitter for use in digital radio communications systems includes: a bit corrector controls bit arrangement in such a manner that a code having high significance, out of multiple codes obtained by coding, is allocated with high priority to a bit having a tendency that the likelihood enlarges at the time of symbol decision on a receiver; a multi-level modulator allocates the code to the multiple bits in accordance with a predetermined symbol arrangement; and a symbol arrangement controller controls the symbol arrangement from equal distance arrangement to another arrangement in accordance with a ratio of the codes different in significance. To control symbol arrangement increases the effect of bit correction and improves an error rate on the receiver.

Abstract: A multilevel QAM demodulator includes a phase difference calculation unit calculating a phase difference signal based on the common phase signal and orthogonal signal after the phase rotation compensation, a phase shift amount calculation unit calculating a phase shift amount indicating a degree of a phase shift based on the common phase signal and orthogonal signal after the phase rotation compensation and phase noise compensation, and a correction unit correcting the phase difference signal based on the phase shift amount. A phase rotation is performed for the phase noise compensation based on the phase difference signal corrected by the correction unit.

Abstract: This disclosure relates systems and methods for a high bandwidth modulation and transmission of communication signals.

Abstract: A communication system including a first device and a second device that are connected by a single signal line in which serial communication is performed by using a first level, a second level and a middle level between the first level and the second level, wherein the first device transmits a clock to the second device by repeating the first level and the middle level; the second device transmits information to the first device based on whether the second device outputs the second level during each period of the middle level in the clock; and when the second device does not transmit information, the first device transmits information to the second device based on whether the first device outputs the second level during each period of the middle level in the clock.

Abstract: Hardware and processes are provided for efficient interpretation of multi-value signals. The multi-value signals have a first voltage range with is used to indicate multiple numerical or logical values, and a second voltage range that is used to provide control functions. In one example, the multi-value circuitry is arranged as a set of rows and columns, which may be cascaded together. The control function can be implemented to cause portions of rows, columns, or cascaded connections to be powered off, thereby saving power and enabling more efficient operation.

Abstract: The present invention relates to a modulation and demodulation method of minimizing an error rate and applying it to a differential operation modulo 4. A modulation apparatus includes a Gray coding circuit 101 to which data of (2n+1) bits are inputted (where “n” is an integer more than 1) and which encodes 2 bits of an input signal of (2n+1) bits to a Gray code as a signal for allowing four quadrants to be identified, an encoding circuit 102 that encodes 3 bits of the input signal of (2n+1) bits as a signal indicating any one of eight subgroups provided in each of the four quadrants so that an average Hamming distance between adjacent subgroups within its quadrant becomes a minimum, and a mapping circuit 104 that maps binary data encoded by the Gray coding circuit 101 and the encoding circuit 102 on the four quadrants.

Abstract: The present invention maps coded bits that have been output from a low density parity check coder 11 onto specific bit positions on a 16 QAM constellation diagram in accordance with a column weighting of the coded bits.

Abstract: A polarity independent differential data transceiver receives a differential voltage signal and outputs a first logic state when the differential voltage signal is in a positive voltage differential range and/or when the differential voltage signal is in a corresponding negative differential voltage range. The differential data transceiver will output a second logic state in response to receiving a voltage differential signal that is in an intermediate differential voltage range near zero between the positive differential voltage range and the corresponding negative differential voltage range.

Abstract: In a provided information processing device, a first information processing module, within its transmission time segment, transmits an encoded signal in which mutually distinct first and second bit values are respectively expressed by pluralities of mutually distinct first amplitude values and second amplitude values, the same amplitude value not occurring consecutively and the amplitude value polarity being inverted with each cycle. Within a transmission time segment for a second information processing module, the first information processing module transmits a clock signal that corresponds to the cycle at which the polarity is inverted.

Abstract: An apparatus for transmitting a signal in a semiconductor integrated circuit includes a multilevel transmission control block that outputs a plurality of bits of an input signal in serial or parallel according to whether a multilevel transmission operation is performed or not, and a signal processing block that selectively performs the multilevel transmission operation according to a form of the input signal, which are output in serial or parallel from the multilevel transmission control block.

Abstract: Systems, methods, and computer readable media for fractional pre-emphasis of multi-mode interconnect are disclosed. According to one aspect, the subject matter described herein includes a method for fractional pre-emphasis of multi-mode interconnect. Multiple bits of binary data are periodically received. For each period, the multiple bits of binary data are encoded into multiple scalar values, each value representing a level of an analog signal to be output over a multi-mode interconnect system during the current period. Multiple analog signal outputs are generated corresponding to multiple scalar values, each signal output being driven to a level according to its corresponding scalar value. For each representative scalar value, a difference between the scalar value generated during the current period and the scalar value generated during the previous period is determined, and a pre-emphasis signal that is proportional to the difference is generated.

Abstract: A method and apparatus for signal processing which enable data compression and recovery with high transmission efficiency are disclosed. Data coding and entropy coding are performed with correlation and grouping is used to increase coding efficiency. A method for signal processing according to this invention, the method includes decapsulating the signal received over an Internet protocol network, obtaining a pilot reference value corresponding to a plurality of data and a pilot difference value corresponding the pilot reference value from the decapsulated signal and obtaining the data using the pilot reference value and the pilot difference value.

Abstract: Provided are a data transmitting device transmitting data through a delay insensitive data transmitting method and a data transmitting method. The data transmitting device and the data transmitting method use the delay insensitive data transmitting method supporting a 2-phase hand shake protocol. During data transmission, data are encoded into three logic state having no space state through a ternary encoding method. According to the data transmitting device and the data transmitting method, data are stably transmitted to a receiver regardless of the length of a wire, and provides more excellent performance in an aspect of a data transmission rate, compared to a related art 4-phase delay data transmitting method.

Abstract: A differential signal output device is disclosed that outputs transmission data as a differential signal. The device includes a first differential signal generation circuit that amplifies a signal representing the transmission data and generates the differential signal from the amplified signal; a dummy data generation circuit that is synchronized with a reference clock of the transmission data and generates dummy data that change only in a bit where the transmission data do not change; and a second differential signal generation circuit that amplifies a signal representing the dummy data and generates another differential signal from the amplified signal.

Abstract: In a communication system, a timing-dependence cancelling module is included for cancelling timing-dependence of a transmission signal, so as to render a timing-dependent signal be capable of being utilized on communication systems. Besides, updating an echo cancelling parameter by applying an error difference variable and a data difference variable, or by directly decreasing a step-size coefficient, may also fulfill the purpose of reducing or eliminating timing dependence in a transmission signal of a communication system.

Abstract: A preprocessing unit samples and digitalizes analog signal. A differential operation unit delays digitalized signal for a predetermined period and differentiates delayed signals. A correlation unit correlates differentiated signal with a plurality of predetermined PN code sequences. A setting unit includes a shift register having a plurality of storage locations for shifting the correlation values and sequentially storing shifted correlation values at the storage locations, respectively, a detector including the determination slots for detecting the storage location of the maximum value, and a slot setter for comparing the storage location of the maximum value from the detector with the predetermined reference storage location and shifting the determination slots by the difference therebetween. A demodulation value estimation unit estimates, as a demodulation value of the received analog signal, a symbol of a PN code sequence corresponding to the maximum value from the shifted determination slots.

Abstract: The present invention provides a digital signal processing device that considerably reduces a return noise generated in a processing result signal in specific signal processing without wastefully increasing the processing load. There is provided a digital signal processing device that executes specific signal processing under which a return noise is generated in a processing result signal which includes an up-sampling processing unit that performs the up-sampling processing for a digital signal with a predetermined up-sampling rate to generate an up-sampling signal, a specific signal processing unit that performs the specific signal processing for the up-sampling signal generated by the up-sampling processing unit to generate the processing result signal, and a down-sampling processing unit that performs the down-sampling processing for the processing result signal generated by the specific signal processing unit with a predetermined down-sampling rate to generate a down-sampling signal.