Abstract: A system and method for EVM self-testing a communication device is provided including receiving (305) a complex waveform, sampling (310) first and second sample voltages from the complex waveform, selecting (315) first and second ideal voltages from I- and Q-arrays, and determining (320) an error vector by comparing the first and second sample voltages with the first and second ideal voltages for a desired number of comparisons (N). The first ideal voltage corresponds with the first sample voltage, the second ideal voltage corresponds with the second sample voltage, and the I- and Q-arrays are derived from a conversion of a bitstream to the complex waveform.

Abstract: Methods, systems, and apparatuses, and combinations and sub-combinations thereof, for down-converting an electromagnetic (EM) signal are described herein. Briefly stated, in embodiments the invention operates by receiving an EM signal and recursively operating on approximate half cycles (½, 1½, 2½, etc.) of the carrier signal. The recursive operations can be performed at a sub-harmonic rate of the carrier signal. The invention accumulates the results of the recursive operations and uses the accumulated results to form a down-converted signal. In an embodiment, the EM signal is down-converted to an intermediate frequency (IF) signal. In another embodiment, the EM signal is down-converted to a baseband information signal. In another embodiment, the EM signal is a frequency modulated (FM) signal, which is down-converted to a non-FM signal, such as a phase modulated (PM) signal or an amplitude modulated (AM) signal.

Abstract: In order to compensate for a frequency offset or a change in the phase of the transmission channel over time during mobile radio transmission of data symbols, the data symbols are transmitted by way of carrier-frequency, modulated data bursts. Sample values of the received signal, which are known in advance and correspond to first and second symbols, are evaluated in order to estimate the frequency offset or the change in the phase of the transmission channel over time. These first and second symbols are transmitted with a defined phase angle by way of the data burst, and are arranged separated from one another in the data burst. Edge symbols in a data burst are advantageously used as first and second symbols, or as a symbol pair, for estimation.

Abstract: A receiver uses a wideband intermediate frequency (IF) in the analog domain and performs low IF down-conversion in the digital domain, using low-power, high-speed, high resolution analog-to-digital converters. The receiver can be integrated into an integrated circuit as one of several receivers. Such an integrated circuit may include multiple transmitters using adaptive non-linear modeling pre-distortion. The non-linear modeling may include memory. Imbalance in intermediate frequency in-phase and quadrature signals may be corrected in the digital domains. DC offsets in the intermediate signal may be corrected in both analog and digital domains. In one instance, the receiver provides a feedback receiver for the adaptive pre-distorter in a transmitter on the integrated circuit.

Abstract: A receiver is a Digital Video Broadcasting-Terrestrial/Handheld (DVB-T/H) receiver. The DVB-T/H receiver comprises a fast fourier transform (FFT) operative on a signal for providing an FFT output signal comprising a number of samples; a spectrum shifter for reordering the samples in the FFT output signal to provide a spectrum shifted signal; and a phase corrector for estimating a phase error from the FFT output signal and for correcting a phase of the spectrum shifted signal in accordance with the estimated phase error.

Abstract: A method and apparatus for correcting the phase and gain of data associated with a constellation pattern of a plurality of received individual symbols. Each symbol is divided into real and imaginary symbol components. The signs of the real and imaginary symbol components of each symbol are determined and used as a basis for determining whether the symbol is associated with a first or third quadrant of the constellation pattern or a second or fourth quadrant of the constellation pattern. The absolute values of the real and imaginary symbol components are determined and used to create a first sum and a second sum. A phase adjustment value ? and a gain adjustment value G are derived from the first and second sums, and are used to create a complex number. Each of the received individual symbols is multiplied by the created complex number to provide corrected constellation pattern data.

Abstract: Multipath components of signals transmitted through time-varying digital radio channels are received with individual delays, and signals through a given channel comprise a code identifying that channel. A delay profile indicating a magnitude (Y) for delay values in a search window is calculated repetitively for known channels; the delays of multipath components for known channels estimated; a signal strength indicator calculated; and a search for new multipath components not already estimated performed at regular time intervals. When a new multipath component is found, its identification code is compared to the codes of the known channels. If the code of the new component is identical to the code of a known channel, a delay profile and a signal strength indicator is calculated for a window transposed to include the new multipath component. In this way as many multipath components as possible are included in the search window for a new cell.

Abstract: A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

Abstract: Embodiments of a method and an apparatus for detecting multiple complex-valued symbols belonging to discrete constellations. The method and apparatus is a detector that finds a closest vector, or a close approximation of it, to a received vector. The invention also gets (optimally, in case of two transmit sources) or closely approximates (for more than two transmit sources) the most likely sequences required for an optimal bit or symbol a-posteriori probability computation. Also part of the present invention is represented by Also embodiments of a method and an apparatus to determine a near-optimal ordering algorithms for the aforementioned purpose. The method and apparatus achieves optimal performance for two transmit antennas and achieves near-optimal performance for a higher number of antennas, with a lower complexity as compared to a maximum-likelihood detection method and apparatus. The method and apparatus are suitable for highly parallel hardware architectures.

Abstract: A second-order Volterra filter has a quadratic section including a plurality of multiplication units that multiply a first input signal with a second input signal. One of the multiplication units employs a signal not delayed from the first input signal, as the second input signal. A remaining one of the multiplication units employs a signal delayed a preset time from the first input signal, as the second input signal. The one of the multiplication units includes a multiplier that multiplies the signal output from the one of the multiplication units and a signal output from each of one or more delay units, each with a preset coefficient. A step gain parameter for updating each preset coefficient of a multiplier of the remaining one of the multiplication units is twice a step gain parameter for updating each preset coefficient of the multiplier of the one of the multiplication units.

Abstract: An IQ mismatch correction circuit comprises: a correction circuit which performs a correction process to I-phase and Q-phase input signals by using one pair of first- or higher-order digital filters; two or more control circuits which independently generate two or more control variables to derive two or more coefficients of transfer functions of the digital filters; and one or more pairs of analyzing filters which change frequency characteristics of the corrected I-phase and Q-phase output signals so that the frequency characteristics is different from those of the original signals. The first control circuit measures a temporally averaged IQ phase mismatch state between the I-phase and Q-phase output signals. The second control circuit measures a temporally averaged IQ phase mismatch state between output signals on I-phase and Q-phase sides of one pair of analyzing filters. These states are fed back to the digital filters as first and second control variables, respectively.

Abstract: The present invention relates to wireless communications and is particularly applicable to devices and modules for correcting errors introduced to a wireless signal after its transmission. An equalizer is provided which compensates for undesirable effects on received radio signals introduced by either signal processing or by the transmission medium. In operation, the equalizer multiples the complex received signal with a complex corrective signal that compensates for these effects. A tap corrective signal corrects for time-varying channel effects (i.e. channel distortions), a timing tracking signal corrects for carrier frequency offset errors, and a phase tracking signal corrects for sampling frequency offset errors.

Abstract: A real-time digital quadrature demodulation method and device for the ultrasonic imaging system are disclosed in this invention. In addition to a multiplying step and a filtering step, the method further comprises a sine and cosine table generating step for generating the sine and cosine table in real time, and a filter parameter generating step for generating corresponding filter parameters in real time to filter signals from the multipliers. The device comprises two multipliers, two filters, a sine and cosine table generating module, a filter parameter generating module, and two parameter memories. The real-time digital quadrature demodulation method and device for the ultrasonic imaging system according to the invention are capable of effectively saving the storage resource, and are easily controllable.

Abstract: A communications system is provided that includes a detector that has I/Q mismatch, a calibration circuit that estimating a phase and/or an amplitude mismatch of the detector, and a compensation circuit that uses the estimated phase and/or amplitude mismatch to mitigate the effects of the amplitude and/or phase mismatch. An IQ-modulated signal produced by the I/Q-modulator can be communicated over a loop back connection to the detector of the communication system. The calibration circuit can estimate the I/Q mismatch for the IQ-modulator and can provide the estimated values to a pre-compensation circuit. In one aspect, I/Q mismatch in the IQ-modulator of a communication system can be determined using a spectrum analyzer. Power measurements can be used to compute the amplitude mismatch and the phase mismatch of an IQ-modulator.

Abstract: Exemplary embodiments of the present invention provide an equalizer combined with a decoder and a method of updating filter coefficients. The method may include calculating output error signals ek, multiplying the output error signals by a parameter, obtaining a partial value by multiplying a delayed decoder decision stored in a filter delay line corresponding to an i-th filter coefficient by the result obtaining a partial value by multiplying a constant by a feedback coefficient and obtaining an updated value by adding the two partial values.

Abstract: A radio receiver for receiving digital radio signals and a method for receiving digital radio signals are used for undertaking the conversion of digital audio signals to a preset clock pulse rate or clock pulse regulation. The digital asynchronous sampling rate conversion has an input buffer, a control system, a coefficient memory, an accumulator and an interpolator. The output signals of the sampling rate conversion are either passed on for playback or switched to a multimedia bus. The radio receiver and the method are suitable for also converting digital audio signals from sound carriers to a preset clock pulse rate.

Abstract: Provided is an apparatus and method for analyzing identification (ID) signals by converting radio frequency (RF) signals which are transmitted with an ID signal added thereto by a transmitting part, e.g., a plurality of transmitters or repeaters, into signals of a desired band; creating ID signals that are identical to the ID signals added to the RF signals; calculating correlation values between the converted signals and the created ID signals based on partial correlation; and extracting channel profile of multi-path signals caused by a channel between the transmitting part and the ID signal analyzing apparatus from the correlation value. The technology of the present research is applied to broadcasting and communication.

Abstract: A process of correction of the spectral inversion for a receiver in a digital communication system: the process allows the reception in the receiver of a training sequence presumably known according to a modulation of type ?/2 BPSK or MDP2. The process includes the following steps: Demodulating of the training sequence; Calculating of the differential correlation on a set of N received samples (Rn) and presumably sent (Sn) to generate a result; Using the result to detect the beginning of the frame and to order a spectral inversion in the chain of reception of the aforementioned receiver before launching the detection of the beginning of the frame. A receiver to process automatically the spectral inversion is also described.

Abstract: A demodulation circuit can perform a capturing operation although a frequency error is large. A phase comparator out puts a predetermined value other than 0 as a determination result of a phase error when a phase error of a carrier wave is large and a signal point is located at a predetermined position. A loop filter outputs a negative minimum value to an integrator when an integrated value of a determination result reaches a positive maximum value of a limiter. Thus, when a phase error is large, a value changing from a negative minimum value to a positive maximum value is output from the loop filter, thereby realizing a broad synchronous capture range.

Abstract: In an OFDM receiving apparatus for receiving a signal that has undergone Orthogonal Frequency Division Multiplexing (OFDM) and applying FFT processing to the receive signal to demodulate transmit data, an OFDM symbol comprising a fixed number of items of sample data is extracted from a receive signal, a position at which FFT processing of the OFDM symbol starts is shifted based upon the state of multipath and FFT processing is executed from the position to which the shift has been made. For example, a channel estimation value is obtained from result of FFT processing of known data contained in the receive signal, a multipath delay profile is obtained by applying FFT processing to this channel estimation value, and the position at which the FFT processing begins is decided based upon the position of a path for which power is maximized among the delay profiles.

Abstract: Method and device for modulating a signal comprising data symbols and reference symbols, characterized in that it comprises at least one step (3) wherein semi-pilot symbols are introduced that transport less information than the symbols customarily used but enough to obtain decisions decided during a decoding step (9), the semi-pilot symbols being disposed between the data symbols and the reference symbols.

Abstract: A configurable all-digital coherent demodulator system for spread spectrum digital communications is disclosed herein. The demodulator system includes an extended and long-code demodulator (ELCD) coupled to a traffic channel demodulator (TCD) and a parameter estimator (PE). The demodulator also includes a pilot assisted correction device (PACD) that is coupled to the PE and the TCD. The ELCD provides a code-demodulated signal to the TCD and the PE. In turn, the TCD provides a demodulated output data signal to the PE. The PACD corrects the phase error of the demodulated output data based on an error estimate that is fed forward from the PE. Accumulation operations in the ELCD, TCD, and PE are all programmable. Similarly, a phase delay in the PACD is also programmable to provide synchronization with the error estimate from the PE.

Abstract: Methods and systems for determining a Log-Likelihood Ratio (LLR) corresponding to each bit of a symbol are provided. The symbol comprises a predefined number of bits based on a predetermined constellation. The methods and systems include expanding the predetermined constellation. The predetermined constellation comprises a plurality of constellation-points wherein each constellation-point has a unique X co-ordinate and Y co-ordinate. Also, the expanded predetermined constellation further comprises points corresponding to each combination of the X co-ordinate and the Y co-ordinate of the constellation-points. The methods and systems further include calculating the LLR corresponding to each bit of the symbol based on the expanded predetermined constellation.

Abstract: A system on a chip integrated circuit includes a first digital module and a second digital module such that the second digital module generates an output during the predetermined period that is based on an output of the first digital module generated during a prior predetermined period. A digital clock generator generates a base clock signal having a plurality of first digital clock cycles over a predetermined period and a second digital clock signal having a plurality of second digital clock cycles over the predetermined period. The plurality of first digital clock cycles are substantially interleaved with the plurality of second digital clock cycles over the predetermined period.

Abstract: Embodiments of the present invention include systems and methods of control using a single wire. The systems and methods presented allow sending or receiving commands and data through a single wire. In one embodiment, commands and data are received by the control system through a single terminal. In another embodiment, commands and data are received and transmitted from the control system through a single terminal.

Abstract: An apparatus and method is described that provides optimal D-PSK demodulation based on the distribution of phase differences between successive D-PSK symbols. A plurality of D-PSK data symbols are received, and each symbol is characterized by a real component and an imaginary component. An angle of correlation between any two successive symbols is calculated. A variance of correlation angles is obtained by using data symbols or pilot symbols, if available. The probability of the correlation angle being each of possible phase difference according the D-PSK constellation is then determined. From the probabilities of the particular correlation angle, a probability of each input bit being a “0” or “1” is determined.

Abstract: A bit/power loading method in an adaptive modulation-based multicarrier communication system computes ratios of modulation mode values to transmission power values sub-channel-by-sub-channel, selects a combination of sub-channels in which a sum of the ratios is maximized for a total number of bits to be simultaneously transmitted, and transmits signals in modulation modes corresponding to ratios of modulation mode values to transmission power values associated with the selected sub-channels. Because the bit/power loading method selects a combination of sub-channel modulation modes with the minimum total transmission power for a given number of bits on the basis of transmission power in each sub-channel modulation mode, the bits can be transmitted at the minimum transmission power in a given environment.

Abstract: A dynamic DC offset removal apparatus and a dynamic DC offset removal method capable of accurately estimating a change position of a dynamic DC offset and a DC offset value before the change and a DC offset value after the change, thereby carrying out equalization processing on a reception signal whose dynamic DC offsets are removed, and improving a bit error rate characteristic.

Abstract: A device for minimizing group delay mismatch in a quadrature receiver (402) having an in-phase channel and a quadrature-phase channel. The device includes a microprocessor (465) for determining an I/Q phase imbalance between digital signals on an in-phase channel and digital signals on a quadrature-phase channel, and for calculating a group delay mismatch between the in-phase channel and the quadrature-phase channel, and a group delay equalizer (426). The group delay equalizer includes a delay line (505 and 605) for delaying one of the in-phase channel and the quadrature-phase channel by one of a plurality of delays, based on an amount of group delay mismatch.

Abstract: A method of multi-user detection in a given uplink and downlink time slot in a software-defined receiver which includes filtering and sampling a received signal; forming a block-banded matrix A of the sampled signals; and solving {circumflex over (d)}=T?1y, where T=(AHA), y=AHx. The methods of solving for the matrix T includes a) computing Cholesky factors of the matrix T by approximating using the block-banded property of the matrix T and A; b) Schur decomposition for Cholesky factors of the matrix T and approximating the lower triangular Cholesky factor matrix R using block Toeplitz property of matrix T; or c) Fourier Transformation.

Abstract: The invention relates to a device for demodulating an input signal containing information being conveyed by phase modulation of a carrier wave. A transmitter generates a signal controlling a phase variation in the carrier wave, for each symbol having N cycles, N being an integer strictly greater than 1. The phase variation stretches on the receiver side over n cycles, n being an integer greater than 1 and less than N. The device generates a single pulse for each symbol received suited to generate the leading edge of the pulse corresponding to the symbol considered after a constant duration from the moment the symbol considered starts; and generates the trailing edge of the pulse considered at a moment the phase shift corresponding to the symbol considered has to be measured. Conversion means generate an output signal with a voltage varying as a function of the duration of the pulse produced.

Abstract: A User Equipment (UE) receives and samples communication signals, where the communication signals have a time frame format, a transmission chip rate and a synchronization code associated with a time slot that includes a midamble that indicates a modulation of the synchronization code where a specified modulation of received synchronization codes identifies the timing for a timeslot in which data is to be received. The UE preferably includes a synchronization code determination circuit, a midamble determination circuit, and a phase modulation sequence detection circuit operatively associated with the midamble determination circuit. The UE can be configured for use with the low chip rate option of the Third Generation Partnership Project (3GPP) Universal Mobile Telecommunication System (UMTS) standards that employ a predefined set of downlink SYNC codes that point to midambles which indicate SYNC code modulation sequence to enables reading of data in a subsequent Broadcast Channel (BCH) message.

Abstract: A method of decoding a GPS carrier signal comprising: (A) receiving a phase modulated GPS signal by using a GPS antenna; (B) extracting a GPS data from the received phase modulated GPS signal; and (C) computing a total probability of a current GPS data bit being “one” or “zero” at a GPS time epoch by using a decoding algorithm.

Abstract: An orthogonal frequency division multiplexing (OFDM) demodulator demodulates an OFDM signal constituted by OFDM symbols each including at least an effective symbol and a scattered known signal. The OFDM demodulator includes a Fourier transform performing unit, a known signal extracting unit, a time dimension interpolation unit, a delay spread generating unit, a frequency dimension interpolation unit, and a waveform equalizing unit. The delay spread generating unit employs a time difference between a time point for a starting position of the Fourier transform operation performed by the Fourier transform performing unit and a time point at which a latest arriving path arrived as the delay spread.

Abstract: A communications receiver receives a received continuous phase modulation (CPM) signal having an original modulation index of h and includes a filter, a continuous phase reconstructor using phase unwrapping, and a modulation index scaler for generating a reconstructed CPM signal having a scaled modulation index H from the received CPM signal having a small modulation index h, with the scaled modulation index H preferably being greater than the original modulation index h, so that, the transmitted CPM signal occupies a narrow bandwidth, yet, during reception, the reconstructed CPM signal with the high modulation index H can be reliably data demodulated for improved performance with reduced demodulation complexity.

Abstract: In a radio-controlled device for measuring time, a demodulating unit demodulates the time information from the received electric signal based on amplitude information of the target radio wave. The amplitude information is obtained from in-phase and quadrature-phase components of the target radio wave. A phase calculator calculates phase data associated with a phase of the target radio wave based on the in-phase and quadrature-phase components. A variability calculator calculates a variability of the phase data of the target radio wave relative to a reference phase. The reference phase changes at a constant rate in time according to a frequency error. The frequency error is contained in the reference signal relative to a frequency of the target carrier wave. A reception determining unit determines whether reception of the radio-controlled device is good based on the calculated variability.

Abstract: This invention provides a receiver for use in a SDAR system which includes a receiving unit having satellite signal detection means for detecting a first transmit signal transmitted from a first communication satellite and a second transmit signal transmitted from a second communication satellite, the first transmit signal produced when the transmitter modulates a primary data stream with a secondary data stream on a first carrier wave associated with the first communication satellite and the second transmit signal produced when the transmitter modulates the primary and secondary data streams on a second carrier wave associated with the second communication satellite, and an encoder re-encodes the primary and the secondary data on a third carrier wave, forming a third transmit signal which is re-transmitted to a receiver using a terrestrial repeater. This invention also provides a method of receiving transmitted data.

Abstract: Apparatus and methods for data demodulation in FM-FSK communication systems may include comparing the power spectral density (PSD) of the received frequency spectrum with that of the previously received samples using digital signal processing on a multi-sample message. A narrow band FM-FSK receiver may include a filter configured to pass FM signal components of a predetermined signal band, a memory configured to store the filtered signal component, and a DSP operably connected to the filter and the memory. The DSP may be configured to output a digital signal based upon a comparison of successive DSP calculated frequencies associated with a peak power of a power spectrum density (PSD) of successive samples of the filtered multi-sample message.

Abstract: Various embodiments provide a Phase Interpolator (PI) that receives input clocks, and outputs intersymbol interference-equalized, phase-shifted output clocks. In one embodiment, the Phase Interpolator comprises two PI Conditioners and a PI Mixer. In one embodiment, a PI Conditioner receives input clocks and is controlled by a different phase-shifted input clock by using a suitable circuit element, such as a flip-flop. Collectively, the input clock-controlled PI Conditioner and Mixer act in concert to control the band limiting effect of the PI Conditioner which, in turn, equalizes intersymbol interference.

Abstract: A phase error correction circuit includes a complex phase rotator for multiplying an input VSB (vestigial-sideband) signal by a phase correction signal and outputting a resultant signal, a specific frequency component elimination filter for eliminating a specific frequency component from the signal output from the complex phase rotator and outputting a resultant signal, a waveform equalizer for performing waveform distortion correction to the signal output from the specific frequency component elimination filter and outputting a resultant signal and a phase correction signal generator for detecting a phase error based on the signal output from the waveform equalizer and outputting a complex signal corresponding to the detected phase error as the phase correction signal.

Abstract: A delay-line demodulator for demodulating a differential quadrature phase shift keying (DQPSK) signal is provided. The demodulator includes two Mach-Zehnder interferometers individually comprising two waveguides having different lengths therebetween and through which a light signal branched from the DQPSK signal propagates, respectively. A phase of the light signal propagating at one of the waveguides is delayed as compared to a phase of the light signal propagating at another one of the waveguides, wherein a divergence amount of polarization is adjusted by driving sets of heaters that are facing each other and sandwiching a half wavelength plate therebetween.

Abstract: An apparatus and method for adaptively correcting I/Q imbalance, which is used in a receiver for correcting a received I/Q imbalanced signal to thus eliminate the I/Q imbalance. First, an interference amount caused by interference from an imbalanced in-phase signal to an imbalanced quadrature-phase signal is computed and accordingly subtracted from the quadrature-phase signal, so that a corrected quadrature-phase signal without phase imbalance is obtained. Next, a power of output in-phase signal, a power of output quadrature-phase signal, and a target are compared to thus determine an in-phase scaling factor and a quadrature-phase scaling factor. Finally, the imbalanced in-phase signal is multiplied by the in-phase scaling factor to thus obtain the output in-phase signal, and the corrected quadrature-phase signal is multiplied by the quadrature-phase scaling factor to thus obtain the output quadrature-phase signal.

Abstract: Aspects of a method and system for a fast-switching Phase-Locked Loop using a Direct Digital Frequency synthesizer may include generating a second signal from a first signal by: frequency translating an inphase component of the first signal utilizing a filtered fast-switching oscillating signal generated using at least a direct digital frequency synthesizer (DDFS), and frequency translating a corresponding quadrature component of the first signal utilizing a phase-shifted version of the generated and filtered fast-switching oscillating signal. The inphase and quadrature components of the first signal may be multiplied with the filtered fast-switching oscillating signal and a phase-shifted version of the filtered fast-switching oscillating signal, respectively.

Abstract: A composite data detector having first and second data detectors. The second detector of the invention starts in a known state and only runs as long as is necessary before being switched off and handing control back over to the smaller detector. Therefore, the composite data detector of the invention consumes less power than the known composite data detector and estimates bits with higher accuracy.

Abstract: Various embodiments are disclosed relating to a wireless transceiver. In an example embodiment, a wireless transceiver may include a transmitter adapted to output a signal at an image frequency (e.g., a simulated image) for a channel during a first mode (e.g., calibration mode) of operation. The wireless transceiver also includes a receiver adapted to receive, via loopback from the transmitter, the (e.g., simulated) image frequency signal and to determine digitally a receiver in-phase/quadrature-phase (I/Q) signal calibration adjustment based on the (simulated) image frequency signal to improve a match in amplitude and a predetermined phase shift between I and Q signals of the receiver during the first (e.g., calibration) mode of operation. The I/Q calibration adjustment may be applied to received signals during a second mode (e.g., operation mode) of operation to improve image rejection.

Abstract: The present invention relates to receiver equipment with AC-coupled receiver circuits and AC coupling filters. A switch connected between a first stage and a second stage among the receiver circuits is adapted to switch from a high coupling corner frequency, for rapid settling of a signal during preparation of data reception, to a low corner frequency, for low signal distortion during data reception. The receiver circuits are adapted to use known properties in the signal to perform the switch at a time when the short term DC-components of the signal are as low as possible.

Abstract: A receiver (300) includes a first mixing digital-to-analog converter (DAC) (336, 332), a second mixing DAC (338, 334), a direct digital frequency synthesizer (DDFS) (302), a phase correction circuit (340), a selectable load (306) and a magnitude correction circuit (350). The first mixing DAC (336, 332) includes a first input for receiving an input signal, a second input for receiving a digital first local oscillator (LO) signal and an output. The second mixing DAC (338, 334) includes a first input for receiving the input signal, a second input for receiving a digital second local oscillator (LO) signal and an output. The DDFS (302) is configured to provide the first and second LO signals, which are quadrature signals. The phase correction circuit (340) is configured to provide a phase correction signal to a control input of the DDFS (302). The first selectable load (306) includes an input coupled to the output of the first mixing DAC (336, 332) and a control input.

Abstract: A method for correcting a soft decision value includes: demodulating a reception signal, which is coded by an error correction code and modulated in order to represent one or multiple bits with one symbol; generating the soft decision value, which is used in decoding of the error correction code; multiplying the soft decision value by a weight factor to correct the soft decision value; estimating an amplitude of the reception signal in every predetermined measurement time period; and variably setting the weight factor in a symbol unit in accordance with an estimating result so that a corrected soft decision value approaches to a predetermined amplitude range.

Abstract: A pulse modulator has a subtraction stage that produces a control error signal from the difference between a complex input signal and a feedback signal. A signal conversion stage converts the control error signal to a control signal. The control signal is multiplied by a complex mixing signal at the frequency ?0 in a first multiplication stage. At least one of the real and imaginary parts of the up-mixed control signal is then quantized by a quantization stage to produce a real pulsed signal. The pulsed signal is then employed to produce the feedback signal for the subtraction stage in a feedback unit. The pulse modulator according to the invention allows the range of reduced quantization noise to be shifted toward a desired operating frequency ?0.

Abstract: The present invention is related to a partially overlapped single-carrier crosstalk signal cancellation method and an apparatus using the same. For this purpose, the present invention provides a crosstalk canceller including a pre-processor for frequency down-shifting an input signal, a crosstalk signal cancellation module for canceling the crosstalk signal by dividing the input signal by an interpolation ratio, a post-processor for converting an output of the crosstalk signal cancellation modulation into a passband signal, and an error feedback processor for performing a decimation operation on a residual crosstalk signal and feeding backing the decimated residual crosstalk signal to the crosstalk signal cancellation module.