Abstract: A repeated preamble bit or symbol pattern such as for a binary phase shift keyed (BPSK) communications signal is received within a modem. An initial frequency offset and phase error estimate is generated by processing a Fast Fourier Transform (FFT) that detects the repeated preamble pattern for a block of samples within the communications signal. Two halves of the block of samples are correlated with a plurality of different BPSK shifted sequences to obtain a symbol timing alignment based on the shifted sequence providing the maximum correlation value. A frequency offset estimate is iteratively updated an N number of times using the shifted sequence providing the maximum correlation value to refine an acquisition estimate of the frequency offset and phase error of the received communications signal.

Abstract: A communications device includes a signal input for receiving signals such as a binary phase shift keyed (BPSK) communications signal having a repeated preamble bit or symbol pattern. A modem processes the communications signal and includes a demodulator and processor that generates an initial frequency offset estimate and phase error estimate by processing a Fast Fourier Transform (FFT) that detects the repeated preamble pattern for a block of samples within the communications signal, correlates within a start of message correlator to search for a start of message sequence and correlates different phases of the repeated preamble pattern within training correlators for reducing false detections of the start of message. Radio circuitry is operative with the modem for processing communications data obtained from the communications signal.

Abstract: A method of controlling a digital demodulator (922) coupled to an equalizer (930) includes the steps of generating an equalizer value (930A), filtering (944) the equalizer value (930A) to obtain a post filter output, subtracting the equalizer output signal (930C) from the decoded data (930D) and generating an error value (924A). The post filter output is correlated (948) with the error value (924A) to obtain a correlated value (74A). A control signal is developed from the correlated value and is used to adjust the digital demodulator (922).

Abstract: An analog video receiver implemented in an integrated circuit device. The analog video receiver includes first and second mixing circuits to generate a complex baseband signal by mixing a carrier-frequency analog video signal with respective sinusoids of a quadrature sinusoid pair; and a filtering circuit to subtract a scaled complex conjugate of the complex baseband signal from the complex baseband signal.

Abstract: An apparatus for demodulating a modulated signal comprises an analog to digital converter (2, 12) for converting an analog modulated input signal to a digital signal. The analog to digital converter is arranged to sample the input signal at a predetermined sampling rate. A digital down converter (4, 14) then receives the digital signal at the sampling rate. The digital down converter has an associated digital intermediate frequency and reduces the frequency of the digital signal to one quarter of the sampling rate. A low pass filter (6, 16) filters selected frequencies from the digital signal. A frequency offset stage (8, 18) applies a modification to the frequency of the filtered signal to reduce frequency offset therein, and a differential demodulator (10, 20) demodulates the signal after modifying the frequency to reduce the frequency offset. There is also disclosed a method for demodulating a signal.

Abstract: A circuit for canceling noise components is provided for a radio wave receiver which receives a long wave standard radio wave. The circuit includes a multiplier, a divider, a differentiation circuit and an adder, and obtains a signal by shifting the phase of a carrier signal by 90 degrees, wherein the carrier signal has the same frequency and the same phase as those of the carrier of a received signal outputted from a carrier reproduction circuit. Thereby, it is possible to certainly remove the noises in the vicinity of a received frequency.

Abstract: The present invention, generally speaking, takes advantage of the properties of quadrature signals to achieve precise quadrature alignment in a simple fashion. In particular, the expectation of the product of quadrature signals is zero. In accordance with the teachings of the invention, a phase error detection network therefore operates by multiplying the received quadrature signals and low-pass filtering the product to produce an error signal. When the signals are in precise quadrature relationship, the error signal will be zero. Real-time feedback control may be used to drive the error to zero. In accordance with another aspect of the invention, a variable phase shift network is achieved using a dual delay line. The difference in delay between the two delay lines is adjusted in response to the error signal to obtain precise quadrature alignment. The principles of the invention may be applied in connection with traditional mixer architectures or with switch-mode (e.g., “aliased undersampling”) architectures.

Abstract: Disclosed is a reception apparatus and method of a mobile station in a Software Defined Radio (SDR) mobile communication system. A radio frequency (RF) processor converts a received RF signal into a digital signal, and outputs data on a per-unit basis according to a predetermined clock. An external memory stores the output data in a predetermined buffer area. A digital signal processing unit reads stored data samples and performs digital signal processing on the read data samples while storing the data in the external memory is completed.

Abstract: A direct conversion receiver and a method for correcting phase imbalance therein is disclosed. An input signal is applied to an in-phase channel and a quadrature channel of the receiver. The input signal is processed by the direct conversion receiver to obtain an in-phase zero intermediate frequency (IF) signal in the in-phase channel and a quadrature zero-IF signal in the quadrature channel. The in-phase zero-IF signal and the quadrature zero-IF signal are filtered to obtain a fixed band signal. A phase imbalance correction value is obtained for the fixed-band quadrature zero-IF signal as a function of the frequency of the fixed-band in-phase zero-IF signal and the fixed-band quadrature zero-IF signal. The in-phase zero-IF signal and the quadrature zero-IF signal are sampled and the phase imbalance correction value is applied using an interpolation to the sampled quadrature zero-IF signal or to the sampled in-phase zero-IF signal to correct the phase imbalance in the direct conversion receiver.

Abstract: The embodiments of the present invention provide a configurable homodyne/heterodyne RF receiver including first and second mixers. The configurable homodyne/heterodyne RF receiver functions as a homodyne receiver when the first and second mixers are configured to operate in parallel, and as a heterodyne receiver when the first and second mixers are configured to operate in series. The embodiments of the present invention further provides an RFID reader employing the configurable homodyne/heterodyne RF receiver to facilitate a listen-before-talk function.

Abstract: A demodulator which is arranged to demodulate a first signal with the aid of a second signal, comprises a first bandpass (30) filter arranged to recover the first signal (36) from a received signal (10) and a second bandpass filter (32) arranged to recover the second signal (30) from the received signal (10). Wherein the passband of the second bandpass filter (32) is substantially narrower than the passband of the first bandpass filter (30).

Abstract: A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a switched circuit network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the switched circuit network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the switched circuit network for transmission on the packet based network, and modulating data signal packets from the packet based network for transmission on the switched circuit network. The call discriminator is used to selectively enable the voice exchange and data exchange.

Abstract: Determining a frequency and phase offset estimates include receiving a signal at an offset estimator. The received signal is zero-padded in the time domain to yield a zero-padded signal. A Fourier transform of the zero-padded signal is taken to yield a transformed signal. The maximum power of the transformed signal is established. Frequency and phase offset estimates are generated based on the maximum power of the transformed signal.

Abstract: An error detection and correction apparatus includes three threshold logic units which make decisions based on current and previous bit values in a bit stream of block-coded data. One of the threshold logic units decodes the data stream based on an advancing time stream of data. Another threshold logic unit decodes the data stream based on a time-reversed stream of data, and the last threshold logic unit decodes the data stream based on a time-reversed input stream of data and a time-reversed set of decisions made by the first threshold logic unit. Each threshold logic unit generates decisions and a parity check of those decisions Error identification information is compared between the three streams of decisions and parity checks on those decisions, thereby producing error information, which is processed by a circuit which determines which is the most likely data transmitted.

Abstract: An OFDM demodulation circuit capable of initiating a demodulation process within a short period of time after the reception of a signal and terminating the demodulation early if it has been initiated erroneously, and an OFDM reception apparatus employing the OFDM demodulation circuit. If a threshold value Sth2 in peak detector 122 is not exceeded within a predetermined time T following the output of a symbol timing signal from peak detector 121, namely if a continuation timing signal is not supplied from peak detector 122 to a demodulation process terminating circuit 162 before demodulation process terminating circuit 162 counts predetermined time T (step S115), demodulation process terminating circuit 162, determining that the position at which the demodulation process has been started was wrong, terminates the currently executed demodulation process soon after the completion of the counting of predetermined time T and returns to a received-signal awaiting state (step S111).

Abstract: A system comprises a receiver module that generates a receiver carrier frequency and that demodulates an orthogonal frequency division multiplexing (OFDM) signal using the receiver carrier frequency. A CFO estimator module communicates with the receiver module and generates a carrier frequency offset (CFO) estimate using an M-th power method and normalizing a magnitude thereof. Another CFO estimator module communicates with the receiver module and generates a carrier frequency offset (CFO) of the OFDM signal using an M-th power method and normalizing a magnitude thereof. The CFO estimator module may be blind. The OFDM signal may also contain pilot subcarriers. The pilot subcarriers may contain known pilot symbols.

Abstract: Methods and systems for a quadrature local oscillator generator utilizing a DDFS for extremely high frequencies. Aspects of one method may include utilizing the DDFS to generate a first signal that may comprise an in-phase (I) component and a quadrature phase (Q) component. A base signal may be divided to generate a second signal with an in-phase (I) component and a quadrature phase (Q) component. The I and Q components of the first and second signals may be mixed by a plurality of mixers, and the outputs of the mixers may be combined to generate an in-phase component of a local oscillator signal and a quadrature phase component of the local oscillator signal. The frequency of the local oscillator signal may be controlled by inverting or not inverting outputs of one or more of the mixers.

Abstract: The data receiver device includes: a bit phase synchronizing circuit (10) for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit (20) for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit (10) is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit (10) and a corresponding clock signal. The bit phase synchronizing circuit (10) initializes the phase adjustment of the data signal when receiving the detection signal.

Abstract: A radio relay system (1) comprises a wireless camera (11) and a signal receiving relay station (12). The wireless camera (11) wirelessly transmits signals to the signal receiving relay station (12) by using the OFDM modulation method. The wireless camera (11) and the signal receiving relay station (12) perform energy dispersion at the time of transmission-line-coding/decoding a transport stream. The PRBS seed (initial value) to be used for the energy dispersion can be externally modified and the user can arbitrarily select a value for the seed.

Abstract: A method and system provide the ability to measure a transmission performance characteristic. A signal is received and equalized. The equalized signal is demodulated and an ideal signal is generated from the demodulated equalized signal. A performance characteristic is the estimated from a difference between the ideal signal and the equalized signal.

Abstract: The present invention provides for making code rate adjustments and modulation type adjustments in a pseudonoise (PN) encoded CDMA system. Coding rate adjustments may be made by changing the number of information bits per symbol, or Forward Error Code (FEC) coding rate. A forward error correction (FEC) block size is maintained at a constant amount. Therefore, as the number of information bits per symbol are increased, an integer multiple of bits per epoch is always maintained. The scheme permits for a greater flexibility and selection of effective data rates providing information bit rates ranging from, for example, approximately 50 kilobits per second to over 5 mega bits per second (Mbps) in one preferred embodiment.

Abstract: A method and system provide the ability to measure a transmission performance characteristic. A signal is received and demodulated. An ideal signal is generated from the demodulated signal. The received signal is coherently averaged to reduce noise. The performance characteristic is the estimated TWTA nonlinearity from a difference between the coherently averaged ideal signal and received signal.

Abstract: A biasing algorithm, apparatus and method for detecting and modulation format of a received signal used in a mobile phone system implementing EDGE technology that transmits and receives both GMSK and 8PSK modulated signals. The biasing method and apparatus may also estimate the modulation format of bursts of data blocks of a received signal using information gathered and/or results determined during the modulation detection of one or more previous bursts of a data block to bias the modulation detection of a present burst of the same data block. The gathered information during the modulation detection of a previous burst includes either the signal-to-noise ratio or the noise energy information of the previous burst.

Abstract: A data communications system for communicating a data signal formed of successive data elements, said system comprising a transmission node; a reception node; and a link providing a data connection from said transmission node to said reception node; in which: said transmission node comprises a clock signal transmitter for transmitting a synchronisation clocking signal to said reception node via said link, said synchronisation clocking signal having synchronising features occurring at a frequency lower than a data element rate; an assembler for assembling elements of said data signal into data frames, each data frame having a plurality of successive data elements of said data signal, for transmission to said reception node via said link, said assembler being responsive to said synchronisation clocking signal so as to set a synchronisation flag associated with a data element having a first predetermined temporal relationship with a synchronising feature of said synchronisation clocking signal; and said receptio

Abstract: A configurable all-digital coherent demodulator system for spread spectrum digital communications is disclosed herein. The demodulator system includes an extended and long code demodulator (ELCD) coupled to a traffic channel demodulator (TCD) and a parameter estimator (PE). The demodulator also includes a pilot assisted correction device (PACD) that is coupled to the PE and the TCD. The ELCD provides a code-demodulated signal to the TCD and the PE. In turn, the TCD provides a demodulated output data signal to the PE. The PACD corrects the phase error of the demodulated output data based on an error estimate that is fed forward from the PE. Accumulation operations in the ELCD, TCD, and PE are all programmable. Similarly, a phase delay in the PACD is also programmable to provide synchronization with the error estimate from the PE.

Abstract: An apparatus for compensating for a phase mismatch in a Quadrature Phase Shift Keying (QPSK) demodulator that includes a phase mismatch extractor module for generating a signal including a phase mismatch function by mixing an I-channel demodulation signal and a Q-channel demodulation signal, which are output signals of a phase shifter, and extracting the phase mismatch function by filtering the generated signal; and a phase mismatch compensator module for digital-converting the phase mismatch function, mapping the digital-converted phase mismatch function to a first compensation signal, generating a second compensation signal by mixing the digital-converted phase mismatch function with a baseband I-channel signal, generating a third compensation signal by adding a baseband Q-channel signal to the second compensation signal, and mixing the first compensation signal with the third compensation signal.

Abstract: There is proposed a technique for determining parameters, especially channel estimation, in the receiver of a communication system utilising adaptive antenna techniques. The technique uses information transmitted in the antenna signals and in the beam signals to determine the parameters.

Abstract: This invention is primarily a circuit structure of self-mixing receiver, and the methodology of circuit structure is described as follows. The first stage is a high input impedance voltage amplifier utilized to amplify the received RF carrier signal from the antenna. Besides, there are no any inductors required. The second stage is a multi-stage amplifier to amplify the output signal of first stage to rail-to-rail level, which is quite the same with supply voltage. The third stage is a mixer adopted to lower the signal frequency. The fourth stage is a digital output converter, which is proposed to demodulate the electric signals and convert the demodulated signal to digital signal.

Abstract: A receiver (20) for performing timing recovery over at least one complex channel at low or less than zero SNR (signal power to noise power, in dB) has at least one receive element such as an antenna, an analog-to-digital converter 21 (ADC), a fractional interpolation filter 23, a matched filter 24, and a timing correction loop 26. The timing correction loop 26 selects a minimum mean square error from the output of the matched filter 24 to determine a timing signal output to the interpolation filter 23, and provides one-bit weights to the matched filter 24. Preferably, the timing correction loop 26 includes a magnitude detector 26c, a moving average filter 26b, and a timing error detector 26a that outputs an integer m and fractional ? timing factor to the interpolation filter 23. Within a phase correction loop 27 is a maximum likelihood channel estimator 27b and a phase error detector 27a that controls a phase rotator 22 disposed between the ADC 21 and the interpolation filter 23.

Abstract: The present invention discloses a variable-frequency circuit with a compensation mechanism, which comprises: a load sensing/decision unit, a frequency-division unit and a level modulation unit. The present invention applies to a power supply having a frequency-division mode. The power supply has a feedback unit generating a feedback signal. The load sensing/decision unit determines the operational mode according to the feedback signal. The frequency-division unit generates a reference frequency signal. The level modulation unit generates a reference level signal. During frequency variation, the level modulation unit generates a compensation current to modulate the reference level signal. Thereby, the PWM unit of the power supply can adjust the working cycle of the power supply according to the reference frequency signal, the reference level signal and the feedback signal.

Abstract: Signals, systems and methods for transmitting and receiving layered modulation for digital signals are presented. A layered signal for transmitting data, comprises a first signal layer including a first carrier and first signal symbols for a first digital signal transmission and a second signal layer including a second carrier and second signal symbols for a second signal transmission disposed on the first signal layer, wherein the layered signal has the first carrier demodulated and first layer decoded to produce the first signal symbols for a first layer transport, the first signal symbols are remodulated and subtracted from the layered signal to produce the second signal layer, and the second signal layer has the second carrier demodulated and decoded to produce the second signal symbols for a second layer transport.

Abstract: A demodulation circuit and method are provided. The demodulation circuit includes a transformation circuit which is configured to transform the received signal into a modified signal representation in which both amplitude-varying information and frequency-varying information are converted to a uniform representation; and a processing circuit which is configured to process the modified signal representation to demodulate the received signal based on the uniform representation. The method includes transforming the signal into a modified signal representation in which both amplitude-varying information and frequency-varying information are converted to a uniform representation; and processing the modified signal representation to demodulate the signal based on the uniform representation.

Abstract: A method and apparatus are provided for calculating a log-likelihood ratio (LLR) for decoding in a receiver for a mobile communication system, wherein the method and apparatus determine selection bits for distinguishing four quadrants in a constellation representing signal points of transmission symbols, determine domain bits for distinguishing the signal points in each domain of the four quadrants according to a modulation order of the transmission symbols, repeat an operation of dividing a received signal into a real component and an imaginary component according to the number of determined domain bits, calculate and origin-shift absolute values of the real component and the imaginary component, and calculate LLRs for the selection bits. Further, the method and apparatus can subsequently calculate LLRs for corresponding domain bits each time the origin-shifted received signal is received.

Abstract: Embodiments of a low intermediate frequency system and method are disclosed. In one embodiment, among others, a method for operating a receiver is disclosed that comprises receiving a radio frequency signal, downconverting the radio frequency signal to a downconverted signal comprising an in-phase component and quadrature component, and estimating a gain and phase imbalance between the in-phase component and the quadrature component.

Abstract: In an I/Q demodulation circuit, an offset amount determined in an offset detection mode is previously stored so that, in a normal reception mode, an offset is corrected for based on the data thus stored. With this configuration, a DC offset and a phase offset can be corrected for without a delay in an I/Q demodulation operation.

Abstract: In a method of phase adjustment for the demodulator 1 of the present invention, the phase adjustment is performed by driving any one of the heaters on the two waveguides 10 and 11 in the Mach-Zehnder interferometer (MZI) 6 and on the two waveguides 14 and 15 in the MZI 7. In case that an initial phase difference between the MZIs 6 and 7 smaller than a required phase difference as ?/2 therebetween, the heaters C and D are driven, that are formed on the first waveguide 10 in the MZI 6, and the heaters G and H are driven, that are formed on the second waveguide 15 in the MZI 7. In case that the initial phase difference is larger than the required phase difference (?/2) therebetween, the heaters A and B formed on the second waveguide 11 in the MZI 6, and the heaters E and F formed on the first waveguide 14 in the MZI 7 are driven.

Abstract: A composite baseband signal includes a desired signal component modulated according to a first modulation scheme and an interfering signal component modulated according to a second modulation scheme. Information is recovered from the composite signal by applying a phase rotation associated with the second modulation scheme to the composite signal to generate a rotated signal. Based on the rotated signal, a channel model associated with the desired signal component and interference cancelling filter coefficients associated with the interfering signal component are generated. The rotated signal is filtered according to the interference cancelling filter coefficients to suppress the interfering signal component from the rotated signal. The filtered signal is equalized based on branch metrics derived from the channel model and symbol hypotheses rotated in accordance with a difference in phase rotations associated with the first and second modulations to recover information from the desired signal component.

Abstract: An intermediate frequency receiver includes mixers for generating first and second IF signals from a RF signal and local oscillator signals. A magnitude calibration loop adjusts a gain of the first and/or second IF signals generated from the mixers depending on a magnitude difference between the IF signals. The phase calibration loop adjusts a phase of a local oscillator signal before being used at the mixers depending on a phase difference between the IF signals.

Abstract: A DPSK demodulator demodulates DPSK signals in a computationally efficient manner to reduce the power requirements of the DPSK demodulator. A DPSK signal is received, digitized, converted to its in-phase (I) and quadrature (Q) components and filtered to remove noise. The I and Q components are processed to determine a relative phase and frequency offset. The phase is adjusted using the frequency offset. The adjusted phase is converted to an absolute phase, which is then mapped to a symbol representative of one or more bits of data.

Abstract: An input signal (IN) is filtered (605) to remove aliases and a switched capacitor network (610) undersamples this signal to provide a downconverted, near-baseband signal. An amplifier (615) adjusts the amplitude of this signal to match a digitizer (620). The digitized output is converted into first phase and second phase signals which are then filtered (640) and decimated (645) to further reduce the sampling rate. The downconverted first and second phase signals, rather than higher frequency signals, control the gain function (AGC) for the amplifier (615). The switched capacitor network (610) provides for both tuning and downconversion of the desired signal to a lower frequency for further processing, thus reducing the frequency and power requirements of an associated amplifier and analog-to-digital converter (digitizer).

Abstract: A simplified spread spectrum demodulator uses a frequency detector to demodulate a modulated spread spectrum signal to obtain successive chip values. A correlation unit correlates the successive chip values with fixed sequences of correlation coefficients to generate correlation values. A decision circuit selects one of the correlation values to decide what symbol the spread spectrum signal represents. The correlation coefficients are obtained by applying the same modulation method as used to modulate the spread spectrum signal, and then the same demodulation method as used by the frequency detector, to the sequences of chips representing different symbols. Since synchronous detection is not employed, no carrier recovery circuit is needed.

Abstract: A method and system for processing a signal are disclosed. The method comprises: applying an algorithm to selectively negate a plurality of samples of the signal to provide negated and non-negated samples of the signal, and use the negated and non-negated samples as in-phase (I) and/or quadrature (Q) components of a plurality of complex samples, the algorithm being such that the plurality of complex samples are equivalent to the result that would be obtained by applying an effective sampling function to the signal, and selecting a beat frequency of the effective sampling function by adjusting the algorithm.

Abstract: A method for correcting I/Q imbalance in a received signal is disclosed. The method includes the steps of grouping (202) the received signal into a predetermined number of clusters, and determining (204) at least one coefficient value by feeding the predetermined number of clusters into a nested loop. The method further includes computing (206) a compensation value based on the at least one coefficient value, and correcting (208) the I/Q imbalance in the received signal by using the compensation value.

Abstract: A system and method demodulate N QAM signals (N being a positive integer equal to or greater than 1) substantially simultaneously using, for example, one or two oscillators, regardless of how many QAM signals need to be demodulated.

Abstract: A communication system disclosed herein includes a channel quality estimation module that determines the channel quality metric utilizing the preamble portion of the packet only. Data, in such a communication system, is transmitted in the form of a packet over a data channel during a packet transmission, wherein each data channel includes several subchannels. The system includes a receiver having at least a baseband processor. The baseband processor couples to receive each baseband sample signal. Specifically, the baseband processor calculates the gain estimation of the each subchannel and generates a channel quality metric for each subchannel that is derived by deinterleaving the sequence of gain estimation magnitudes, convolving the deinterleaved sequence of gain estimation magnitudes with a short window index, and detecting the number of times the convolution falls beneath a predetermined threshold.

Abstract: Methods and apparatuses for maximizing power and spectral efficiencies in a wireless communication system are disclosed. The invention is particularly useful for layered modulation applications because power levels for such applications are relatively high. A layered modulation signal comprises an upper and a lower layer signal that interfere with each other within the same frequency band such that the upper layer signal can be demodulated directly from the layered modulation signal, and the lower layer signal can be demodulated after subtracting the first layer signal from the layered modulation signal. The invention applies one or more of the following four signal schemes in a communication signal including varying the symbol rate (rather than the code rate), reducing or eliminating the guard band, reducing excess signal bandwidth and employing layered modulation within the guard band of the legacy signal.

Abstract: Methods and apparatuses employing symmetrical phase-shift keying (SPSK) for data modulation and demodulation. Each symbol in a transmission signal carries n-bit information and is transmitted with one of 2n+1 directions. Half directions among the 2n+1 directions are regarded as default directions and the remaining are regarded as complementary directions. Each default direction has a corresponding complementary direction with a phase difference of ? and representing the same n-bit information as the default direction. The phase difference between any two successive symbols after modulation is less than or equal to ?/2.

Abstract: The invention relates to a method for determining the position xp of a peak of a pulse in a signal received at a receiver. In order to improve the accuracy of this determination, the method comprises taking samples of said received signal, determining at least three samples, at least one of which has a signal strength exceeding a threshold value, and determining the position xp of the pulse peak based on an interpolation of at least two of the determined samples, which at least two samples are selected based on the signal strengths of the at least three determined samples, and which interpolation includes an evaluation of the signal strength of the at least two samples. The invention relates equally to a device and to a cellular communication system comprising means for realizing this method.

Abstract: The present invention discloses a method and apparatus of IQ imbalance compensation for a receiver. The repetitive attribute of the preamble in a signal received by the receiver is used to estimate the IQ imbalance parameters. The data carried by the preamble repeats itself every N sampling intervals. A MSE equation is derived based on assuming the ratios between any two sampling points separated by N samples are identical, and the IQ imbalance parameters can be estimated by solving the MSE equation using the LS algorithm. Consequently, the IQ mismatch offset of the signal is compensated according to the estimated parameters.

Abstract: Various embodiments are described herein for a system and method of detecting Automatic Identification System (AIS) signals in space and decoding these signals. In one aspect, a system for performing this function is described which includes a receiver configured to receive the plurality of AIS signals and pre-process the plurality of AIS signals to produce digital input data, and a processing unit configured to process the digital input data to identify one or more candidate AIS message signals based on Doppler offsets associated with the digital input data, determine corresponding Doppler offset estimates and time estimates of the one or more candidate AIS message signals, decode the one or more candidate AIS message signals to obtain corresponding message segments and validate the decoded message segments for proper AIS formatting.