Synchronization Failure Prevention Patents (Class 375/357)
  • Patent number: 10623054
    Abstract: Techniques for implementing timesharing in discontinuous systems, for example to implement low power modes, are discussed. In some embodiments, a set of bit loading tables is determined in advance, and bit loading tables are then selected based on which lines are transmitting and which are quiet.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: April 14, 2020
    Assignee: Lantiq Deutschland GmbH
    Inventors: Rainer Strobel, Lilia Smaoui, Vladimir Oksman
  • Patent number: 10469214
    Abstract: Techniques and mechanisms for a clock recovery circuit to generate a cyclical signal based on data signals which are susceptible to circuit switching jitter. In an embodiment, a clock recovery circuit comprises switch circuitry which receives a first signal representing a logical combination of multiple pulsed signals (which, in turn, are each based on a different respective differential data signal). The switch circuitry provides to latch circuitry of the clock recovery circuit a second signal based on the first signal. The latch circuitry generates a cyclical signal based on the second signal, and transitions the switch circuitry between an open-circuit state and a closed-circuit state. In another embodiment, the latch circuitry implements a predetermined and configurable time period between a transition of the cyclical signal and a next subsequent logic state transition of the cyclical signal.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 5, 2019
    Assignee: Intel Corporation
    Inventors: Pankaj Dudulwar, Mohit Verma, Hongjiang Song, Mingming Xu
  • Patent number: 10095575
    Abstract: A user equipment node, upon determining that the data loss in a requested file is above, or likely to be above a threshold value, transmits a delivery missing report to a server node indicating that the data loss in the requested file is above the threshold value. The delivery missing report is used by the server node for determining whether or not a multicast file repair procedure should be enabled, based on the number of delivery missing reports it has received from other user equipment nodes. This enables a point-to-multipoint file repair procedure to be enabled sooner, and prevent a flood of point-to-point file repairs.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: October 9, 2018
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Robbie Ling, Emer Chen, Jinyang Xie
  • Patent number: 10025344
    Abstract: A network system includes at least one node configured to exchange messages through a set of communication links. Each node includes a synchronizer, a set of monitors in communication with the synchronizer, a physical oscillator and a state timer clock and a local timer clock, each clock being driven by the physical oscillator and having a variable clock value that locally tracks passage of clock time for the node. The network system is configured to execute a synchronization process when a specified condition occurs. Upon receiving a Sync message, each of the nodes is configured to store an incoming Sync message, increment a local timer clock value, or ignore the Sync message based on a local timer clock value associated with an incoming Sync message.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: July 17, 2018
    Inventor: Mahyar R. Malekpour
  • Patent number: 10019047
    Abstract: A load control device for controlling the power delivered from an AC power source to an electrical load is able to receive radio-frequency (RF) signals from a Wi-Fi-enabled device, such as a smart phone, via a wireless local area network. The load control device comprises a controllably conductive device, a controller for rendering the controllably conductive device conductive and non-conductive, and a Wi-Fi module operable to receive the RF signals directly from the wireless network. The controller may cooperate with one or more other devices to synchronize in time the adjustments made by one or more load control devices that are operable to control the power delivered to one or more electrical loads. The one or more load control devices may also cooperate with one or more Internet based information providers to provide preconfigured and condition based adjustments of the one or more electrical loads.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: July 10, 2018
    Assignee: Lutron Electronics Co., Inc.
    Inventor: John Bull
  • Patent number: 9939840
    Abstract: An integrated circuit receives test-control information that is phase encoded on a scan clock used for testing a scan chain within the IC. The phase encoding does not affect the normal use of the scan clock and scan test chain and allows additional test-related data such as power supply, clock, and additional global and specialized status data to be collected by a secondary test data storage system such as a shift register. The phase encoding further controls selectively outputting the enhanced test status or the traditional scan test outputs.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: April 10, 2018
    Assignee: NXP USA, INC.
    Inventors: Ling Wang, Huangsheng Ding, Wei Zhang
  • Patent number: 9601089
    Abstract: A display device includes a display panel including data lines, scan lines, and pixels connecting with the data lines and the scan lines, a scan driver configured to supply scan signals to the scan lines, a source drive integrated circuit (“IC”) configured to convert digital video data into data voltages and to supply the data voltages to the data lines, and a timing controller configured to transmit the digital video data to the source drive IC and to control driving timing of the scan driver and the source drive IC, in which a transmitter and a receiver of the source drive IC are connected via a pair of transmission lines to a transmitter and a receiver of the timing controller.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: March 21, 2017
    Inventor: Won-Tae Choi
  • Patent number: 9532247
    Abstract: A technique for radio link detection in a wireless communication system includes estimating a first error rate of an indicator channel. In this case, the indicator channel includes an indication of a number of symbols in a control channel. A second error rate of the control channel is also estimated. The first and second error rates are then combined to provide a performance metric. Based on the performance metric, a determination is made as to whether a radio link problem exists.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: December 27, 2016
    Assignee: APPLE INC.
    Inventors: Ian Wong, Taeyoon Kim
  • Patent number: 9424807
    Abstract: A multimedia system includes a main special function register (SFR) configured to store SFR information; a plurality of processing modules each configured to process frames of data, based on the SFR information; and a system control logic configured to control operations of the main SFR and the plurality of processing modules. The plurality of processing modules may process data of different frames at the same time period.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: August 23, 2016
    Inventors: Dong Han Lee, Sung Hoo Choi, Jae Sop Kong, Sung Chul Yoon, Kee Moon Chun
  • Patent number: 9413569
    Abstract: Various exemplary embodiments relate to a method of producing adaptive thresholds in a binary frame based communication system, including: collecting Kst samples of a received signal corresponding to a start bit; computing an estimate of as received signal parameter Pst in the start bit; adjusting an start threshold based upon Pst; collecting Ksp samples of the received signal corresponding to a stop bit; computing an estimate of a received signal parameter Psp in the stop bit; and adjusting an stop threshold based upon Psp.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: August 9, 2016
    Assignee: NXP B.V.
    Inventor: Shakti Prasad Shenoy
  • Patent number: 9398065
    Abstract: A method and system may include a source station to provide wireless multicast transmission to a plurality of destination stations according to a protocol adaptation layer multicast management protocol. The topology includes audio/video sources and sinks and intervening branch devices. Messages between sources and sink devices may be used for resource management such as device discovery and certification. If certification is shown, the disclosed transmission performs AV streaming directly to the least one sink device without the need for a displayport (DP) interface or a high definition multimedia interface (HDMI) or additional bridge devices/dongles that convert WiGig to some other interface supported by the monitor.
    Type: Grant
    Filed: December 17, 2011
    Date of Patent: July 19, 2016
    Inventor: Srikanth Kambhatla
  • Patent number: 9372744
    Abstract: A transmission signal transmitted via a common data signal line, includes a management data region different from a control/monitoring data region including data of control data and monitoring data signals. The slave station acquires input information from an input part corresponding to its own station, acquires control data for reference by an output part of another station in a correspondence relation with the input part from the transmission signal, and obtains a pseudo output change timing equal to a true output change timing of the output part based on the control data. A signal configuring data indicating a first failure state when a time difference between the pseudo output change timing and an input change timing of the input part is smaller than a first threshold value or a second failure state when the time difference is larger than a second threshold value is superimposed on the management data region.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: June 21, 2016
    Inventors: Kenji Nishikido, Youichi Hoshi, Shotaro Kusumoto
  • Patent number: 9369212
    Abstract: A system, method and apparatus for power saving using burst-mode transmission over point-to-point physical connections. In one embodiment, a physical layer device (PHY) is provided that includes a data detector that is configured to generate a first control signal upon receipt of a non-idle code group over an interface between the PHY and a media access control (MAC) device and to generate a second control signal when all data received from the MAC device has been transmitted by the physical layer device. The PHY also includes a laser for transmission of data over an optical network cable, the laser being configured to perform a first transition from an off state to an on state based on the first control signal, and to perform a second transition from the on state back to the off state based on the second control signal.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: June 14, 2016
    Inventors: Glen Kramer, Lowell David Lamb, Jaroslaw Wojtowicz, Ryan Edgar Hirth
  • Patent number: 9207704
    Abstract: An integrated circuit receives a first and second clock signal and a select signal that selects one of the clock signals. A glitchless switching circuit supplies an output clock signal according to which of the first and second clocks is selected by the select signal. A reset circuit coupled to the glitchless switching circuit responds to a direction of a transition of the select signal and generates a first reset signal in response to a first direction of the transition and generates a second reset signal in response to a second direction of the transition. The reset pulses are supplied respectively to first and second paths in the glitchless switching circuit to reset the state machine formed by the first and second paths in the event one of the input clocks is absent.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: December 8, 2015
    Assignee: Silicon Laboratories, Inc.
    Inventors: William J. Anker, Srisai R. Seethamraju
  • Patent number: 9118308
    Abstract: A duty cycle corrector includes a VCD (Voltage-Controlled Delay) circuit, an edge detector, an SR latch, a mode controller, and a CP (Charge Pump) circuit. The VCD circuit delays an input clock signal for a delay period so as to generate a delay clock signal. The delay period is adjusted according to a CP control voltage. The edge detector detects clock edges of the input clock signal and the delay clock signal so as to correspondingly generate a first clock edge signal and a second clock edge signal. The SR latch generates a toggling signal according to the first clock edge signal and the second clock edge signal. The mode controller generates a mode control voltage. The CP circuit operates in different modes according to the mode control voltage. The CP circuit generates the CP control voltage according to the toggling signal and the mode control voltage.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: August 25, 2015
    Inventor: Yeong-Sheng Lee
  • Patent number: 9036758
    Abstract: A method and apparatus for detecting an envelope are provided. The method and apparatus may detect an envelope of a modulating signal based on a low calculation complexity and a simple circuit configuration, by detecting an envelope for a plurality of sampling signals with equal time intervals.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: May 19, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Keun Yoon, Ui Kun Kwon, Sang Joon Kim
  • Patent number: 9020075
    Abstract: Methods and systems are described for improving a data at a receiver using one or more signal peak detectors. A signal is received having an initial signal level from the transmitter, the signal having a long bit and a short bit. The initial signal voltage of the signal is measured using a signal peak detector. A pre-emphasis value is determined using the signal voltage and is communicated to the transmitter, causing the transmitter to transmit the signal using an adjusted signal level. A second signal voltage of the initial signal is measured using a second signal peak detector, the second signal voltage being used to determine the pre-emphasis value. In another embodiment, a state machine having data relating to appropriate pre-emphasis is used in determining the pre-emphasis value. In another embodiment, one peak detector is used to measure the long bit and another peak detector is used to measure the short bit. In another embodiment, the signal does not have associated link training data.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Osamu Kobayashi, Gyo Un Choi
  • Patent number: 8983513
    Abstract: A method and apparatus for automatically switching functions associated with a leading radio to another radio on a channel is disclosed. The method includes receiving, from a leading radio by at least one other radio operating on a channel, an associated timing signal via at least one control timing message. Other radios use the timing signal to synchronize transmissions made on the channel. The method also includes receiving, by the other radios, an indication that the leading radio can no longer provide control timing messages. The method further includes maintaining, by each radio on the channel, values for various elements associated with radios operating on the channel and selecting a new leading radio from the other radios based on priorities of the various elements.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: March 17, 2015
    Assignee: Motorola Solutions, Inc.
    Inventors: Hun Weng Khoo, Yueh Ching Chung, David G. Wiatrowski
  • Patent number: 8971469
    Abstract: A master device and slave devices are connected with each other through an SDA and an SCL, and at least one of a serial communication data signal communicated through the SDA and a serial communication clock signal communicated through the SCL is latched with use of a noise removal clock signal whose frequency is higher than that of the serial communication clock signal, and is taken in.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: March 3, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Imai, Nobuaki Takahashi
  • Patent number: 8971470
    Abstract: Techniques are described to provide a device and network of devices that collect distributed coordinated timestamps from distributed time counters in a multi-module or multi-integrated circuit system. The interconnect between the modules can be a single-wire or a two-wire interconnect. The modules communicatively coupled to the interconnect can use a collision-avoidance protocol for triggering the broadcasting of timestamps among the modules as well for allowing all modules to transmit their timestamps. Timestamps from multiple clocks can be transmitted by all modules and then collected and compared to produce correction factors to clock signals of each module to potentially achieve distributed clock synchronization in multiple independent modules or integrated circuits.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: March 3, 2015
    Assignee: Intel Corporation
    Inventor: Dmitrii Loukianov
  • Patent number: 8923341
    Abstract: A method switches master/slave timing in a communication network without traffic disruption. The method includes a master device informing a slave of timing loss. The master device additionally begins transmitting with timing from a local reference clock and begins receive timing recovery. The slave freezes its receive timing recovery and locks its transmit clock. The master device transitions its transmit timing to use the recovered receive clock. The slave gradually switches to transmitting using its local clock signal. The method may be used in synchronous Ethernet networks.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: December 30, 2014
    Assignee: Vitesse Semiconductor Corporation
    Inventors: James D. Barnette, Mandeep S. Chadha, James A. McIntosh
  • Patent number: 8897408
    Abstract: A method for operating an automation system with a plurality of communication users linked for communication purposes via a serial connection, of which at least one functions as sender and at least one as a receiver, includes determining at a sender an offset value between an occurrence of a synchronous signal and a communication clock cycle, transmitting the determined offset value in a data transmission to the at least one receiver, waiting at the at least one receiver until a time period commensurate with the offset value has elapsed, and generating at the at least one receiver an output signal after the time period has elapsed.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: November 25, 2014
    Assignee: Siemens Aktiengesellschaft
    Inventor: Peter Jänicke
  • Patent number: 8843136
    Abstract: In a mobile communications network, drifts in timing of user equipment in soft handover may be accounted for by measuring the offset between the current timing of the user equipment and the first significant path of downlink frames from cells of the active set at first and second instances. Differences in the respective offsets from the first and second instances may be calculated to determine if the drift is unidirectional in time for all cells of the active set. A unidirectional drift in the offsets is indicative of a drift in timing of the user equipment, allowing the current timing to be momentarily unfrozen and updated.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: September 23, 2014
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Jonas Ohlsson, Simon Hultgren, Olof Torstensson
  • Patent number: 8824613
    Abstract: There is provided a signal transmission device including a first communication module including a first signal transmission unit for transmitting a first transmission signal having first amplitude to a second communication module through a predetermined transmission path, and the second communication module including a second signal transmission unit for transmitting a second transmission signal having second amplitude different from the first amplitude to the first communication module through the predetermined transmission path, and a transmission timing adjustment unit for adjusting a transmission timing of the second transmission signal by the second signal transmission unit so that a transition timing of the first transmission signal transmitted from the first communication module and a transition timing of the second transmission signal coincide with each other at a receiving end of the first communication module.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: September 2, 2014
    Assignee: Sony Corporation
    Inventors: Tatsuo Shimizu, Takeshi Maeda, Uichiro Omae
  • Patent number: 8817937
    Abstract: A timing control apparatus includes an adder and a comparator. The adder adds unused time error in each of a plurality of periods to form a cumulative value, and the comparator compares the cumulative value to a reference value. The unused time error is computed during operation of a first clock, and a control signal is generated to switch from the first clock to a second clock based on an output of the comparator. The frequency of the first clock is greater than a frequency of the second clock.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: August 26, 2014
    Assignee: Intel Corporation
    Inventor: Daniel Greenspan
  • Patent number: 8817933
    Abstract: Methods and apparatus are presented for obtaining clock data from Manchester coded serial data streams, in which received data is sampled at a sample rate higher than the serial data baud rate, multi-bit groups of transition bits are generated which individually indicate data transition locations in a corresponding multi-bit sampled data bit group, and clock data is derived using the multi-bit groups of transition bits without requiring receipt of synchronization data or receipt of a separate clock.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: August 26, 2014
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Darshini H. Mehta, Alan Campbell
  • Patent number: 8774339
    Abstract: It is disclosed a network element for a communication network configured to synchronize its local clock to a reference clock signal. The network element comprises: a main board comprising an internal module configured to support an internal synchronization transport protocol, and a connector connected to the internal module; and a pluggable module configured to be removably connected to the connector. The pluggable module is configured to, when connected to the connector: exchange external synchronization information with a further network element, the external synchronization information being formatted according to an external synchronization transport protocol different from the internal synchronization transport protocol; exchange with the internal module internal synchronization information formatted according to the internal synchronization transport protocol; and interface the internal synchronization transport protocol and the external synchronization transport protocol.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: July 8, 2014
    Assignee: Alcatel Lucent
    Inventors: Massimo Belisomi, Alessandro Zecchi, Marzio Gerosa, Giorgio Claudio Mazzurana
  • Patent number: 8756052
    Abstract: An electronic device is provided, having a locally and temporally adaptive prediction database.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: June 17, 2014
    Assignee: BlackBerry Limited
    Inventors: David Ryan Walker, Jerome Pasquero
  • Patent number: 8737552
    Abstract: A method of and apparatus for synchronous data transfer are described. The method may include encoding a clock period and data into an encoded signal, transmitting the encoded signal from a master device to a slave device, and recovering the data at the slave device without using a local oscillator. The apparatus may comprise a first integrated circuit including a master device configured to transmit an encoded signal of a clock period and data on a first port, and a second integrated circuit including a slave device where the slave device is configured to receive the encoded signal on a second port coupled to the first port and to recover the data without using a local oscillator.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: May 27, 2014
    Assignee: Xilinx, Inc.
    Inventor: Nicholas J. Sawyer
  • Patent number: 8731106
    Abstract: Briefly, some embodiments of the invention may provide devices, systems and methods of in-phase and quadrature mismatch analysis and correction. For example, a method in accordance with an embodiment of the invention may include re-encoding an estimated symbol of an input signal having an in-phase component and a quadrature component, based on an analysis of a mismatch between said in-phase component and said quadrature component.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: May 20, 2014
    Assignee: Marvell International Ltd.
    Inventor: Guy Wolf
  • Patent number: 8724759
    Abstract: The current application is directed to maintaining the correct number of symbols in a protocol frame in a digital communications receiver, to prevent catastrophic failure due to dynamic multipath or cycle slips. Timing recovery and framing are coherent, facilitated by placing channel estimation directly into a larger timing recovery loop.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: May 13, 2014
    Assignee: I Berium Communications, Inc.
    Inventors: Raúl Alejandro Casas, Stephen Biracree, Anand Mahendra Shah, Slobodan Simovich, Thomas Joseph Endres
  • Patent number: 8718214
    Abstract: Reducing jitter in signal wiring without requiring a larger circuit scale is difficult in the technology of the related art. A signal wiring system to resolve the above problem therefore includes an output unit to output a differential signal, a receiver unit to receive differential signals from the output unit, a jitter suppression circuit to suppress the amount of the jitter in the differential signal received by the receiver unit according to a suppression coefficient, and a signal wiring unit for conveying a differential signal from the output unit and including a wiring length set according to a suppression coefficient in the jitter suppression circuit.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: May 6, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Yasushi Aoki
  • Patent number: 8687753
    Abstract: A method of syncing a serial data stream includes the step of providing a data stream having frames and sub-frames. Each sub-frame is provided with an expected SYNC Word, and there is an expected offset between the SYNC Words in each sub-frame. The data is sent to a plurality of sync modules. Each sync module searches for an expected and different one of the SYNC Words. The sync modules identify an expected SYNC Word, then look for a different one of the SYNC Words at said expected offset from its expected SYNC Word to verify that it has properly identified a SYNC Word.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: April 1, 2014
    Assignee: Hamilton Sundstrand Corporation
    Inventor: Paul J. Leblanc
  • Patent number: 8680973
    Abstract: RFID tags are used for many purpose including tracking. RFID interrogators are used to retrieve information from tags. In many applications, a plurality of RFID interrogators are required. Synchronization between interrogators in the same theatre of operation is critical to ensure that their broadcasts do not interfere with each other. In fixed RFID interrogator applications, RFID interrogators can be wired together allowing a channel to synchronize the transmissions of the RFID interrogators. Methods described herein can ensure that synchronization is maintained in the event of the failure of a synchronizing master. Furthermore, additional methods for synchronizing RFID interrogators in wireless applications are described allowing synchronization in the absence of wired connections between interrogators.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: March 25, 2014
    Assignee: Neology, Inc.
    Inventors: James Robert Kruest, Gary Bann
  • Patent number: 8670512
    Abstract: Circuit and methods accelerate jitter tracking and reduce or eliminate the processing delay of loop filtering in timing recovery. A timing recovery circuit incorporates a phase tracking accelerator and a frequency tracking accelerator to compute the phase and frequency variation of incoming signal during the delay period of a loop filter. In one embodiment, phase and frequency tracking accelerators are realized in direct forms. In another embodiment, pre-computed look-up tables are employed in phase and frequency tracking accelerators to ease timing closure and simplify accelerator circuit. The phase tracking accelerator and the frequency tracking accelerator together compensate the estimated phase at the output of a loop filter and eliminate the processing delay of loop filtering. The loop bandwidth and jitter tolerance of timing recovery are increased.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: March 11, 2014
    Assignee: PMC-Sierra US, Inc.
    Inventor: Nanyan Wang
  • Patent number: 8666009
    Abstract: An enhanced base station and clock synchronization method are provided. The method includes scanning to discover a satellite transmitting a satellite signal and a master base station providing clock synchronization signal, entering, when a satellite having a signal that fulfills predetermined conditions is found, a master mode for receiving the satellite signal to acquire clock synchronization and transmitting a clock synchronization signal to at least one slave base station, and entering, when no satellite having a signal that fulfills the predetermined conditions is found, a slave mode for receiving the clock synchronization signal from the master base station to acquire clock synchronization. The method allows the base station to switch between the master and slave modes dynamically according to variation of the communication environment, resulting in efficient clock synchronization.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: March 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jai Jin Lim, Woo Jae Kim
  • Patent number: 8643696
    Abstract: Techniques are described herein that synchronize media streams using time signal(s) from an independent time source. An independent time source is a time source that is independent from (i.e., that is not connected to) an asynchronous data network via which the media streams are transferred. In accordance with the techniques described herein, media server(s) transfer the media streams to client(s) via an asynchronous data network. The independent time source provides the time signal(s) to the media server(s) and/or the client(s). If the time signal(s) are provided to the media server(s), the media server(s) may provide timing information that is based on the timing signal(s) to the client(s). The client(s) use the timing information from the media server(s) and/or the timing signal(s) from the timing source to synchronize the media streams.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: February 4, 2014
    Assignee: Broadcom Corporation
    Inventor: Tommy Wing Chau Kee
  • Patent number: 8619938
    Abstract: A clock generation device provided for a transmitter is provided and comprises a clock generator, a calculator and a first phase locked loop (PLL) circuit. The clock generator generates a first clock signal. The calculator calculates a frequency difference between the first and second clock signals. The first PLL circuit generates an output clock signal according to a first reference clock signal related to the first clock signal, and a frequency of the output clock signal is changed according to the frequency difference. The transmitter transmits data according to the output clock signal.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: December 31, 2013
    Assignee: Mediatek Inc.
    Inventors: Kuan-Hua Chao, Chuan Liu, Tse-Hsiang Hsu
  • Publication number: 20130315358
    Abstract: A method, telecommunication apparatus, and electronic device for detecting a status of a radio link are disclosed. A transceiver 302 may maintain a radio link with a network base station 104. A processor 304 may map channel state information to a synchronization status associated with the radio link based on the received signal and determine the synchronization status via a block error rate estimate in the radio link based on the channel state information.
    Type: Application
    Filed: July 30, 2013
    Publication date: November 28, 2013
    Inventors: Sandeep Krishnamurthy, Eoin Buckley, Ravi Kuchibhotla, Robert T Love, Ravi Nory
  • Patent number: 8582628
    Abstract: A data reception unit 21 of a reception device 20n receives calibration data to detect a data reception state or a clock reception state in the reception device 20n from a data transmission unit 11 of a transmission device 10. A decoder unit 24 causes a transmission unit 26 to send out calibration sample data that a sampler unit 23 obtained by sampling calibration data to the transmission device 10. A control unit 15 of the transmission device 10 detects a data reception state or a clock reception state in the reception device 20n based on calibration sample data received from the reception device 20n and controls the data transmission unit 11 and a clock transmission unit 12 based on the detection result.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: November 12, 2013
    Assignee: Thine Electronics, Inc.
    Inventors: Seiichi Ozawa, Hironobu Akita
  • Patent number: 8576969
    Abstract: Aspects of the disclosure provide a method for detecting marks. The method includes receiving a data signal from a channel. Further, the method includes matching the data signal to a template that corresponds to a predetermined pattern transmitted over the channel to detect marks, prior to decoding the data signal into a decoded bit stream.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: November 5, 2013
    Assignee: Marvell International Ltd.
    Inventors: Jin Xie, Mats Oberg
  • Publication number: 20130287154
    Abstract: A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.
    Type: Application
    Filed: June 26, 2013
    Publication date: October 31, 2013
    Applicant: Fujitsu Semiconductor Limited
    Inventor: Masato TOMITA
  • Patent number: 8565350
    Abstract: A method, telecommunication apparatus, and electronic device detect a status of a radio link. A transceiver 302 may receive a reference signal transmitted from a base station 104. A processor 304 may assume a transmission of a codeword of a first payload type from the base station and may determine a synchronization status based on the received reference signal and based on the assumed transmission of the codeword of the first payload type from the base station.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: October 22, 2013
    Assignee: Motorola Mobility LLC
    Inventors: Sandeep H. Krishnamurthy, Michael E. Buckley, Ravi Kuchibhotla, Robert T. Love, Ravi Nory
  • Publication number: 20130243139
    Abstract: A method for synchronizing two connection nodes by a reception node of the connection nodes with a clock data recovery circuit that generates a synchronization clock from input data. The method includes performing a synchronization process to establish synchronization between the connection nodes based on the synchronization clock, performing a connection failure process when the synchronization is not established when a first time elapses after receiving the input data, correcting the clock data recovery circuit when the synchronization is not established when a second time elapses after receiving the input data, wherein the second time is shorter than the first time, and performing a resynchronization process to establish synchronization between the connection nodes based on a synchronization clock, which is generated by the clock data recovery circuit that has been corrected, before the first time elapses and after the second time elapses.
    Type: Application
    Filed: April 16, 2013
    Publication date: September 19, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Masato Tomita
  • Patent number: 8537951
    Abstract: A network entity and computer program for detecting occurrence of transmission resynchronizations in a network carrying packets subject to variable delays, and adaptively varying the play out time of data packets. The method may include that the packets are received at a network entity and forwarded by delaying them by a jitter protection time, and determining for a predetermined time period a set of arrival time jitter values. A peak to peak value may be determined indicating the largest difference among the values included in the determined set of arrival time jitter values and detecting an out of range condition. The peak to peak value may be compared with the jitter protection time when the out of range condition is detected and detecting that a resynchronization occurred on the basis of the comparing.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: September 17, 2013
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventor: Arto Mahkonen
  • Patent number: 8509371
    Abstract: A continuous-rate clock and data recovery circuit includes a delay locked loop with a first integrator and a phase locked loop with a separate integrator. The delay locked loop and the phase locked loop are in a dual loop architecture. The first integrator is a digital accumulator that wraps upon exceeding a maximum or minimum value. The second integrator is a digital accumulator that saturates at its maximum or minimum value.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: August 13, 2013
    Assignee: Analog Devices, Inc.
    Inventor: John G. Kenney
  • Patent number: 8494091
    Abstract: Certain aspects of a method and system for satellite communication are disclosed. Aspects of one method may include a receiver that handles digital broadcasting. The receiver may be enabled to dynamically vary spacing between two or more pilots and/or the size of one or more pilots within at least one frame based on a determined symbol rate. The size of each of a plurality of received programs may be determined and the spacing between two or more pilots may be dynamically varied based on the determined size of each of the plurality of received programs.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: July 23, 2013
    Assignee: Broadcom Corporation
    Inventor: Tommy Yu
  • Patent number: 8472580
    Abstract: A clock and data recovery circuit injects a noise waveform into the control loop to offset the data sampling point artificially in order to induce errors. The amplitude of the injected waveform can be varied to ascertain the effect on the bit error rate (BER) so as to be able to evaluate the temporal noise margin.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: June 25, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan Paul Milton, Richard Simpson, Eugenia Carr Cordero Crespo
  • Patent number: 8457267
    Abstract: A system may include a bus carrying signals, a frame pulse generator generating a generally periodic frame pulse signal having timing boundaries delineating consecutive timing periods and a frame pulse enable signal active for a portion of each timing period proximate to the timing boundaries and inactive otherwise, a first controlled buffer driving the frame pulse signal on the bus during durations in which the frame pulse enable signal is active to generate a modified frame pulse, a reference clock controller receiving the modified frame pulse via the bus and generating a reference clock enable signal in response to presence of the modified frame pulse, a reference clock generator generating a generally periodic reference clock signal, and a second controlled buffer driving the reference clock signal on the bus during durations in which the reference clock enable signal is active to generate a modified reference clock.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: June 4, 2013
    Assignee: Fujitsu Limited
    Inventors: Joseph G. Trotta, Noah Gottfried, Richard Gammenthaler
  • Publication number: 20130114653
    Abstract: A device and method for synchronization of data for audio and/or video between a memory of a device in a motor vehicle and an external device is provided. The method comprises synchronizing the data between the memory and the external device through a radio connection through a synchronization unit. The method further comprises outputting a status signal (St) based on a charge state (C) of the first power source by a monitoring unit to the synchronization unit and signaling from the synchronization unit to the external device an interruption of the synchronization due to low charge level. The method further comprises terminating the synchronization of the data based on the status signal (St) indicating that the charge state (C) of the first power source is below a threshold (th) and/or that a second power source for charging of the first power source is disconnected from the first power source.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 9, 2013
    Applicant: Harman Becker Automotive Systems GmbH
    Inventor: Harman Becker Automotive Systems GmbH