Abstract: Techniques for implementing timesharing in discontinuous systems, for example to implement low power modes, are discussed. In some embodiments, a set of bit loading tables is determined in advance, and bit loading tables are then selected based on which lines are transmitting and which are quiet.

Abstract: Methods, systems, and devices for access heatmap generation at a memory device are described. In some examples, a memory device may maintain a register for tracking access operation occurrence, for which access operations of an address of the memory device may be mapped to multiple fields of the register. In some cases, in response to a first access operation performed on a first address of the memory device, the memory device may increment a first field and a second field of the register and, in response to a second access operation performed on a second address of the memory device, the memory device may increment the first field and a third field of the register. In some examples, the memory device may maintain a second register having a set of fields that each indicate a respective address for which an access occurrence satisfies a threshold.

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

Abstract: Various example embodiments of the inventive concepts provide an error correction circuit and a semiconductor device. The error correction circuit includes clock-sync distributor circuitry configured to output a plurality of distributor output data based on distributor reception data received using a first clock signal, each of the plurality of distributor output data output based on the first clock signal or a second clock signal, the second clock signal having a higher frequency than a frequency of the first clock signal, a node processor configured to generate a plurality of output data by performing error correction decoding using the plurality of distributor output data, output a first subset of the plurality of output data based on the first clock signal, and output a second subset of the plurality of output data based on the second clock signal, and clock-sync combiner circuitry configured to output, based on the first clock signal, the plurality of output data received from the node processor.

Abstract: Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.

Abstract: A communication interface circuit has a deserializer configured to convert a serial stream of 3-bit symbols received from a three-wire serial bus to a parallel multi-symbol word comprising a plurality of symbols ordered in accordance with time of arrival at an input of the deserializer, detection circuits configured to determine whether a pattern of symbols in the parallel multi-symbol word indicates a corrupt data packet, and a finite state machine configured to activate one or more flags responsive to feedback received from the detection circuits. each flag can be configured to cause termination of reception of the corrupt data packet when the each flag is active.

Abstract: A method for using a power saving signaling pattern, a terminal, and a computer readable storage medium. The method includes: determining, by a terminal, a Discontinuous Reception (DRX) timer in an operating state, the DRX timer being one of: an on duration timer with a long DRX cycle and an on duration timer with a short DRX cycle; determining, by the terminal, a pattern for monitoring the power saving signaling based on the DRX timer; and monitoring, by the terminal, the power saving signaling based on the determined pattern for monitoring the power saving signaling.

Abstract: A method, performed by a network entity, of performing time sensitive communication (TSC) includes: establishing a first protocol data unit (PDU) session with a first user equipment (UE) and a second PDU session for a second UE; receiving, from the first UE, an announce message obtained from a first time sensitive network (TSN) node; configuring, based on the announce message, a port state of the network entity; and transmitting, to the second UE or a second TSN node, the announce message.

Abstract: Provided for herein are systems, methods, apparatus and software configured synchronize clocks across two or more processing devices. The techniques of the present disclosure include: obtaining, at a processing device, indications of clocks, wherein the indications comprise an indication for a clock for each of a plurality of processing devices; determining, from the indications, whether a clock of the processing device leads or lags a majority of clocks of the plurality of processing devices; and adjusting the clock of the processing device in a direction of the majority of the clocks of the plurality of processing devices.

Abstract: A microelectromechanical device is provided. A vibrating structure gyroscope included in the device employs a temporal differential sensing method alone or a spatial differential sensing method in combination with the temporal differential sensing method. When used in combination, the temporal sensing method may be applied before the spatial sensing method or applied after the spatial sensing method. The temporal differential sensing samples signals at times t1 and t2 when velocity of a sensing mass within the vibrating structure gyroscope is maximum and has an opposite sign. The temporal sensing method improves Euler and Centrifugal forces cancellation and increases the signal to noise ratio if forces remain equal at times t1 and t2. Applying a high sampling speed can result in times t1 and t2 being sufficiently close to each other and therefore cancel any error terms associated with Euler and Centrifugal forces.

Abstract: A method, system, and apparatus for applying dithering to waveforms in a transmitter such as a Bluetooth transmitter. A current waveform corresponding to a current bit of a bitstream is received where the current waveform has a nominal frequency deviation defined by a value of the current bit. Based on the determination that the current waveform and an immediately previous bit of the bitstream are associated with different bit values, a first dithered signal is output which is defined by a first frequency offset pseudorandomly selected from a first set of frequency offsets. A subsequent waveform to the current waveform is received corresponding to a subsequent bit of the bitstream. Based on the subsequent bit and the current bit being associated with bits of the same value, a second dithered signal is output which is defined by a second frequency offset pseudorandomly selected from a second set of frequency offsets.

Abstract: A synchronous serial bus peripheral circuit includes a peripheral identification (ID) register and a state machine circuit. The state machine circuit is coupled to the peripheral ID register, and is configured to transmit a status value based on a peripheral ID field of data received via the receiver shift register equaling a value stored in the peripheral ID register.

Abstract: An optical transceiver can be calibrated using an internal receiver side eye scan generator, and calibration values (e.g., modulator values) can be stored in memory for recalibration of the optical transceiver. The eye scan generator can receive data from the transmitter portion via an integrated and reconfigurable loopback path. At a later time, different calibration values can be accessed in memory and used to recalibrate the optical transceiver or update the calibrated values using the receive-side eye scan generator operating in loopback mode.

Abstract: A link quality monitoring method performed by a mobile terminal includes the following steps: performing, by the mobile terminal, detection for a pre-configured radio link monitoring reference signal to determine whether the radio link monitoring reference signal is received; and reporting, by the mobile terminal, based on whether the radio link monitoring reference signal is received, in-synchronization or out-of-synchronization used to indicate radio link quality of the radio link used by the mobile terminal.

Abstract: One embodiment of the present invention relates to a method for a reader to transmit and receive a signal to and from a tag, the method comprising: a step in which a first reader transmits a first signal to a tag; and a step in which the first reader receives the first signal reflected on the tag. The timing for the first reader to transmit the first signal is determined by using an offset value based on an ID related to the first reader.

Abstract: A method, performed by a network entity, of performing time sensitive communication (TSC) includes: establishing a first protocol data unit (PDU) session with a first user equipment (UE) and a second PDU session for a second UE; receiving, from the first UE, an announce message obtained from a first time sensitive network (TSN) node; configuring, based on the announce message, a port state of the network entity; and transmitting, to the second UE or a second TSN node, the announce message.

Abstract: A system that synchronizes waveforms received over a network from one or more devices, such as medical devices. Because of network delays or losses, waveforms can arrive at varying rates and times. Precise post-synchronization of the received data, to within a few milliseconds, is needed for accurate analysis. Applications include automatic classification of waveforms, such as detection of myocardial infraction from heart monitor waveforms. Synchronization uses sequence numbers assigned by each device, but must also account for sequence number wraparounds. Waveforms may also be synchronized across devices, by calculating the bias between within-device synchronized times and a common time source or common disturbance. Waveform data may also be stored data in a database or data warehouse; embodiments may index the data using a key with a date-time prefix and a hash code suffix, to support distributed indexing while reducing the chance of hash collisions to a very small probability.

Abstract: Some embodiments of the time resilient system and methods disclosed herein can be configured to detect and defend against invalid time signals. According to various embodiments of the disclosed technology, the time resilient system include a receiver for collecting time signals sourced from an external clock. By way of example only, the external clock may be a high precision clock housed within a Global Positioning System. Other embodiments may include an internal clock calibrated to a time reflected on the external clock so that the internal clock and the external clock are synchronized. Additionally, a controller may monitor changes in time signals of the external over a period of time against the internal clock, where the system is alerted of a timing attack when the time signals collected from the receiver deviate a pre-determined time range with the time of the internal clock.

Abstract: A test and measurement instrument for generating an analog waveform, including an interpolator configured to receive a digital signal and output interpolated samples of the digital signal at a sample rate, a filter modulation controller configured to output first filter coefficients at a first time and second filter coefficients at a second time, a convolver configured to generate a convolved signal by convolving the interpolated samples of the digital signal and the first filter coefficients and convolving the interpolated samples of the digital signal and the second filter coefficients; and a digital-to-analog converter configured to convert the convolved signal to an analog signal based on a fixed, constant clock signal.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-Generation (4G) communication system such as long term evolution (LTE). A terminal in a wireless communication system is provided. The terminal includes a transceiver, and at least one processor configured to receive, from a base station (BS), a beam failure recovery configuration comprising at least one reference signal for identifying a candidate beam for the beam failure recovery and associated random access (RA) parameters, identify the candidate beam for the beam failure recovery using the at least one reference signal, and perform a physical random access channel (PRACH) using the at least one reference signal and the associated RA parameters on the candidate beam for the beam failure recovery.

Abstract: Embodiments of the present technology provide a synchronous device. The synchronous device provides a first latch configured to store a data input signal during a first state of a first clock signal and a slack guard circuit. The slack guard circuit provides a delay element coupled to the first latch and configured to generate a delayed data signal, a gated-input cell coupled to the delay element and configured to propagate the delayed data signal during the first state of the first clock signal, and a comparator coupled to the first latch and the gated-input cell.

Abstract: Techniques performed by a User Equipment (UE) are provided for fast timing acquisition for Discontinuous Reception (DRX) cycles. The UE determines one or more System Frame Number (SFN) hypotheses. Each of the one or more SFN hypothesis can represent a possible SFN at which the UE can wake up from a sleep state of a Discontinuous Reception (DRX) cycle. For at least one of the one or more SFN hypotheses, the UE generates a detection metric based at least partially on a Physical Broadcast Channel (PBCH) sequence received from a base station, and determines, based on a value of the detection metric, whether the at least one SFN hypothesis represents a current SFN in accordance with a clock source used the base station for communicating with the UE. Other aspects, embodiments, and features are also claimed and described.

Abstract: Techniques for implementing timesharing in discontinuous systems, for example to implement low power modes, are discussed. In some embodiments, a set of bit loading tables is determined in advance, and bit loading tables are then selected based on which lines are transmitting and which are quiet.

Abstract: Techniques and mechanisms for a clock recovery circuit to generate a cyclical signal based on data signals which are susceptible to circuit switching jitter. In an embodiment, a clock recovery circuit comprises switch circuitry which receives a first signal representing a logical combination of multiple pulsed signals (which, in turn, are each based on a different respective differential data signal). The switch circuitry provides to latch circuitry of the clock recovery circuit a second signal based on the first signal. The latch circuitry generates a cyclical signal based on the second signal, and transitions the switch circuitry between an open-circuit state and a closed-circuit state. In another embodiment, the latch circuitry implements a predetermined and configurable time period between a transition of the cyclical signal and a next subsequent logic state transition of the cyclical signal.

Abstract: A user equipment node, upon determining that the data loss in a requested file is above, or likely to be above a threshold value, transmits a delivery missing report to a server node indicating that the data loss in the requested file is above the threshold value. The delivery missing report is used by the server node for determining whether or not a multicast file repair procedure should be enabled, based on the number of delivery missing reports it has received from other user equipment nodes. This enables a point-to-multipoint file repair procedure to be enabled sooner, and prevent a flood of point-to-point file repairs.

Abstract: A network system includes at least one node configured to exchange messages through a set of communication links. Each node includes a synchronizer, a set of monitors in communication with the synchronizer, a physical oscillator and a state timer clock and a local timer clock, each clock being driven by the physical oscillator and having a variable clock value that locally tracks passage of clock time for the node. The network system is configured to execute a synchronization process when a specified condition occurs. Upon receiving a Sync message, each of the nodes is configured to store an incoming Sync message, increment a local timer clock value, or ignore the Sync message based on a local timer clock value associated with an incoming Sync message.

Abstract: A load control device for controlling the power delivered from an AC power source to an electrical load is able to receive radio-frequency (RF) signals from a Wi-Fi-enabled device, such as a smart phone, via a wireless local area network. The load control device comprises a controllably conductive device, a controller for rendering the controllably conductive device conductive and non-conductive, and a Wi-Fi module operable to receive the RF signals directly from the wireless network. The controller may cooperate with one or more other devices to synchronize in time the adjustments made by one or more load control devices that are operable to control the power delivered to one or more electrical loads. The one or more load control devices may also cooperate with one or more Internet based information providers to provide preconfigured and condition based adjustments of the one or more electrical loads.

Abstract: An integrated circuit receives test-control information that is phase encoded on a scan clock used for testing a scan chain within the IC. The phase encoding does not affect the normal use of the scan clock and scan test chain and allows additional test-related data such as power supply, clock, and additional global and specialized status data to be collected by a secondary test data storage system such as a shift register. The phase encoding further controls selectively outputting the enhanced test status or the traditional scan test outputs.

Abstract: A display device includes a display panel including data lines, scan lines, and pixels connecting with the data lines and the scan lines, a scan driver configured to supply scan signals to the scan lines, a source drive integrated circuit (“IC”) configured to convert digital video data into data voltages and to supply the data voltages to the data lines, and a timing controller configured to transmit the digital video data to the source drive IC and to control driving timing of the scan driver and the source drive IC, in which a transmitter and a receiver of the source drive IC are connected via a pair of transmission lines to a transmitter and a receiver of the timing controller.

Abstract: A technique for radio link detection in a wireless communication system includes estimating a first error rate of an indicator channel. In this case, the indicator channel includes an indication of a number of symbols in a control channel. A second error rate of the control channel is also estimated. The first and second error rates are then combined to provide a performance metric. Based on the performance metric, a determination is made as to whether a radio link problem exists.

Abstract: A multimedia system includes a main special function register (SFR) configured to store SFR information; a plurality of processing modules each configured to process frames of data, based on the SFR information; and a system control logic configured to control operations of the main SFR and the plurality of processing modules. The plurality of processing modules may process data of different frames at the same time period.

Abstract: Various exemplary embodiments relate to a method of producing adaptive thresholds in a binary frame based communication system, including: collecting Kst samples of a received signal corresponding to a start bit; computing an estimate of as received signal parameter Pst in the start bit; adjusting an start threshold based upon Pst; collecting Ksp samples of the received signal corresponding to a stop bit; computing an estimate of a received signal parameter Psp in the stop bit; and adjusting an stop threshold based upon Psp.

Abstract: A method and system may include a source station to provide wireless multicast transmission to a plurality of destination stations according to a protocol adaptation layer multicast management protocol. The topology includes audio/video sources and sinks and intervening branch devices. Messages between sources and sink devices may be used for resource management such as device discovery and certification. If certification is shown, the disclosed transmission performs AV streaming directly to the least one sink device without the need for a displayport (DP) interface or a high definition multimedia interface (HDMI) or additional bridge devices/dongles that convert WiGig to some other interface supported by the monitor.

Abstract: A transmission signal transmitted via a common data signal line, includes a management data region different from a control/monitoring data region including data of control data and monitoring data signals. The slave station acquires input information from an input part corresponding to its own station, acquires control data for reference by an output part of another station in a correspondence relation with the input part from the transmission signal, and obtains a pseudo output change timing equal to a true output change timing of the output part based on the control data. A signal configuring data indicating a first failure state when a time difference between the pseudo output change timing and an input change timing of the input part is smaller than a first threshold value or a second failure state when the time difference is larger than a second threshold value is superimposed on the management data region.

Abstract: A system, method and apparatus for power saving using burst-mode transmission over point-to-point physical connections. In one embodiment, a physical layer device (PHY) is provided that includes a data detector that is configured to generate a first control signal upon receipt of a non-idle code group over an interface between the PHY and a media access control (MAC) device and to generate a second control signal when all data received from the MAC device has been transmitted by the physical layer device. The PHY also includes a laser for transmission of data over an optical network cable, the laser being configured to perform a first transition from an off state to an on state based on the first control signal, and to perform a second transition from the on state back to the off state based on the second control signal.

Abstract: An integrated circuit receives a first and second clock signal and a select signal that selects one of the clock signals. A glitchless switching circuit supplies an output clock signal according to which of the first and second clocks is selected by the select signal. A reset circuit coupled to the glitchless switching circuit responds to a direction of a transition of the select signal and generates a first reset signal in response to a first direction of the transition and generates a second reset signal in response to a second direction of the transition. The reset pulses are supplied respectively to first and second paths in the glitchless switching circuit to reset the state machine formed by the first and second paths in the event one of the input clocks is absent.

Abstract: A duty cycle corrector includes a VCD (Voltage-Controlled Delay) circuit, an edge detector, an SR latch, a mode controller, and a CP (Charge Pump) circuit. The VCD circuit delays an input clock signal for a delay period so as to generate a delay clock signal. The delay period is adjusted according to a CP control voltage. The edge detector detects clock edges of the input clock signal and the delay clock signal so as to correspondingly generate a first clock edge signal and a second clock edge signal. The SR latch generates a toggling signal according to the first clock edge signal and the second clock edge signal. The mode controller generates a mode control voltage. The CP circuit operates in different modes according to the mode control voltage. The CP circuit generates the CP control voltage according to the toggling signal and the mode control voltage.

Abstract: A method and apparatus for detecting an envelope are provided. The method and apparatus may detect an envelope of a modulating signal based on a low calculation complexity and a simple circuit configuration, by detecting an envelope for a plurality of sampling signals with equal time intervals.

Abstract: Methods and systems are described for improving a data at a receiver using one or more signal peak detectors. A signal is received having an initial signal level from the transmitter, the signal having a long bit and a short bit. The initial signal voltage of the signal is measured using a signal peak detector. A pre-emphasis value is determined using the signal voltage and is communicated to the transmitter, causing the transmitter to transmit the signal using an adjusted signal level. A second signal voltage of the initial signal is measured using a second signal peak detector, the second signal voltage being used to determine the pre-emphasis value. In another embodiment, a state machine having data relating to appropriate pre-emphasis is used in determining the pre-emphasis value. In another embodiment, one peak detector is used to measure the long bit and another peak detector is used to measure the short bit. In another embodiment, the signal does not have associated link training data.

Abstract: A method and apparatus for automatically switching functions associated with a leading radio to another radio on a channel is disclosed. The method includes receiving, from a leading radio by at least one other radio operating on a channel, an associated timing signal via at least one control timing message. Other radios use the timing signal to synchronize transmissions made on the channel. The method also includes receiving, by the other radios, an indication that the leading radio can no longer provide control timing messages. The method further includes maintaining, by each radio on the channel, values for various elements associated with radios operating on the channel and selecting a new leading radio from the other radios based on priorities of the various elements.

Abstract: Techniques are described to provide a device and network of devices that collect distributed coordinated timestamps from distributed time counters in a multi-module or multi-integrated circuit system. The interconnect between the modules can be a single-wire or a two-wire interconnect. The modules communicatively coupled to the interconnect can use a collision-avoidance protocol for triggering the broadcasting of timestamps among the modules as well for allowing all modules to transmit their timestamps. Timestamps from multiple clocks can be transmitted by all modules and then collected and compared to produce correction factors to clock signals of each module to potentially achieve distributed clock synchronization in multiple independent modules or integrated circuits.

Abstract: A master device and slave devices are connected with each other through an SDA and an SCL, and at least one of a serial communication data signal communicated through the SDA and a serial communication clock signal communicated through the SCL is latched with use of a noise removal clock signal whose frequency is higher than that of the serial communication clock signal, and is taken in.

Abstract: A method switches master/slave timing in a communication network without traffic disruption. The method includes a master device informing a slave of timing loss. The master device additionally begins transmitting with timing from a local reference clock and begins receive timing recovery. The slave freezes its receive timing recovery and locks its transmit clock. The master device transitions its transmit timing to use the recovered receive clock. The slave gradually switches to transmitting using its local clock signal. The method may be used in synchronous Ethernet networks.

Abstract: A method for operating an automation system with a plurality of communication users linked for communication purposes via a serial connection, of which at least one functions as sender and at least one as a receiver, includes determining at a sender an offset value between an occurrence of a synchronous signal and a communication clock cycle, transmitting the determined offset value in a data transmission to the at least one receiver, waiting at the at least one receiver until a time period commensurate with the offset value has elapsed, and generating at the at least one receiver an output signal after the time period has elapsed.

Abstract: In a mobile communications network, drifts in timing of user equipment in soft handover may be accounted for by measuring the offset between the current timing of the user equipment and the first significant path of downlink frames from cells of the active set at first and second instances. Differences in the respective offsets from the first and second instances may be calculated to determine if the drift is unidirectional in time for all cells of the active set. A unidirectional drift in the offsets is indicative of a drift in timing of the user equipment, allowing the current timing to be momentarily unfrozen and updated.

Abstract: There is provided a signal transmission device including a first communication module including a first signal transmission unit for transmitting a first transmission signal having first amplitude to a second communication module through a predetermined transmission path, and the second communication module including a second signal transmission unit for transmitting a second transmission signal having second amplitude different from the first amplitude to the first communication module through the predetermined transmission path, and a transmission timing adjustment unit for adjusting a transmission timing of the second transmission signal by the second signal transmission unit so that a transition timing of the first transmission signal transmitted from the first communication module and a transition timing of the second transmission signal coincide with each other at a receiving end of the first communication module.

Abstract: Methods and apparatus are presented for obtaining clock data from Manchester coded serial data streams, in which received data is sampled at a sample rate higher than the serial data baud rate, multi-bit groups of transition bits are generated which individually indicate data transition locations in a corresponding multi-bit sampled data bit group, and clock data is derived using the multi-bit groups of transition bits without requiring receipt of synchronization data or receipt of a separate clock.

Abstract: A timing control apparatus includes an adder and a comparator. The adder adds unused time error in each of a plurality of periods to form a cumulative value, and the comparator compares the cumulative value to a reference value. The unused time error is computed during operation of a first clock, and a control signal is generated to switch from the first clock to a second clock based on an output of the comparator. The frequency of the first clock is greater than a frequency of the second clock.

Abstract: It is disclosed a network element for a communication network configured to synchronize its local clock to a reference clock signal. The network element comprises: a main board comprising an internal module configured to support an internal synchronization transport protocol, and a connector connected to the internal module; and a pluggable module configured to be removably connected to the connector. The pluggable module is configured to, when connected to the connector: exchange external synchronization information with a further network element, the external synchronization information being formatted according to an external synchronization transport protocol different from the internal synchronization transport protocol; exchange with the internal module internal synchronization information formatted according to the internal synchronization transport protocol; and interface the internal synchronization transport protocol and the external synchronization transport protocol.

Abstract: An electronic device is provided, having a locally and temporally adaptive prediction database.