Abstract: A clock generating device includes: a frequency divider having an input node coupled to a transmission interface for generating a reference clock signal according to an input data received from the transmission interface; and a clock/data recovery circuit having a data input node coupled to the transmission interface and a reference clock input node coupled to an output node of the frequency divider, for generating an output clock signal according to one of the input data received at the data input node and the reference clock signal received at the reference clock input node.

Abstract: A rake receiver for DS-CDMA UWB system and a DS-CDMA receiver having the same are provided. The rake receiver includes: a channel estimator for estimating a channel having a predetermined chip duration by using a synchronization acquisition sequence; a tracking module for detecting a channel variation and adjusting a synchronization position value when the channel variation is detected; a first switch for selecting one of an output value of an analog-to-digital converter and an output value of a correlator and outputting the selected value; a second switch for selecting one of the output value of the analog-to-digital converter and the output value of the correlator; and a plurality of demodulators having a parallel processing structure to demodulate received signals by using the channel estimation value inputted from the channel estimator, the synchronization position value stored by the tracking module, and an output value of the second switch.

Abstract: A timing system is disclosed for use in a wireless communication system that includes wireless transceiver and a digital baseband processing system. The timing system includes a primary clock generation system that provides a low frequency clock that is used as the reference clock for a digital signal processing system, which generates low frequency timing signals, and a secondary clock generation system that provides a high frequency clock that is used by the wireless transceiver to produce high resolution timing signals to control the timing of the wireless transceiver. The high resolution timing signals are commenced responsive to a low resolution timing signal.

Abstract: In a method for synchronization of a mobile radio receiver to a base station, in which a verification step or a plurality of verification steps is or are also carried out in addition to the synchronization steps and one or more identification step or steps which may be present, at least one of the verification steps is carried out in parallel with a synchronization step and/or with an identification step.

Abstract: The apparatus contains a counter that is synchronized to the reference time in the mobile station. The counter counts sampled chips of the radio signal to produce a count. The apparatus further includes a controller that controls the processing of the radio signal, activates the processing of the radio signal when the count matches a begin count, and deactivates the processing of the radio signal when the count matches an end count, wherein the begin count and the end count are determined by a signal processor as a function of the time frame offset of the radio signal with respect to the reference time in the mobile station.

Abstract: User Equipment in a wireless communication network considers the downlink channel bandwidth in setting out of synchronization (OoS) and in synchronization (IS) thresholds and filter durations. Additionally, the UE may consider transmitter antenna configuration—that is, the number of transmitting antennas in a MIMO system—in setting the OoS and IS thresholds. The UE determines it is OoS when a monitored, filtered, downlink channel quality metric, such as reference symbol SINR, is below the OoS threshold.

Abstract: Semiconductor device and operation method thereof includes an aspect of the present invention, there is provided a clock generator configured to receive an external clock signal to generate a first clock signal corresponding to a rising edge of the external clock and a second clock signal corresponding to a falling edge of the external clock, a drive control signal generator configured to restrict an activation period of the first clock signal within a deactivation period of the second clock signal to generate a first drive control signal, and restrict an activation period of the second clock signal within a deactivation period of the first clock signal to generate a second drive control signal and an output driver configured to receive a drive data in response to the first and second drive control signal to drive an output terminal in response to the drive data.

Abstract: In an apparatus and method for checking a network synchronization clock signal in a communication system, the apparatus generates a divided clock signal which is the same as an externally inputted network synchronization clock signal, compares the value of one period of the network synchronization clock signal to the value of one period of the divided clock signal, and determines whether the network synchronization clock signal is normal or not. Thus, the reliability of an operation of checking the network synchronization clock signal is enhanced.

Abstract: A first node initiating communications with a second node already in a secure network sends a discovery burst having a preamble portion and a payload portion. The preamble portion is sent at a varying frequency between high and low thresholds that are reflective of Doppler uncertainty between the nodes. The second node continuously listens at a frequency, termed an acquisition frequency. A data sequence in the preamble portion, known to the second node, is received and used to determine the receive instant in the preamble portion, and thereby compare against the known frequency ramp to determine the frequency at which the payload portion will be received. Preferably, the first node varies the preamble portion between thresholds more than once within the time span of a single preamble portion, and the preamble and payload portions are spread with different spreading codes. The preamble portion may also be disguised with noise generated by the first node.

Abstract: A communication system, clock recovery circuit, and method are provided for allowing data to be transmitted across a communication system and between clock recovery circuits absent a clock master specifically designed for one node of the communication system. Absent a clock master, the communication system is permitted to enter into an all slave mode, with periodic unlock conditions possibly rotating about the communication system ring topology. However, the unlock condition can be readily detected and if the received data bitstream formed into a recovered clock exceeds a threshold above or is less than a threshold below a reference clock generated during instances of unlock, then the clock recovery circuit will fix the synchronizing clock to the reference clock, and cause the bitstream to resynchronize to the reference clock before the reference clock is again disabled to allow the communication system to re-enter the all slave and rotating unlock condition.

Abstract: Information systems, detectors, and methods for a communication link, such as the downlink of a cellular telephone system, reduce the problem of uplink transmit power peaks when the uplink is out of synchronization (OoS). One method of indicating that a first link to a communication node is OoS includes the step of including an OoS signal in signals that are sent by the node on a second link. The OoS signal includes at least one data bit transmitted by the node that indicates that the first link is synchronized or OoS. A method of determining that a first link to a communication node is OoS includes the step of detecting an OoS signal in signals that are sent by the node on a second link. The OoS signal includes at least one data bit that indicates that the first link is synchronized or OoS.

Abstract: In multicarrier communication system using N subcarriers, in which a transmitter communicates with K receivers, the transmitter determines a channel quality information (CQI) feedback quantity indicative of the number of subcarriers for which CQIs will be fed back among the N subcarriers, for the K receivers, and transmits the CQI feedback quantity to the K receivers. Thereafter, upon receiving CQIs corresponding to the determined CQI feedback quantity, being fed back from the K receivers, the transmitter allocates subcarriers for which there are CQIs being fed back from at least one receiver among the K receivers among the N subcarriers, to any one receiver among the receivers that have fed back CQIs according to a first scheme, thereby guaranteeing the maximum throughput and the maximum fairness.

Abstract: A wireless communication system is provided that includes RF circuitry and signal processing circuitry. The signal processing circuitry includes a dedicated frequency burst (FB) search hardware circuit which exhibits relatively low noise in comparison with other digital processing circuitry, such as a DSP and MCU, within the system. The RF circuitry, dedicated FB search hardware circuit and the other digital processing circuitry can each be activated and inactivated. In one embodiment, when the RF circuitry and the dedicated FB search hardware are active, other digital processing circuitry remains inactive to avoid noise problems that could degrade reception and interfere with the FB search hardware locating the FB. Noise problems in the system are thus desirably reduced.

Abstract: A clock signal regeneration system and method to adjust the phase of a frequency-locked clock signal is provided. The system includes a numerically controlled oscillator, a clock source, and an adder. In one embodiment, additional components are included in the system to ensure that underflow or overflow of the numerically controlled oscillator is prevented. In another embodiment, additional components are included to ensure that output pulses from the numerically controlled oscillator do not occur within a minimum time interval. The method includes deriving a phase adjustment factor, adding the phase adjustment factor to a frequency control word, providing the modified frequency control word to a numerically controlled oscillator and generating a phase shifted, frequency-locked output signal.

Abstract: A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.

Abstract: When a controller transmits a clock pulse of a positive phase as a first transmit signal (a) and a clock pulse of an opposite phase as a second transmit signal (b), the controller modulates the “H” pulse of the second transmit signal to a signal advanced by time of td1 relative to the “L” pulse of the first transmit signal when the logic of transmit data is “1”, and to a signal advanced by time of td2 relative thereto when the logic of transit data is “0” and transmits the modulated signal. A data carrier device detects the change of the delay time of the second transmit signal by using a clock extracted from the first transmit signal to demodulate data (e).

Abstract: A method for midamble estimation comprises the steps of receiving a burst of symbols, selecting a subset of the burst of symbols that comprises a first midamble symbol, calculating, for each symbol in the subset, a corresponding midamble estimation error, and determining the lowest calculated midamble estimation error to locate the first midamble symbol. A receiver comprises an antenna configured to receive a burst of symbols, a timing estimator configured to select a subset of the burst of symbols that comprises a first midamble symbol, a midamble estimator configured to calculate, for each symbol in the subset, a corresponding midamble estimation error, and a processor configured to select the symbol in the subset corresponding to a lowest calculated midamble estimation error as the first midamble symbol.

Abstract: A switching circuit located in a computer system is disclosed in the present invention. The switching circuit comprises a first phase-locked loop generating a first host clock signal, a second phase-locked loop generating a second host clock signal and an output switch unit coupled to the first PLL and the second PLL. When the computer system operates in a first mode, the output switch unit chooses the first host clock signal to be a fundamental clock signal of the front side bus. In the other hand, when the computer system operates in a second mode, the output switch unit chooses the second host clock signal to be a fundamental clock signal of the front side bus.

Abstract: A method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a media access controller and to at least one component; characterized by defining a short synchronization period; processing at least one signal conveyed over the data line during the short synchronization period to determine a presence of a synchronization error; and maintaining at least the clock line in a low power mode when the data line is substantially idle. A device having frame synchronization capabilities, the device includes a clock signal provider and at least one component connected to a data line. The clock signal provider is adapted to provide a high frequency clock signal over a clock line during a transmission of information over the data line.

Abstract: There is provided an RF receiver recovering timing offset by shifting timing slots in response to timing offset occurring when a signal is sampled.

Abstract: Methods and apparatus are provided for detecting a loss of lock condition in a clock and data recovery system. A loss of lock condition is detected in a clock and data recovery system that generates a recovered clock signal from a received signal by sampling the received signal for a plurality of different phases using one or more latches clocked by the recovered clock; evaluating the samples to monitor a data eye associated with the received signal; and detecting the loss of lock condition if the data eye does not satisfy one or more predefined conditions. Generally, the predefined conditions identify a loss of the data eye (e.g, when the data eye cannot be substantially detected), for example, based on a degree of opening of the data eye. The clock and data recovery system can optionally be restarted if the loss of lock condition is detected.

Abstract: To synchronize time between network devices equally capable of accurately maintaining an indication of current time, one of the network devices is deemed to be a reference for time and the other network devices synchronize their indications of current time to the reference. To synchronize copies of data at multiple network devices, each network device maintains a counter representative of the passage of time but not necessarily of current time. The counter at each device is periodically synchronized with the counters of other network devices. When data is changed at a network device, the value of the counter at the time of changing is stored in association with the changed data. Stored counter values are used to determine whether a local copy or a remote copy of the data is likely more recent and therefore preferable. A further test may be applied if a counter value comparison is inconclusive.

Abstract: A signal receiving circuit includes: a sampler, for receiving an analog signal and sampling the analog signal according to a sampling clock to generate a sampling signal; an ADC, coupled to the sampler, for converting the sampling signal to a digital signal; an equalizer, coupled to the ADC, for equalizing the digital signal to generate an equalized digital signal; a quantizer, coupled to the equalizer for quantizing the equalized digital signal to generate a processed digital signal; and a timing recovery circuit, directly connected to the output terminal of the sampler and coupled to the quantizer, for adjusting the timing of the sampling clock according to the processed digital signal and the digital signal. Timing recovery parameter generating circuits are also disclosed.

Abstract: A system for implementing time stamp related features in a real time stamp distribution system is discussed. The distribution system derives a real time stamp (RTS) at a master timekeeping network element and distributes the RTS to associated network elements by way of a number of distribution techniques. Under certain network conditions, the real time stamp may not reach one or more of the network elements at the valid real time. In the present system, the network elements are able to derive a local time based on timing information recorded at the network element. Thus the system can detect an error in the time stamp delivered to a network element and can correct the time stamp utilizing a local time stamp feature.

Abstract: A wireless clock system includes a master clock or other master time source, and a plurality of slave clocks or repeater devices. Each slave clock can both wirelessly receive and wirelessly transmit time signals including current time data. To avoid conflicts among the slave clocks, each slave clock transmits time signals in a frequency-hopping manner over pseudo-randomized frequencies and at pseudo-randomized transmission start times. In another embodiment, power consumption at the slave clocks is minimized by activating and deactivating receivers within the slave clocks at predetermined times and at predetermined intervals, each interval being longer than the previous interval, until valid time signals are received from either the master clock or another slave clock. Calibration of the slave clock's time base is also performed.

Abstract: An OFDM frequency control device converts an incoming signal from analog to digital and calculates a correlation value between the guard interval and data part from which the guard interval is copied, of the A/D converted incoming signal. Then, the device averages such correlation values for the first frame through a plurality of frames and detects the peak of the averaged correlation value. Then, by detecting the phase of the peak position, the device generates the control signal for an oscillator. The control signal is set in such a way that a control amount for each time should be a control step ? and is applied to the oscillator. Furthermore, ? is appropriately controlled based on detected information.

Abstract: A control unit supplies a new control value to a frequency source. The value is determined by the frequency source frequency and the reference frequency. The control unit further calculates a rate of change value based at least on the new and a previous control value if there is communication with the reference frequency generator and stores these values in corresponding stores. Another control unit calculates a new control value based on the rate of change value from the rate of change store and the last used control value from the control value store and supplies the new control value to the frequency source if there is no communication with the reference generator.

Abstract: A signal supply apparatus for a public and private mobile communication system. The apparatus has Internet protocol base transceiver subsystems, and a private base station controller that controls the Internet protocol base transceiver subsystems. Instead of having a global positioning system receiver (GPSR) in each of the Internet protocol base transceiver subsystems to receive time of day (TOD) signals, the TOD signals are relayed to each of the Internet protocol base transceiver subsystems via a LAN cable. It is only the base station controllers that have the GPSR that receives the TOD signals. Then, these TOD signals are relayed from the base station controller to respective collective base station transceivers and then from each collective base station transceiver to their respective Internet protocol base transceiver subsystems via a LAN cable.

Abstract: Synchronous timing techniques provide redundant reference frequencies to enable a packet switching system to continuously generate one or more master clock frequencies when an original reference frequency is lost or unavailable.

Abstract: A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses.

Abstract: Disclosed is a SERDES circuit including a clock and data recovery circuit that allows operational margin in temporal and voltage directions to be measured, using a phase offset signal and a threshold voltage control signal, a pre-emphasis driver circuit and an equalizer circuit in order to reduce ISI on a transmission line, and an optimization control circuit for controlling the overall circuit. The optimization control circuit controls an equalizer control signal that is for adjusting characteristics of the equalizer circuit and a driver control signal that is for adjusting characteristics of the pre-emphasis driver circuit and sets the equalizer control signal and driver control signal so that the operational margin of the clock and data recovery circuit is maximized.

Abstract: A system and method for detecting a synchronization (sync) signal in a communication signal are disclosed. A received communication signal is stored in a memory and portions thereof are read from the memory and monitored to detect the sync signal. When a detected sync signal is determined to be invalid, previously read portions of the received communication signal, preferably beginning at a portion of the received signal immediately after a start of the detected sync signal, are again read and monitored to detect the sync signal. Such reading and monitoring of previously read portions of a received signal provide for recovery from so-called false triggering based on invalid sync signals.

Abstract: A redundant synchronous clock distribution system is provided comprising at least a first and a second clock module and first and second clock distribution branches adapted for synchronizing at least one clock slave module connected downstream to the redundant synchronous clock distribution system. Each of the first and second clock modules are adapted to act as a master clock module or a slave clock module. A clock switchover module is adapted to switch each of the first and second clock modules to change between the master mode and the slave mode. The clock switchover module comprises a flip-flop-circuit having a first circuit part and a second circuit part, wherein the first circuit part is located on the first clock module and the second circuit part is located on the second clock module.

Abstract: In one embodiment, a jitter detector comprises a logic circuit coupled to receive a plurality of inputs indicative of states captured from a plurality of outputs of a delay chain responsive to a first clock input and a plurality of clocked storage devices coupled to the logic circuit. The logic circuit is configured to identify a first input of the plurality of inputs that is: (i) captured in error from a corresponding one of the plurality of outputs of the delay chain, and (ii) the corresponding one of the plurality of outputs of the delay chain is least delayed by the delay chain among the plurality of outputs that are captured in error. The plurality of clocked storage devices are configured to accumulate an indication of which of the plurality of outputs have been captured in error over a plurality of clock cycles of the first clock input.

Abstract: A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce said signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. The signal is capable of being represented as a series of characters. A character is capable of being represented as a first data bit, a second data bit, and a control bit. A first interconnect is configured to convey the first data bit. A second interconnect is configured to convey the second data bit. A third interconnect is configured to convey the control bit. The third interconnect is positioned substantially between the first interconnect and the second interconnect.

Abstract: A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce the signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. Preferably, the destination port is in a first cross link multiplexer, the origin port is in a second cross link multiplexer, and the first cross link multiplexer is configured to convey the signal toward the second cross link multiplexer in more than one direction. In an embodiment, the signal is capable of being represented as a series of characters, and a character is capable of being represented as a number of bits. Preferably, the plurality of cross link multiplexers includes a delay buffer to delay conveyance of a first bit so that it remains substantially synchronized with a second bit.

Abstract: Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.

Abstract: Systems and methods for transferring data across clock domains in a manner that avoids metastability of the data and is very tolerant of variations in the clock signals of the different clock domains. One embodiment of the invention comprises a mechanism for passing data from a first clock to a second clock domain in a digital pulse width modulated (PWM) amplification system. In this embodiment, parallel data is generated in the process of converting PCM data to PWM data. The parallel data is processed in a clock domain having a first clock rate and is passed to a second clock domain having a clock rate that is twice the rate of the first clock domain. The parallel data is then serialized at the higher clock rate of the second clock domain.

Abstract: A time information receiver and radio controlled watch that receives a time code in which different data pulses are disposed one in a unit period. A composite signal waveform of a plurality of detected signals of the time code shifted sequentially by a unit period of 1 second is obtained by sample adders. A start point of each unit period is detected from the composite signal waveform as a seconds synchronization point where the receiver and watch is seconds-synchronized with the time code. An accurate seconds synchronization point is detected from the detected signal even when the same includes a considerable noise (FIG. 4).

Abstract: An apparatus and method for WGIO phase modulation are described. In one embodiment, the method includes the receipt of a high-speed data stream, encoded according to an 8b/10b code. Once received, a symbol rate of the data stream is reduced by a predetermined amount. Finally, once the symbol rate is reduced, a square wave carrier is phase modulated, using the reduced data rate data stream to generate a WGIO signal having double side band spectrum distributed either side of the square wave carrier. Accordingly, in one embodiment, a 3GIO signal may be phase modulated in order to fall within a spectrum that is not currently occupied by a wireless protocol, including, for example, Wireless Local Area Network (WLAN), Wireless Wide Area Networks (WWAN), global positioning systems (GPS), or the like in order to prevent interference therebetween.

Abstract: In a method and a circuit for timing pulse generation, a frame pulse of a corresponding system is masked when an alarm signal of either a working system or a protection system is received, a monitoring window which indicates an absorbable range of delay time difference between the frame pulses is generated upon an arrival of the frame pulse of the system selected by a switching signal, when the alarm signal of a system not selected is generated upon selection of the switching signal. Alternatively, a request signal for regenerating the monitoring window which indicates an absorbable range of delay time difference between the frame pulses is provided upon an arrival of the frame pulse of the system selected by the switching signal, when a slip signal is generated upon selection of the switching signal.

Abstract: A device (D2) is dedicated to the reconstruction of clock signals, for example within communication equipment (EQ2) of an IP network. This device (D2) comprises i) a phase-locked loop (BV) having a cut-off frequency dependent, on the one hand, on a configuration value making it possible to reconstruct clock signals according to a chosen clock frequency, and on the other hand, a chosen sampling frequency, and ii) control means (MC2) responsible for forcing the phase-locked loop (BV) to present a variable cut-off frequency according to a received operating mode indication.

Abstract: The invention concerns a method for synchronising clocks of base transceiver stations in a telecommunications system and a mobile communications system. According to the invention, in either some or in all base station sites of the telecommunications network a location measurement unit is installed, which receives an accurate clock including an extra-system signal. The clock information is transmitted further to base transceiver stations, whose frame transmissions are synchronised in accordance with the clock information. By using the implementation in accordance with the invention both economic and functional advantages are achieved, e.g. the capacity can be increased by up to 50-300%, depending on the manner of implementation.

Abstract: A method for effecting synchronous pulse generation for use in serial communications is provided. The method includes the steps of generating a difference signal representing a signal level difference between at least two data stream signals; providing a clock signal; providing a counter, defining a sample count value of the counter; incrementing the counter in relation to the clock signal; and determining whether a current count value of the counter corresponds to the sample count value. If the current count value corresponds to the sample count value, then the method performs a step of generating a synchronous pulse.

Abstract: A frequency synchronization method comprise a first step of detecting a frequency error which occurs when a high-frequency receiving signal is converted into a digital signal of a base-band, performing rounding or discarding processing and generating a local oscillation signal depending on the converted analog signals, a second step of generating a digital signal whose frequency depending on a discard component obtained by the rounding or discarding processing when the rounding or discarding processing is performed, and a third step of canceling a frequency component of the digital signal which is generated by the second step from a frequency component of the digital signal of the base-band.

Abstract: A method of synchronizing data in a communications system includes generating a composite signal comprising a serial stream of data partitioned in one or more frames, and transmitting the composite signal to a receiver. Multiphase clock signals are generated. The composite signal received at the receiver is compared with each of the multiphase clock signals until either sustained coincidence therebetween is achieved or sustained non-coincidence is achieved, thereby synchronizing the receiver to bit boundaries in the composite signal and to one or more of the clock phase signals. One or more bit templates at the receiver is correlated with one or more corresponding bit templates in the composite signal received at the receiver to determine where frames start in the composite signal, thereby synchronizing the receiver to the one or more frames in the composite signal.

Abstract: A versatile, programmable, low-cost transmit line driver is provided. The line driver includes a digital-to-analog converter that receives a digital input and provides an analog output. The line driver is reconfigurable between the voltage mode of operation.

Abstract: A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the DRR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.

Abstract: The invention relates to a method and system for adjusting a clock signal placed in a network element of a data network. The clock signal is adjusted on the basis of difference values formed by means of received synchronizing messages. Each difference value is a difference of a reception time value and a transmission value of a received synchronizing message. The reception time value of the synchronizing message depends on a cumulated number of periods of the clock signal at a moment of arrival of the synchronizing message, and the transmission value depends on a position of the synchronizing message in a chronological transmission order of the synchronizing messages. In the adjusting process, an adjusting effect of the difference values belonging to a lower part (304) of a margin of fluctuation (306) of the difference values is weighted more heavily than an adjusting effect of the difference values belonging to an upper part (305) of the margin of fluctuation of the difference values.

Abstract: Both a pre-word (PW) and a sync word (SW) are used to establish a synchronization or only the sync word (SW) is used to establish a synchronization in accordance with an operational status related to the synchronization in a mobile wireless communication apparatus. For example, during an initial synchronization with a control channel (110) being received, both the pre-word (PW) and the sync word (SW) are used to establish a synchronization when a calculation result in a synchronization calculating part exceeds a predetermined threshold value only once. During an initial synchronization with a direct communication channel (112) being received, both the pre-word (PW) and the sync word (SW) are used to establish a synchronization when the calculation result exceeds the predetermined threshold value once; or alternatively, only the sync word (SW) is used to establish a synchronization when the calculation result successively exceeds the predetermined threshold value twice.